Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques [9053-10] (Englisch)
- Neue Suche nach: Chen, Y.
- Neue Suche nach: Zhou, J.
- Neue Suche nach: You, J.
- Neue Suche nach: Liu, H.
- Neue Suche nach: SPIE (Society)
- Neue Suche nach: Chen, Y.
- Neue Suche nach: Zhou, J.
- Neue Suche nach: You, J.
- Neue Suche nach: Liu, H.
- Neue Suche nach: Sturtevant, John L.
- Neue Suche nach: Capodieci, Luigi
- Neue Suche nach: SPIE (Society)
In:
Design-process-technology co-optimization for manufacturability
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9053 0B
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2014
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Print
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Titel:Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques [9053-10]
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Beteiligte:Chen, Y. ( Autor:in ) / Zhou, J. ( Autor:in ) / You, J. ( Autor:in ) / Liu, H. ( Autor:in ) / Sturtevant, John L. / Capodieci, Luigi / SPIE (Society)
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Kongress:Conference; 8th, Design-process-technology co-optimization for manufacturability ; 2013 ; San Jose, CA
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Erschienen in:PROCEEDINGS- SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING ; 9053 ; 9053 0B
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Verlag:
- Neue Suche nach: SPIE
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Erscheinungsort:Bellingham, Washington
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Erscheinungsdatum:01.01.2014
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Format / Umfang:9053 0B
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Anmerkungen:Includes bibliographical referencesand index.
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
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Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 90530A
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A fast triple patterning solution with fix guidanceFang, Weiping / Arikati, Srini / Cilingir, Erdem / Hug, Marco A. / De Bisschop, Peter / Mailfert, Julien / Lucas, Kevin / Gao, Weimin et al. | 2014
- 90530B
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Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniquesChen, Yijian / Zhou, Jun / You, Jun / Liu, Hongyi et al. | 2014
- 90530C
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Self-aligned quadruple patterning-aware routingNakajima, Fumiharu / Kodama, Chikaaki / Ichikawa, Hirotaka / Nakayama, Koichi / Nojima, Shigeki / Kotani, Toshiya et al. | 2014
- 90530E
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Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clusteringGao, Jhih-Rong / Yu, Bei / Pan, David Z. et al. | 2014
- 90530F
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Model based multilayers fix for litho hotspots beyond 20nm nodeRabie, Asmaa / Madkour, Kareem / George, Kirolos / ElManhawy, Wael / Brunet, Jean-Marie / Kwan, Joe et al. | 2014
- 90530G
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Configurable hot spot fixing systemKajiwara, Masanari / Kobayashi, Sachiko / Mashita, Hiromitsu / Aburada, Ryota / Furuta, Nozomu / Kotani, Toshiya et al. | 2014
- 90530H
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"Smart" source, mask, and target co-optimization to improve design related lithographically weak spotsChung, No-Young / Kang, Pil-Soo / Bang, Na-Rae / Kim, Jong-Du / Lee, Suk-Ju / Choi, Byung-Il / Choi, Bong-Ryoul / Park, Sung-Woon / Baik, Ki-Ho / Hsu, Stephen et al. | 2014
- 90530I
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Layout induced variability and manufacturability checks in FinFETs processBan, Yongchan / Sweis, Jason / Hurat, Philippe / Lai, Ya-Chieh / Kang, Yongseok / Paik, Woo Hyun / Xu, Wei / Song, Huiyuan et al. | 2014
- 90530J
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Layout optimization of DRAM cells using rigorous simulation model for NTDJeon, Jinhyuck / Kim, Shinyoung / Park, Chanha / Yang, Hyunjo / Yim, Donggyu / Kuechler, Bernd / Zimmermann, Rainer / Muelders, Thomas / Klostermann, Ulrich / Schmoeller, Thomas et al. | 2014
- 90530M
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Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulationsGómez, Sergio / Moll, Francesc / Mauricio, Juan et al. | 2014
- 90530N
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Technology-design-manufacturing co-optimization for advanced mobile SoCsYang, Da / Gan, Chock / Chidambaram, P. R. / Nallapadi, Giri / Zhu, John / Song, S. C. / Xu, Jeff / Yeap, Geoffrey et al. | 2014
- 90530O
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Optimizing standard cell design for qualityYuan, Chimin / Tipple, Dave / Warner, Jeff et al. | 2014
- 90530P
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Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)Ban, Yongchan / Choi, Changseok / Shin, Hosoon / Kang, Yongseok / Paik, Woo Hyun et al. | 2014
- 90530Q
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Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAMVandewalle, Boris / Chava, Bharani / Sakhare, Sushil / Ryckaert, Julien / Dusa, Mircea et al. | 2014
- 90530R
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Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processesTorres, J. Andres / Sakajiri, Kyohei / Fryer, David / Granik, Yuri / Ma, Yuansheng / Krasnova, Polina / Fenger, Germain / Nagahara, Seiji / Kawakami, Shinichiro / Rathsack, Benjamen et al. | 2014
- 90530S
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ECO fill: automated fill modification to support late-stage design changesDavis, Greg / Wilson, Jeff / Yu, J. J. / Chiu, Anderson / Chuang, Yao-Jen / Yang, Ricky et al. | 2014
- 90530T
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Yield-aware decomposition for LELE double patterningKohira, Yukihide / Yokoyama, Yoko / Kodama, Chikaaki / Takahashi, Atsushi / Nojima, Shigeki / Tanaka, Satoshi et al. | 2014
- 90530U
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A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation methodCheng, Qi / You, Jun / Chen, Yijian et al. | 2014
- 90530V
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Localization concept of re-decomposition area to fix hotspots for LELE processYokoyama, Yoko / Sakanushi, Keishi / Kohira, Yukihide / Takahashi, Atsushi / Kodama, Chikaaki / Tanaka, Satoshi / Nojima, Shigeki et al. | 2014
- 90530W
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Decomposition-aware layout optimization for 20/14nm standard cellsWang, Lynn T. -. / Madhavan, Sriram / Malik, Shobhit / Chiu, Eric / Capodieci, Luigi et al. | 2014
- 90530X
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Resist profile aware source mask optimizationChen, Ao / Foong, Yee Mei / Hsieh, Michael / Khoh, Andrew / Hsu, Stephen / Feng, Mu / Qiu, Jianhong / Aquino, Chris et al. | 2014
- 90530Z
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Robust and automated solution for correcting hotspots locally using cost-function based OPC solverBabcock, Carl / Yang, Dongok / McGowan, Sarah / Ye, Jun / Yan, Bo / Qiu, Jianhong / Baron, Stanislas / Pandey, Taksh / Kapasi, Sanjay / Aquino, Chris et al. | 2014
- 905301
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Front Matter: Volume 9053| 2014
- 905302
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Lithography-induced limits to scaling of design qualityKahng, Andrew B. et al. | 2014
- 905303
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A pattern-driven design regularization methodologyCain, Jason P. / Rodriguez, Norma P. / Sweis, Jason / Gennari, Frank E. / Lai, Ya-Chieh et al. | 2014
- 905304
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Systematic physical verification with topological patternsDai, Vito / Lai, Ya-Chieh / Gennari, Frank / Teoh, Edward / Capodieci, Luigi et al. | 2014
- 905305
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Synthesis of lithography test patterns through topology-oriented pattern extraction and classificationShim, Seongbo / Chung, Woohyun / Shin, Youngsoo et al. | 2014
- 905306
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Systematic data mining using a pattern database to accelerate yield rampTeoh, Edward / Dai, Vito / Capodieci, Luigi / Lai, Ya-Chieh / Gennari, Frank et al. | 2014
- 905307
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Layout pattern-driven design rule evaluationBadr, Yasmine / Ma, Ko-wei / Gupta, Puneet et al. | 2014
- 905308
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Bridging the gap from mask to physical design for multiple patterning lithographyYu, Bei / Gao, Jhih-Rong / Xu, Xiaoqing / Pan, David Z. et al. | 2014
- 905309
-
Demonstrating production quality multiple exposure patterning aware routing for the 10NM nodeLiebmann, Lars / Gerousis, Vassilios / Gutwin, Paul / Zhang, Mike / Han, Geng / Cline, Brian et al. | 2014
- 905310
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A layout decomposition algorithm for self-aligned multiple patterningYou, Jun / Liu, Hongyi / Chen, Yijian et al. | 2014
- 905311
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Work smarter not harder: How to get more results with less modelingMadkour, Kareem / Pikus, Fedor / Anis, Mohab et al. | 2014
- 905312
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Scanner correction capabilities aware CMP lithography hotspot analysisKatakamsetty, Ushasree / Colin, Hui / Yeo, Sky / Valerio, Perez / Qing, Yang / Fong, Quek Shyue / Aravind, Narayana Samy / Matthias, Ruhm / Roberto, Schiwon et al. | 2014
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Systematic physical verification with topological patterns [9053-3]Dai, V. / Lai, Y.-C. / Gennari, F. / Teoh, E. / Capodieci, L. / SPIE (Society) et al. | 2014
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Layout pattern-driven design rule evaluation [9053-6]Badr, Y. / Ma, K. / Gupta, P. / SPIE (Society) et al. | 2014
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``Smart'' source, mask, and target co-optimization to improve design related lithographically weak spots [9053-16]Chung, N.-Y. / Kang, P.-S. / Bang, N.-R. / Kim, J.-D. / Lee, S.-J. / Choi, B.-I. / Choi, B.-R. / Park, S.-W. / Baik, K.-H. / Hsu, S. et al. | 2014
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Yield-aware decomposition for LELE double patterning [9053-29]Kohira, Y. / Yokoyama, Y. / Kodama, C. / Takahashi, A. / Nojima, S. / Tanaka, S. / SPIE (Society) et al. | 2014
-
Localization concept of re-decomposition area to fix hotspots for LELE process [9053-31]Yokoyama, Y. / Sakanushi, K. / Kohira, Y. / Takahashi, A. / Kodama, C. / Tanaka, S. / Nojima, S. / SPIE (Society) et al. | 2014
-
Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clustering [9053-13]Gao, J.-R. / Yu, B. / Pan, D.Z. / SPIE (Society) et al. | 2014
-
Decomposition-aware layout optimization for 20/14nm standard cells [9053-32]Wang, L.T.-N. / Madhavan, S. / Malik, S. / Chiu, E. / Capodieci, L. / SPIE (Society) et al. | 2014
-
A pattern-driven design regularization methodology [9053-2]Cain, J.P. / Rodriguez, N.P. / Sweis, J. / Gennari, F.E. / Lai, Y.-C. / SPIE (Society) et al. | 2014
-
Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques [9053-10]Chen, Y. / Zhou, J. / You, J. / Liu, H. / SPIE (Society) et al. | 2014
-
Technology-design-manufacturing co-optimization for advanced mobile SoCs (Invited Paper) [9053-23]Yang, D. / Gan, C. / Chidambaram, P.R. / Nallapadi, G. / Zhu, J. / Song, S.C. / Xu, J. / Yeap, G. / SPIE (Society) et al. | 2014
-
Resist profile aware source mask optimization [9053-33]Chen, A. / Foong, Y.M. / Hsieh, M. / Khoh, A. / Hsu, S. / Feng, M. / Qiu, J. / Aquino, C. / SPIE (Society) et al. | 2014
-
Self-aligned quadruple patterning-aware routing [9053-11]Nakajima, F. / Kodama, C. / Ichikawa, H. / Nakayama, K. / Nojima, S. / Kotani, T. / SPIE (Society) et al. | 2014
-
Configurable hot spot fixing system [9053-15]Kajiwara, M. / Kobayashi, S. / Mashita, H. / Aburada, R. / Furuta, N. / Kotani, T. / SPIE (Society) et al. | 2014
-
Bridging the gap from mask to physical design for multiple patterning lithography (Invited Paper) [9053-7]Yu, B. / Gao, J.-R. / Xu, X. / Pan, D.Z. / SPIE (Society) et al. | 2014
-
Systematic data mining using a pattern database to accelerate yield ramp [9053-5]Teoh, E. / Dai, V. / Capodieci, L. / Lai, Y.-C. / Gennari, F. / SPIE (Society) et al. | 2014
-
Layout induced variability and manufacturability checks in FinFETs process [9053-17]Ban, Y. / Sweis, J. / Hurat, P. / Lai, Y. / Kang, Y. / Paik, W. / Xu, W. / Song, H. / SPIE (Society) et al. | 2014
-
Layout optimization of DRAM cells using rigorous simulation model for NTD [9053-19]Jeon, J. / Kim, S. / Park, C. / Yang, H. / Yim, D. / Kuechler, B. / Zimmermann, R. / Muelders, T. / Klostermann, U. / Schmoeller, T. et al. | 2014
-
Synthesis of lithography test patterns through topology-oriented pattern extraction and classification [9053-4]Shim, S. / Chung, W. / Shin, Y. / SPIE (Society) et al. | 2014
-
Model based multilayers fix for litho hotspots beyond 20nm node [9053-14]Rabie, A. / Madkour, K. / George, K. / ElManhawy, W. / Brunet, J.-M. / Kwan, J. / SPIE (Society) et al. | 2014
-
Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes [9053-27]Torres, J.A. / Sakajiri, K. / Fryer, D. / Granik, Y. / Ma, Y. / Krasnova, P. / Fenger, G. / Nagahara, S. / Kawakami, S. / Rathsack, B. et al. | 2014
-
Lithography-induced limits to scaling of design quality (Invited Paper) [9053-1]Kahng, A.B. / SPIE (Society) et al. | 2014
-
Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations [9053-36]Gomez, S. / Moll, F. / Mauricio, J. / SPIE (Society) et al. | 2014
-
Optimizing standard cell design for quality [9053-24]Yuan, C. / Tipple, D. / Warner, J. / SPIE (Society) et al. | 2014
-
ECO fill: automated fill modification to support late-stage design changes [9053-28]Davis, G. / Wilson, J. / Yu, J.J. / Chiu, A. / Chuang, Y.-J. / Yang, R. / SPIE (Society) et al. | 2014
-
Work smarter not harder: How to get more results with less modeling [9053-38]Madkour, K. / Pikus, F. / Anis, M. / SPIE (Society) et al. | 2014
-
Robust and automated solution for correcting hotspots locally using cost-function based OPC solver [9053-35]Babcock, C. / Yang, D. / McGowan, S. / Ye, J. / Yan, B. / Qiu, J. / Baron, S. / Pandey, T. / Kapasi, S. / Aquino, C. et al. | 2014
-
Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip) [9053-25]Ban, Y. / Choi, C. / Shin, H. / Kang, Y. / Paik, W. / SPIE (Society) et al. | 2014
-
A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method [9053-30]Cheng, Q. / You, J. / Chen, Y. / SPIE (Society) et al. | 2014
-
A layout decomposition algorithm for self-aligned multiple patterning [9053-37]You, J. / Liu, H. / Chen, Y. / SPIE (Society) et al. | 2014
-
Scanner correction capabilities aware CMP lithography hotspot analysis [9053-39]Katakamsetty, U. / Colin, H. / Yeo, S. / Valerio, P. / Qing, Y. / Fong, Q.S. / Aravind, N.S. / Matthias, R. / Roberto, S. / SPIE (Society) et al. | 2014
-
Demonstrating production quality multiple exposure patterning aware routing for the 10NM node [9053-8]Liebmann, L. / Gerousis, V. / Gutwin, P. / Zhang, M. / Han, G. / Cline, B. / SPIE (Society) et al. | 2014
-
A fast triple patterning solution with fix guidance [9053-9]Fang, W. / Arikati, S. / Cilingir, E. / Hug, M.A. / De Bisschop, P. / Mailfert, J. / Lucas, K. / Gao, W. / SPIE (Society) et al. | 2014
-
Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM [9053-26]Vandewalle, B. / Chava, B. / Sakhare, S. / Ryckaert, J. / Dusa, M. / SPIE (Society) et al. | 2014