Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs (Englisch)
- Neue Suche nach: Xuechao Wei,
- Neue Suche nach: Cody Hao Yu,
- Neue Suche nach: Peng Zhang,
- Neue Suche nach: Youxiang Chen,
- Neue Suche nach: Yuxin Wang,
- Neue Suche nach: Han Hu,
- Neue Suche nach: Yun Liang,
- Neue Suche nach: Cong, Jason
- Neue Suche nach: Xuechao Wei,
- Neue Suche nach: Cody Hao Yu,
- Neue Suche nach: Peng Zhang,
- Neue Suche nach: Youxiang Chen,
- Neue Suche nach: Yuxin Wang,
- Neue Suche nach: Han Hu,
- Neue Suche nach: Yun Liang,
- Neue Suche nach: Cong, Jason
In:
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)
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1-6
;
2017
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ISBN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
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Beteiligte:Xuechao Wei, ( Autor:in ) / Cody Hao Yu, ( Autor:in ) / Peng Zhang, ( Autor:in ) / Youxiang Chen, ( Autor:in ) / Yuxin Wang, ( Autor:in ) / Han Hu, ( Autor:in ) / Yun Liang, ( Autor:in ) / Cong, Jason ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.06.2017
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Format / Umfang:6585845 byte
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
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Toward optimal legalization for mixed-cell-height circuit designsChen, Jianli / Ziran Zhu, / Zhu, Wenxing / Chang, Yao-Wen et al. | 2017
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Fixed-parameter tractable algorithms for optimal layout decomposition and beyondKuang, Jian / Young, Evangeline F. Y. et al. | 2017
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Minimizing cluster number with clip shifting in hotspot pattern classificationKuan-Jung Chen, / Yu-Kai Chuang, / Bo-Yi Yu, / Shao-Yun Fang, et al. | 2017
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PriSearch: Efficient search on private dataRiazi, M. Sadegh / Songhori, Ebrahim M. / Koushanfar, Farinaz et al. | 2017
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SmartSwap: High-performance and user experience friendly swapping in mobile systemsZhu, Xiao / Liu, Duo / Zhong, Kan / Jinting Ren, / Li, Tao et al. | 2017
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RESPARC: A reconfigurable and energy-efficient architecture with Memristive Crossbars for deep Spiking Neural NetworksAnkit, Aayush / Sengupta, Abhronil / Panda, Priyadarshini / Roy, Kaushik et al. | 2017
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A new paradigm for synthesis of linear decompressorsGizdarski, Emil / Wohl, Peter / Waicukauski, John et al. | 2017
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Test methodology for dual-rail asynchronous circuitsHuang, Kuan-Yen / Shen, Ting-Yu / Li, Chien-Mo et al. | 2017
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Enabling write-reduction strategy for journaling file systems over byte-addressable NVRAMChen, Tseng-Yi / Chang, Yuan-Hao / Chen, Shuo-Han / Kuo, Chih-Ching / Yang, Ming-Chang / Wei, Hsin-Wen / Shih, Wei-Kuan et al. | 2017
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Transport or store? Synthesizing flow-based microfluidic biochips using distributed channel storageLiu, Chunfeng / Li, Bing / Yao, Hailong / Pop, Paul / Ho, Tsung-Yi / Schlichtmann, Ulf et al. | 2017
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Invited: Accelerator design for deep learning trainingAgrawal, Ankur / Chia-Yu Chen, / Jungwook Choi, / Gopalakrishnan, Kailash / Jinwook Oh, / Shukla, Sunil / Srinivasan, Viji / Venkataramani, Swagath / Zhang, Wei et al. | 2017
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Power and area efficient hold time fixing by free metal segment allocationChiu, Wei-Lun / Jiang, Iris Hui-Ru / Lu, Chien-Pang / Chang, Yu-Tung et al. | 2017
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LSTA: Learning-based static timing analysis for high-dimensional correlated on-chip variationsBian, Song / Hiromoto, Masayuki / Shintani, Michihiro / Sato, Takashi et al. | 2017
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Table of contents| 2017
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In quest of the next information processing substrateDatta, Suman / Seabaugh, Alan / Niemier, Michael / Raychowdhury, Arijit / Schlom, Darrell / Jena, Debdeep / Xing, Grace / Wong, H. -S. Philip / Pop, Eric / Salahuddin, Sayeef et al. | 2017
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FlexCL: An analytical performance model for OpenCL workloads on flexible FPGAsWang, Shuo / Liang, Yun / Wei Zhang, et al. | 2017
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Analyzing hardware based malware detectorsPatel, Nisarg / Sasan, Avesta / Homayoun, Houman et al. | 2017
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Learning to produce direct tests for security verification using constrained process discoveryKuo-Kai Hsieh, / Wang, Li-C. / Wen Chen, / Bhadra, Jayanta et al. | 2017
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Energy-efficient execution for repetitive app usages on big.LITTLE architecturesLi, Xianfeng / Guikang Chen, / Wen Wen, et al. | 2017
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HALWPE: Hardware-assisted light weight performance estimation for GPUsO'Neal, Kenneth / Brisk, Philip / Shriver, Emily / Kishinevsky, Michael et al. | 2017
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INVITED: Safety guard: Runtime enforcement for safety-critical cyber-physical systemsWu, Meng / Zeng, Haibo / Wang, Chao / Yu, Huafeng et al. | 2017
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FFD: A framework for fake flash detectionZimu Guo, / Xu, Xiaolin / Tehranipoor, Mark M. / Forte, Domenic et al. | 2017
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Improving performance and lifetime of large-page NAND storages using erase-free subpage programmingMyungsuk Kim, / Jaehoon Lee, / Lee, Sungjin / Jisung Park, / Kim, Jihong et al. | 2017
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InCheck: An in-application recovery scheme for soft errorsDidehban, Moslem / Lokam, Sai Ram Dheeraj / Shrivastava, Aviral et al. | 2017
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Phase-driven learning-based dynamic reliability management for multi-core processorsZhiyuan Yang, / Serafy, Caleb / Tiantao Lu, / Srivastava, Ankur et al. | 2017
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A fast and power efficient architecture to parallelize LSTM based RNN for cognitive intelligence applicationsPeng Ouyang, / Shouyi Yin, / Shaojun Wei, et al. | 2017
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A kernel decomposition architecture for binary-weight Convolutional Neural NetworksHyeonuk Kim, / Jaehyeong Sim, / Yeongjae Choi, / Lee-Sup Kim, et al. | 2017
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Hierarchical reversible logic synthesis using LUTsSoeken, Mathias / Roetteler, Martin / Wiebe, Nathan / De Micheli, Giovanni et al. | 2017
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Rescuing memristor-based neuromorphic design with high defectsLiu, Chenchen / Hu, Miao / Strachan, John Paul / Li, Hai et al. | 2017
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Copyright page| 2017
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Secure information flow verification with mutable dependent typesFerraiuolo, Andrew / Weizhe Hua, / Myers, Andrew C. / Suh, G. Edward et al. | 2017
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Invited: ESL design in SystemC AMSBarnasconi, Martin / Adhikari, Sumit et al. | 2017
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Leveraging compiler optimizations to reduce runtime fault recovery overheadHosseini, Fateme S. / Fotouhi, Pouya / Yang, Chengmo / Gao, Guang R. et al. | 2017
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Automated systolic array architecture synthesis for high throughput CNN inference on FPGAsXuechao Wei, / Cody Hao Yu, / Peng Zhang, / Youxiang Chen, / Yuxin Wang, / Han Hu, / Yun Liang, / Cong, Jason et al. | 2017
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Hierarchical dataflow modeling of iterative applicationsHyesun Hong, / Hyunok Oh, / Soonhoi Ha, et al. | 2017
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Towards aging-induced approximationsAmrouch, Hussam / Khaleghi, Behnam / Gerstlauer, Andreas / Henkel, Jorg et al. | 2017
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Power-aware performance tuning of GPU applications through microbenchmarkingBombieri, Nicola / Busato, Federico / Fummi, Franco et al. | 2017
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Exploiting thread and data level parallelism for ultimate parallel SystemC simulationSchmidt, Tim / Liu, Guantao / Domer, Rainer et al. | 2017
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INVITED: Specification, verification and design of evolving automotive softwareRamesh, S. / Vogel-Heuser, Birgit / Chang, Wanli / Roy, Debayan / Licong Zhang, / Chakraborty, Samarjit et al. | 2017
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Component-oriented high-level synthesis for continuous-flow microfluidics considering hybrid-schedulingLi, Mengchu / Tseng, Tsun-Ming / Li, Bing / Ho, Tsung-Yi / Schlichtmann, Ulf et al. | 2017
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Design of an energy-efficient accelerator for training of convolutional neural networks using frequency-domain computationJong Hwan Ko, / Mudassar, Burhan / Na, Taesik / Mukhopadhyay, Saibal et al. | 2017
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Boosting the performance of 3D charge trap NAND flash with asymmetric feature process size characteristicChen, Shuo-Han / Chen, Yen-Ting / Wei, Hsin-Wen / Shih, Wei-Kuan et al. | 2017
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A novel ReRAM-based main memory structure for optimizing access latency and reliabilityYang Zhang, / Dan Feng, / Jingning Liu, / Wei Tong, / Bing Wu, / Caihua Fang, et al. | 2017