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Inhaltsverzeichnis – Band 24, Ausgabe 10

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1485
A method for generating structurally aligned grids for semiconductor device simulation
Heitzinger, C. / Sheikholeslami, A. / Jong Mun Park, / Selberherr, S. | 2005
1485
Device Simulation - A Method for Generating Structurally Aligned Grids for Semiconductor Device Simulation
Heitzinger, C. / Sheikholeslami, A. / Park, J.M. / Selberherr, S. | 2005
1492
Quasi-static scheduling of independent tasks for reactive systems
Cortadella, J. / Kondratyev, A. / Lavagno, L. / Passerone, C. / Watanabe, Y. | 2005
1492
Embedded Systems - Quasi-Static Scheduling of Independent Tasks for Reactive Systems
Cortadella, J. / Kondratyev, A. / Lavagno, L. / Passerone, C. / Watanabe, Y. | 2005
1515
Combining ordered best-first search with branch and bound for exact BDD minimization
Ebendt, R. / Gunther, W. / Drechsler, R. | 2005
1515
Logic Synthesis - Combining Ordered Best-First Search With Branch and Bound for Exact BDD Minimization
Ebendt, R. / Günther, W. / Drechsler, R. | 2005
1530
Low Power Design - Intra-Task Voltage Scheduling on DVS-Enabled Hard Real-Time Systems
Shin, D. / Kim, J. | 2005
1530
Intra-task voltage scheduling on DVS-enabled hard real-time systems
Dongkun Shin, / Jihong Kim, | 2005
1550
A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line
Pesic, T.V. / Jankovic, N.D. | 2005
1550
Modeling - A Compact Nonquasi-Static MOSFET Model Based on the Equivalent Nonlinear Transmission Line
Pesic, T.V. / Jankovic, N.D. | 2005
1562
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates
Rong Jiang, / Wenyin Fu, / Charlie Chung-Ping Chen, | 2005
1562
Parasitic Extraction - EPEEC: Comprehensive SPICE-Compatible Reluctance Extraction for High-Speed Interconnects Above Lossy Multilayer Substrates
Jiang, R. / Fu, W. / Chen, C.C.-P. | 2005
1572
Resource allocation for coarse-grain FPGA development
Eguro, K. / Hauck, S.A. | 2005
1572
Reconfigurable Systems - Resource Allocation for Coarse-Grain FPGA Development
Eguro, K. / Hauck, S.A. | 2005
1582
Testing - Schematic Array Models for Associative and Non-Associative Memory Circuits
Bose, S. / Nandi, A. | 2005
1582
Schematic array models for associative and non-associative memory circuits
Bose, S. / Nandi, A. | 2005
1594
On reducing test application time for scan circuits using limited scan operations and transfer sequences
Yonsang Cho, / Pomeranz, I. / Reddy, S.M. | 2005
1594
Testing - On Reducing Test Application Time for Scan Circuits Using Limited Scan Operations and Transfer Sequences
Cho, Y. / Pomeranz, I. / Reddy, S.M. | 2005
1606
Fault diagnosis and logic debugging using Boolean satisfiability
Smith, A. / Veneris, A. / Ali, M.F. / Viglas, A. | 2005
1606
Testing - Fault Diagnosis and Logic Debugging Using Boolean Satisfiability
Smith, A. / Veneris, A. / Fahim Ali, M. / Viglas, A. | 2005
1622
An efficient heterogeneous tree multiplexer synthesis technique
Hsu-Wei Huang, / Cheng-Yeh Wang, / Jing-Yang Jou, | 2005
1622
SHORT PAPERS - An Efficient Heterogeneous Tree Multiplexer Synthesis Technique
Huang, H.-W. / Wang, C.-Y. / Jou, J.-Y. | 2005
1629
Evaluating the reliability of NAND multiplexing with PRISM
Norman, G. / Parker, D. / Kwiatkowska, M. / Shukla, S. | 2005
1629
SHORT PAPERS - Evaluating the Reliability of NAND Multiplexing With PRISM
Norman, G. / Parker, D. / Kwiatkowska, M. / Shukla, S. | 2005
1637
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree
Saaied, H. / Al-Khalili, D. / Al-Khalili, A.J. / Nekili, M. | 2005
1637
SHORT PAPERS - Simultaneous Adaptive Wire Adjustment and Local Topology Modification for Tuning a Bounded-Skew Clock Tree
Saaied, H. / Al-Khalili, D. / Al-Khalili, A.J. / Nekili, M. | 2005
1644
2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)
| 2005
1644
ANNOUNCEMENTS - Call for Papers: IEEE ISCAS 2006
| 2005
c1
Table of contents
| 2005
c2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information
| 2005
c3
IEEE Circuits and Systems Society Information
| 2005
c4
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors
| 2005

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