Gate Sizing with Controlled Displacement (English)
- New search for: Chen, W.
- New search for: Hsieh, C.-T.
- New search for: Pedram, M.
- New search for: ACM
- New search for: Chen, W.
- New search for: Hsieh, C.-T.
- New search for: Pedram, M.
- New search for: ACM
In:
Physical design
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127-132
;
1999
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ISBN:
- Conference paper / Print
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Title:Gate Sizing with Controlled Displacement
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Contributors:
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Conference:International symposium, Physical design ; 1999 ; Monterey, CA
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Published in:Physical design ; 127-132
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Publisher:
- New search for: ACM
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Publication date:1999-01-01
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Size:6 pages
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Remarks:Also known as ISPD-99
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ISBN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 4
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The Deep Sub-micron Signal Integrity ChallengeKirkpatrick, D. / ACM et al. | 1999
- 9
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Methodology to Analyze Power, Voltage Drop and Their Effects on Clock Skew/Delay in Early Stages of DesignIwabuchi, M. / Sakamoto, N. / Sekine, Y. / Omachi, T. / ACM et al. | 1999
- 16
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EMI-Noise Analysis Under ASIC Design EnvironmentHayashi, S. / Yamada, M. I. / ACM et al. | 1999
- 22
-
An Efficient Sequential Quadratic Programming Formulation of Optimal Wire Spacing for Cross-Talk Noise Avoidance RoutingMorton, P. / Dai, W. / ACM et al. | 1999
- 30
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Post-Routing Timing Optimization with Routing CharacterizationChangfan, C. / Hsu, Y.-C. / Tsai, F.-S. / ACM et al. | 1999
- 36
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Buffer Insertion for Clock Delay and Skew MinimizationZeng, X. / Zhou, D. / Li, W. / ACM et al. | 1999
- 42
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Incremental Capacitance Extraction and its Application to Iterative Timing Driven Detailed RoutingYuan, Y. / Banerjee, P. / ACM et al. | 1999
- 48
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Interconnect Coupling Noise in CMOS VSLI CircuitsTang, K. / Friedman, E. / ACM et al. | 1999
- 48
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Interconnect coupling noise in CMOS VLSI circuitsTang, K.T. / Friedman, E.G. et al. | 1999
- 55
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SRC Top Ten Physical Design ProblemsParkhurst, J. / Sherwani, N. / Maturi, S. / Ahrams, D. / Chiprout, E. / ACM et al. | 1999
- 60
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Towards Synthetic Benchmark Circuits for Evaluating Timing-Driven CAD ToolsStroobandt, D. / Verplaetse, P. l. / Van Campenhout, J. / ACM et al. | 1999
- 67
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Generation of Very Large Circuits to Benchmark the Partitioning of FPGA'sPistorius, J. / Legai, E. / Minoux, M. / ACM et al. | 1999
- 74
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Transistor-Level Micro Placement and Routing for Two-Dimensional Digital VLSI Cell SynthesisRiepe, M. / Sakallah, K. / ACM et al. | 1999
- 83
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Partitioning by Iterative DeletionMadden, P. H. / ACM et al. | 1999
- 90
-
Optimal Partitioners and End-Case Placers for Standard-Cell LayoutCaldwell, A. E. / Kahng, A. B. / Markov, B. I. L. / ACM et al. | 1999
- 97
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Slicing Floorplans with Range ConstraintsYoung, F. Y. / Wong, D. F. / ACM et al. | 1999
- 103
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Arbitrary Convex and Concave Rectilinear Block PackingFujiyosi, K. / Murata, H. / ACM et al. | 1999
- 112
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Subwavelength Optical Lithography: Challenges and Impact on Physical DesignKahng, A. B. / Pati, Y. C. / ACM et al. | 1999
- 121
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Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting MasksBerman, P. / Kahng, A. B. / Vidhani, D. / Wang, E. H. / Zelikovsky, F. A. / ACM et al. | 1999
- 127
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Gate Sizing with Controlled DisplacementChen, W. / Hsieh, C.-T. / Pedram, M. / ACM et al. | 1999
- 133
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Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI Interconnect Under a Higher Order AWE ModelHu, J. / Sapatnekar, S. / ACM et al. | 1999
- 140
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Efficient Solution of Systems of Orientation ConstraintsGanley, J. / ACM et al. | 1999
- 145
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Behavior of Congestion Minimization During PlacementWang, M. / Sarrafzadeh, M. / ACM et al. | 1999
- 151
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Partitioning with Terminals: A "New" Problem and New BenchmarksAlpert, C. / Caldwell, A. / Kahng, A. B. / Markov, I. / ACM et al. | 1999
- 158
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Transistor-Level Placement for Full Custom Datapath Cell DesignVahia, D. / Ciesielski, M. / ACM et al. | 1999
- 164
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Circuit Clustering Using Graph ColoringSingh, A. / Marek-Sadowska, M. / ACM et al. | 1999
- 170
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Why So Many Start-ups Today? A Designer and Venture Capitalist's ViewBechtolsheim, A. / ACM et al. | 1999
- 172
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Interconnect Thermal Modeling for Determining Design Limits on Current DensityChen, D. / Li, E. / Rosenbaum, E. / Kang, S.-M. / ACM et al. | 1999
- 179
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Standard Cell Placement for Even On-Chip Thermal DistributionTsai, C.-H. / Kang, S.-M. / ACM et al. | 1999
- 186
-
Measuring Nets Routability for MCM's General Area Routing ProblemsKusnadi / Carothers, J. D. / ACM et al. | 1999
- 193
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Getting to the Bottom of DSM II: The Global Wiring ParadigmSylvester, D. / Keutzer, K. / ACM et al. | 1999
- 201
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Crosstalk Constrained Global Route EmbeddingParakh, P. / Brown, R. B. / ACM et al. | 1999
- 208
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Timing Driven Maze RoutingHur, S.-W. / Jagannathan, A. / Lillis, J. / ACM et al. | 1999
- 214
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Via Design Rule Consideration in Multi-Layer Maze Routing AlgorithmsCong, J. / Fang, J. / Khoo, K.-Y. / ACM et al. | 1999