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    Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT (English)

    In: 2009 design, automation and test in Europe conference and exhibition ; 1302-1307  ; 2009

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    Table of contents conference proceedings

    The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.

    1
    Has anything changed in electronic design since 1983?
    Muller, Mike et al. | 2009
    2
    Embedded systems design - Scientific challenges and work directions
    Sifakis, J. et al. | 2009
    3
    A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip
    Huaxi Gu, / Jiang Xu, / Wei Zhang, et al. | 2009
    9
    SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
    Seiculescu, C. / Murali, S. / Benini, L. / De Micheli, G. et al. | 2009
    15
    User-centric design space exploration for heterogeneous Network-on-Chip platforms
    Chou, Chen-Ling / Marculescu, Radu et al. | 2009
    21
    A highly resilient routing algorithm for fault-tolerant NoCs
    Fick, David / DeOrio, Andrew / Chen, Gregory / Bertacco, Valeria / Sylvester, Dennis / Blaauw, David et al. | 2009
    27
    Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
    Whitty, S. / Sahlbach, H. / Ernst, R. / Putzke-Roming, W. et al. | 2009
    33
    An ILP formulation for task mapping and scheduling on multi-core architectures
    Ying Yi, / Wei Han, / Xin Zhao, / Erdogan, Ahmet T. / Arslan, Tughrul et al. | 2009
    39
    DPR in high energy physics
    Gao, Wenxue / Kugel, Andreas / Manner, Reinhard / Abel, Norbert / Meier, Nick / Kebschull, Udo et al. | 2009
    45
    A flexible layered architecture for accurate digital baseband algorithm development and verification
    Alimohammad, Amirhossein / Fard, Saeed F. / Cockburn, Bruce F. et al. | 2009
    51
    Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
    Huang, Lin / Yuan, Feng / Xu, Qiang et al. | 2009
    57
    Integrated scheduling and synthesis of control applications on distributed embedded systems
    Samii, Soheil / Cervin, Anton / Eles, Petru / Peng, Zebo et al. | 2009
    63
    Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude
    Chengmo Yang, / Orailoglu, A. et al. | 2009
    69
    Pipelined data parallel task mapping/scheduling technique for MPSoC
    Yang, Hoeseok / Ha, Soonhoi et al. | 2009
    75
    Joint logic restructuring and pin reordering against NBTI-induced performance degradation
    Wu, Kai-Chiang / Marculescu, Diana et al. | 2009
    81
    A self-adaptive system architecture to address transistor aging
    Khan, O. / Kundu, S. et al. | 2009
    87
    Masking timing errors on speed-paths in logic circuits
    Choudhury, M.R. / Mohanram, K. et al. | 2009
    93
    WCRT algebra and interfaces for esterel-style synchronous processing
    Mendler, Michael / von Hanxleden, Reinhard / Traulsen, Claus et al. | 2009
    99
    Reliable mode changes in real-time systems with fixed priority or EDF scheduling
    Stoimenov, Nikolay / Perathoner, Simon / Thiele, Lothar et al. | 2009
    105
    Improved worst-case response-time calculations by upper-bound conditions
    Pollex, V. / Kollmann, S. / Albers, K. / Slomka, F. et al. | 2009
    111
    A generalized scheduling approach for dynamic dataflow applications
    Plishker, W. / Sane, N. / Bhattacharyya, S.S. et al. | 2009
    117
    Optimizing data flow graphs to minimize hardware implementation
    Gomez-Prado, D. / Ren, Q. / Ciesielski, M. / Guillot, J. / Boutillon, E. et al. | 2009
    123
    Multi-clock Soc design using protocol conversion
    Sinha, R. / Roop, P.S. / Basu, S. / Salcic, Z. et al. | 2009
    129
    A formal approach to design space exploration of protocol converters
    Avnit, K. / Sowmya, A. et al. | 2009
    135
    Model-based synthesis and optimization of static multi-rate image processing algorithms
    Keinert, J. / Dutta, H. / Hannig, F. / Haubelt, C. / Teich, J. et al. | 2009
    141
    2.8 PANEL SESSION - Consolidation, a Modern ``Moor of Venice'' Tale
    Casale-Rossi, M. / De Micheli, G. et al. | 2009
    141
    Panel session - Consolidation, a modern “Moor of Venice” tale
    Casale-Rossi, M. / De Micheli, G. et al. | 2009
    142
    Variation resilient adaptive controller for subthreshold circuits
    Mishra, B. / Al-Hashimi, B.M. / Zwolinski, M. et al. | 2009
    148
    Minimization of NBTI performance degradation using internal node control
    Bild, David R. / Bok, Gregory E. / Dick, Robert P. et al. | 2009
    154
    Physically clustered forward body biasing for variability compensation in nanometer CMOS design
    Sathanur, Ashoka / Pullini, Antonio / Benini, Luca / De Micheli, Giovanni / Macii, Enrico et al. | 2009
    160
    An event-guided approach to reducing voltage noise in processors
    Gupta, Meeta S. / Reddi, Vijay Janapa / Holloway, Glenn / Wei, Gu-Yeon / Brooks, David M. et al. | 2009
    166
    Design and implementation of a database filter for BLAST acceleration
    Afratis, P. / Galanakis, C. / Sotiriades, E. / Mplemenos, G.-G. / Chrysos, G. / Papaefstathiou, I. / Pnevmatikatos, D. et al. | 2009
    172
    A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
    Siozios, K. / Pavlidis, V.F. / Soudris, D. et al. | 2009
    178
    Priority-based packet communication on a bus-shaped structure for FPGA-systems
    Sander, O. / Glas, B. / Roth, C. / Becker, J. / Muller-Glaser, K.D. et al. | 2009
    184
    Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor
    Ahmed, S.Z. / Eydoux, J. / Rouge, L. / Cuelle, J.-B. / Sassatelli, G. / Torres, L. et al. | 2009
    190
    Functional qualification of TLM verification
    Bombieri, N. / Fummi, F. / Pravadelli, G. / Hampton, M. / Letombe, F. et al. | 2009
    196
    Solver technology for system-level to RTL equivalence checking
    Koelbl, A. / Jacoby, R. / Jain, H. / Pixley, C. et al. | 2009
    202
    A high-level debug environment for communication-centric debug
    Goossens, K. / Vermeulen, B. / Nejad, A.B. et al. | 2009
    208
    Cache aware compression for processor debug support
    Vishnoi, A. / Panda, P.R. / Balakrishnan, M. et al. | 2009
    214
    Fault insertion testing of a novel CPLD-based fail-safe system
    Griessnig, G. / Mader, R. / Steger, C. / Weiss, R. et al. | 2009
    220
    Test architecture design and optimization for three-dimensional SoCs
    Li Jiang, / Lin Huang, / Qiang Xu, et al. | 2009
    226
    A co-design approach for embedded system modeling and code generation with UML and MARTE
    Vidal, Jorgiano / de Lamotte, Florent / Gogniat, Guy / Soulard, Philippe / Diguet, Jean-Philippe et al. | 2009
    232
    Componentizing hardware/software interface design
    Hao, K. / Fei Xie, et al. | 2009
    238
    A UML frontend for IP-XACT-based IP management
    Schattkowsky, T. / Tao Xie, / Mueller, W. et al. | 2009
    244
    Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA
    Arpinen, Tero / Koskinen, Tapio / Salminen, Erno / Hamalainen, Timo D. / Hannikainen, Marko et al. | 2009
    250
    Aelite: A flit-synchronous Network on Chip with composable and predictable services
    Hansson, Andreas / Subburaman, Mahesh / Goossens, Kees et al. | 2009
    256
    Configurable links for runtime adaptive on-chip communication
    Al Faruque, M.A. / Ebi, T. / Henkel, J. et al. | 2009
    262
    Synthesis of low-overhead configurable source routing tables for network interfaces
    Loi, Igor / Angiolini, Federico / Benini, Luca et al. | 2009
    268
    SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
    Jara-Berrocal, A. / Gordon-Ross, A. et al. | 2009
    274
    Analog layout synthesis - Recent advances in topological approaches
    Graeb, H. / Balasa, F. / Castro-Lopez, R. / Chang, Y.-W. / Fernandez, F.V. / Lin, P.-H. / Strasser, M. et al. | 2009
    280
    An accurate interconnect thermal model using equivalent transmission line circuit
    Baohua Wang, / Mazumder, P. et al. | 2009
    284
    Analogue mixed signal simulation using spice and SystemC
    Kirchner, Tobias / Bannow, Nico / Grimm, Christoph et al. | 2009
    288
    Reliability aware through silicon via planning for 3D stacked ICs
    Shayan, A. / Xiang Hu, / He Peng, / Chung-Kuan Cheng, / Wenjian Yu, / Popovich, M. / Toms, T. / Xiaoming Chen, et al. | 2009
    292
    A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
    Nagaraj, Kelageri / Kundu, Sandip et al. | 2009
    296
    Analysis and optimization of NBTI induced clock skew in gated clock trees
    Chakraborty, Ashutosh / Ganesan, Gokul / Rajaram, Anand / Pan, David Z. et al. | 2009
    300
    Bitstream relocation with local clock domains for partially reconfigurable FPGAs
    Flynn, Adam / Gordon-Ross, Ann / George, Alan D. et al. | 2009
    304
    Parallel transistor level full-chip circuit simulation
    He Peng, / Chung-Kuan Cheng, et al. | 2009
    308
    Performance-driven dual-rail insertion for chip-level pre-fabricated design
    Chen, Fu-Wei / Liu, Yi-Yu et al. | 2009
    312
    Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning
    Trautmann, M. / Mamagkakis, S. / Bougard, B. / Declerck, J. / Umans, E. / Dejonghe, A. / Van der Perre, L. / Catthoor, F. et al. | 2009
    316
    Fast and accurate protocol specific bus modeling using TLM 2.0
    van Moll, H.W.M. / Corporaal, H. / Reyes, V. / Boonen, M. et al. | 2009
    320
    Incorporating graceful degradation into embedded system design
    Glass, M. / Lukasiewycz, M. / Haubelt, C. / Teich, J. et al. | 2009
    324
    Rewiring using IRredundancy Removal and Addition
    Chun-Chi Lin, / Chun-Yao Wang, et al. | 2009
    328
    Gate replacement techniques for simultaneous leakage and aging optimization
    Wang, Yu / Xiaoming Chen, / Wang, Wenping / Cao, Yu / Xie, Yuan / Yang, Huazhong et al. | 2009
    334
    Enabling concurrent clock and power gating in an industrial design flow
    Bolzani, L. / Calimera, A. / Macii, A. / Macii, E. / Poncino, M. et al. | 2009
    340
    TRAM: A tool for Temperature and Reliability Aware Memory Design
    Khajeh, A. / Gupta, A. / Dutt, N. / Kurdahi, F. / Eltawil, A. / Khouri, K. / Abadir, M. et al. | 2009
    346
    Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs
    Casteres, Jean / Ramaherirariny, Tovo et al. | 2009
    352
    A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
    Reorda, M.S. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
    352
    A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable Chips
    Reorda, M.S. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
    358
    Communication minimization for in-network processing in body sensor networks: A buffer assignment technique
    Ghasemzadeh, H. / Jain, N. / Sgroi, M. / Jafari, R. et al. | 2009
    364
    A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard
    Larcher, Luca / Brama, Riccardo / Ganzerli, Marcello / Iannacci, Jacopo / Bedani, Marco / Gnudi, Antonio et al. | 2009
    369
    Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
    Diaz-Madrid, J.A. / Neubauer, H. / Hauer, H. / Domenech-Asensi, G. / Ruiz-Merino, R. et al. | 2009
    374
    PANEL SESSION - Is the second wave of HLS the one industry will surf on?
    Le Toumelin, L. et al. | 2009
    375
    Analyzing the impact of process variations on parametric measurements: Novel models and applications
    Reda, Sherief / Nassif, Sani R. et al. | 2009
    381
    On linewidth-based yield analysis for nanometer lithography
    Sreedhar, A. / Kundu, S. et al. | 2009
    387
    Impact of voltage scaling on nanoscale SRAM reliability
    Chandra, Vikas / Aitken, Robert et al. | 2009
    393
    A file-system-aware FTL design for flash-memory storage systems
    Po-Liang Wu, / Yuan-Hao Chang, / Tei-Wei Kuo, et al. | 2009
    399
    FSAF: File system aware flash translation layer for NAND Flash Memories
    Mylavarapu, S.K. / Choudhuri, S. / Shrivastava, A. / Jongeun Lee, / Givargis, T. et al. | 2009
    405
    A set-based mapping strategy for flash-memory reliability enhancement
    Yuan-Sheng Chu, / Jen-Wei Hsieh, / Yuan-Hao Chang, / Tei-Wei Kuo, et al. | 2009
    411
    Energy efficient multiprocessor task scheduling under input-dependent variation
    Cong, J. / Gururaj, K. et al. | 2009
    417
    Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
    Kim, Jungsoo / Sungjoo Yoo, / Chong-Min Kyung, et al. | 2009
    423
    ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
    Kahng, A.B. / Bin Li, / Li-Shiuan Peh, / Samadi, K. et al. | 2009
    429
    PANEL SESSION - Open source hardware IP, are you serious?
    Parrish, P. et al. | 2009
    430
    5.1 HOT TOPIC - Concurrent SoC Development and End-to-End Planning
    Anghel, L. / Smith, G. et al. | 2009
    430
    HOT TOPIC - Concurrent SoC development and end-to-end planning
    Anghel, L. et al. | 2009
    431
    Nano-electronics challenge chip designers meet real nano-electronics in 2010s?
    Fujita, S. et al. | 2009
    433
    MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
    Matsunaga, S. / Hayakawa, J. / Ikeda, S. / Miura, K. / Endoh, T. / Ohno, H. / Hanyu, T. et al. | 2009
    436
    Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect Ttransistors
    Mitra, S. / Zhang, J. / Patil, N. / Wei, H. et al. | 2009
    436
    Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors
    Mitra, Subhasish / Zhang, Jie / Patil, Nishant / Hai Wei, et al. | 2009
    442
    Reconfigurable circuit design with nanomaterials
    Dong, Chen / Chilstedt, Scott / Chen, Deming et al. | 2009
    448
    An architecture for secure software defined radio
    Chunxiao Li, / Raghunathan, A. / Jha, N.K. et al. | 2009
    454
    Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage
    Xu Guo, / Schaumont, Patrick et al. | 2009
    460
    Hardware aging-based software metering
    Dabiri, Foad / Potkonjak, Miodrag et al. | 2009
    466
    On-chip communication architecture exploration for processor-pool-based MPSoC
    Joo, Young-Pyo / Kim, Sungchan / Soonhoi Ha, et al. | 2009
    472
    Combined system synthesis and communication architecture exploration for MPSoCs
    Lukasiewycz, Martin / Streubuhr, Martin / Glass, Michael / Haubelt, Christian / Teich, Jurgen et al. | 2009
    478
    UMTS MPSoC design evaluation using a system level design framework
    Densmore, D. / Simalatsar, A. / Davare, A. / Passerone, R. / Sangiovanni-Vincentelli, A. et al. | 2009
    484
    Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
    Vayrynen, M. / Singh, V. / Larsson, E. et al. | 2009
    490
    Improving yield and reliability of chip multiprocessors
    Pan, A. / Khan, O. / Kundu, S. et al. | 2009
    496
    A unified online Fault Detection scheme via checking of Stability Violation
    Yan, Guihai / Han, Yinhe / Li, Xiaowei et al. | 2009
    502
    Statistical fault injection: Quantified error and confidence
    Leveugle, R. / Calvez, A. / Maistri, P. / Vanhauwaert, P. et al. | 2009
    507
    KAST: K-associative sector translation for NAND flash memory in real-time systems
    Hyunjin Cho, / Dongkun Shin, / Young Ik Eom, et al. | 2009
    513
    White box performance analysis considering static non-preemptive software scheduling
    Viehl, Alexander / Pressler, Michael / Bringmann, Oliver / Rosenstiel, Wolfgang et al. | 2009
    519
    Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems
    Konig, Frank / Boers, Dave / Slomka, Frank / Margull, Ulrich / Niemetz, Michael / Wirrer, Gerhard et al. | 2009
    524
    Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources
    Negrean, Mircea / Schliecker, Simon / Ernst, Rolf et al. | 2009
    530
    Light NUCA: A proposal for bridging the inter-cache latency gap
    Suarez, Dario / Monreal, Teresa / Vallejo, Fernando / Beivide, Ramon / Vinals, Victor et al. | 2009
    536
    ReSim, a trace-driven, reconfigurable ILP processor simulator
    Fytraki, S. / Pnevmatikatos, D. et al. | 2009
    542
    Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
    Ansaloni, Giovanni / Bonzini, Paolo / Pozzi, Laura et al. | 2009
    548
    Algorithms for the automatic extension of an instruction-set
    Galuzzi, Carlo / Theodoropoulos, Dimitris / Meeuws, Roel / Bertels, Koen et al. | 2009
    554
    Dimensioning heterogeneous MPSoCs via parallelism analysis
    Ristau, B. / Limberg, T. / Arnold, O. / Fettweis, G. et al. | 2009
    558
    MPSoCs run-time monitoring through Networks-on-Chip
    Fiorin, L. / Palermo, G. / Silvano, C. et al. | 2009
    562
    Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints
    Ludovici, D. / Gilabert, F. / Medardoni, S. / Gomez, C. / Gomez, M.E. / Lopez, P. / Gaydadjiev, G.N. / Bertozzi, D. et al. | 2009
    566
    A hybrid packet-circuit switched on-chip network based on SDM
    Modarressi, Mehdi / Sarbazi-Azad, Hamid / Arjomand, Mohammad et al. | 2009
    570
    SecBus: Operating System controlled hierarchical page-based memory bus protection
    Lifeng Su, / Courcambeck, Stephan / Guillemin, Pierre / Schwarz, Christian / Pacalet, Renaud et al. | 2009
    574
    A link arbitration scheme for quality of service in a latency-optimized network-on-chip
    Diemer, Jonas / Ernst, Rolf et al. | 2009
    578
    Flow regulation for on-chip communication
    Zhonghai Lu, / Millberg, Mikael / Jantsch, Axel / Bruce, Alistair / van der Wolf, Pieter / Henriksson, Tomas et al. | 2009
    582
    Customizing IP cores for system-on-chip designs using extensive external don't-cares
    Kai-hui Chang, / Bertacco, V. / Markov, I.L. et al. | 2009
    586
    Extending IP-XACT to support an MDE based approach for SoC design
    El Mrabti, Amin / Petrot, Frederic / Bouchhima, Aimen et al. | 2009
    590
    Overcoming limitations of the SystemC data introspection
    Genz, C. / Drechsler, R. et al. | 2009
    594
    Selective Light V~t~h Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power Reduction
    Xu, H. / Vemuri, R. / Jone, W.-B. et al. | 2009
    594
    Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage
    Reduction, Power / Xu, Hao / Vemuri, Ranga / Jone, Wen-Ben et al. | 2009
    598
    A power-efficient migration mechanism for D-NUCA caches
    Bardine, A. / Comparetti, M. / Foglia, P. / Gabrielli, G. / Prete, C.A. et al. | 2009
    602
    PANEL SESSION - Vertical integration versus disaggregation
    Zorian, Y. et al. | 2009
    603
    Trends and challenges in wireless application processors
    Garnier, Pierre et al. | 2009
    604
    System-level process variability analysis and mitigation for 3D MPSoCs
    Garg, Siddharth / Marculescu, Diana et al. | 2009
    610
    Co-design of signal, power, and thermal distribution networks for 3D ICs
    Young-Joon Lee, / Yoon Jo Kim, / Huang, Gang / Bakir, Muhannad / Yogendra Joshi, / Fedorov, Andrei / Lim, Sung Kyu et al. | 2009
    616
    Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
    Bobba, Shashikanth / Jie Zhang, / Pullini, Antonio / Atienza, David / De Micheli, Giovanni et al. | 2009
    622
    Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
    Ben Jamaa, M.H. / Mohanram, K. / De Micheli, G. et al. | 2009
    628
    Enhancing correlation electromagnetic attack using planar near-field cartography
    Real, D. / Valette, F. / Drissi, M. et al. | 2009
    634
    Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
    Lomne, V. / Maurine, P. / Torres, L. / Robert, M. / Soares, R. / Calazans, N. et al. | 2009
    640
    Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
    Sauvage, L. / Guilley, S. / Danger, J.-L. / Mathieu, Y. / Nassar, M. et al. | 2009
    646
    Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPT
    Henzen, L. / Carbognani, F. / Felber, N. / Fichtner, W. et al. | 2009
    646
    Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
    Henzen, L. / Carbognani, F. / Felber, N. / Fichtner, W. et al. | 2009
    652
    Architectural support for low overhead detection of memory violations
    Ghose, S. / Gilgeous, L. / Dudnik, P. / Aggarwal, A. / Waxman, C. et al. | 2009
    658
    Caspar: Hardware patching for multicore processors
    Wagner, I. / Bertacco, V. et al. | 2009
    664
    A new speculative addition architecture suitable for two's complement operations
    Cilardo, Alessandro et al. | 2009
    670
    Limiting the number of dirty cache lines
    de Langen, Pepijn / Juurlink, Ben et al. | 2009
    676
    Contactless testing: Possibility or pipe-dream?
    Marinissen, E.J. / Dae Young Lee, / Hayes, J.P. / Sellathamby, C. / Moore, B. / Slupsky, S. / Pujol, L. et al. | 2009
    682
    Analysis and optimization of fault-tolerant embedded systems with hardened processors
    Izosimov, Viacheslav / Polian, Ilia / Pop, Paul / Eles, Petru / Peng, Zebo et al. | 2009
    688
    On bounding response times under software transactional memory in distributed multiprocessor real-time systems
    Fahmy, S.F. / Ravindran, B. / Jensen, E.D. et al. | 2009
    694
    An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems
    Chuan-Yue Yang, / Jian-Jia Chen, / Tei-Wei Kuo, / Thiele, L. et al. | 2009
    700
    A graph grammar based approach to automated multi-objective analog circuit design
    Das, Angan / Vemuri, Ranga et al. | 2009
    706
    Massively multi-topology sizing of analog integrated circuits
    Palmers, P. / McConnaghy, T. / Steyaert, M. / Gielen, G. et al. | 2009
    712
    Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
    Ali, Sawal / Li Ke, / Wilcock, Reuben / Wilson, Peter et al. | 2009
    718
    Computation of IP3 using single-tone moments analysis
    Tannir, D. / Khazaka, R. et al. | 2009
    724
    Formal approaches to analog circuit verification
    Barke, Erich / Grabowski, Darius / Graeb, Helmut / Hedrich, Lars / Heinen, Stefan / Popp, Ralf / Steinhorst, Sebastian / Wang, Yifan et al. | 2009
    730
    Panel session - ESL methodology for SoC
    Toda, L. / Rhines, W. et al. | 2009
    730
    7.1 PANEL SESSION - ESL Methodology for SoC
    Toda, L. / Rhines, W. et al. | 2009
    731
    An overview of non-volatile memory technology and the implication for tools and architectures
    Hai Li, / Yiran Chen, et al. | 2009
    737
    Power and performance of read-write aware Hybrid Caches with non-volatile memories
    Xiaoxia Wu, / Jian Li, / Lixin Zhang, / Speight, E. / Yuan Xie, et al. | 2009
    743
    Using non-volatile memory to save energy in servers
    Roberts, David / Kgil, Taeho / Mudge, Trevor et al. | 2009
    749
    aEqualized: A novel routing algorithm for the Spidergon Network On Chip
    Concer, Nicola / Iamundo, Salvatore / Bononi, Luciano et al. | 2009
    755
    Group-caching for NoC based multicore cache coherent systems
    Wang Zuo, / Shi Feng, / Zuo Qi, / Ji Weixing, / Li Jiaxin, / Deng Ning, / Xue Licheng, / Tan Yuan, / Qiao Baojun, et al. | 2009
    761
    A monitor interconnect and support subsystem for multicore processors
    Madduri, S. / Vadlamani, R. / Burleson, W. / Tessier, R. et al. | 2009
    767
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