Extending IP-XACT to Support an MDE Based Approach for SoC Design (English)
- New search for: El Mrabti, A.
- New search for: Petrot, F.
- New search for: Bouchhima, A.
- New search for: El Mrabti, A.
- New search for: Petrot, F.
- New search for: Bouchhima, A.
In:
2009 design, automation and test in Europe conference and exhibition
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586-589
;
2009
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ISBN:
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ISSN:
- Conference paper / Print
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Title:Extending IP-XACT to Support an MDE Based Approach for SoC Design
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Contributors:
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Conference:2009 design, automation and test in Europe conference and exhibition ; 2009 ; Nice, France
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Published in:DATE -PROCEEDINGS - HARDCOPY ; 2 ; 586-589
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Publisher:
- New search for: Curran
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Place of publication:New York
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Publication date:2009-01-01
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Size:4 pages
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Remarks:Includes bibliographical references and index
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ISBN:
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ISSN:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Has anything changed in electronic design since 1983?Muller, Mike et al. | 2009
- 2
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Embedded systems design - Scientific challenges and work directionsSifakis, J. et al. | 2009
- 3
-
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chipHuaxi Gu, / Jiang Xu, / Wei Zhang, et al. | 2009
- 9
-
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chipsSeiculescu, Ciprian / Murali, Srinivasan / Benini, Luca / De Micheli, Giovanni et al. | 2009
- 15
-
User-centric design space exploration for heterogeneous Network-on-Chip platformsChou, Chen-Ling / Marculescu, Radu et al. | 2009
- 21
-
A highly resilient routing algorithm for fault-tolerant NoCsFick, D. / DeOrio, A. / Chen, G. / Bertacco, V. / Sylvester, D. / Blaauw, D. et al. | 2009
- 27
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Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architectureWhitty, Sean / Sahlbach, Henning / Ernst, Rolf / Putzke-Roming, Wolfram et al. | 2009
- 33
-
An ILP formulation for task mapping and scheduling on multi-core architecturesYing Yi, / Wei Han, / Xin Zhao, / Erdogan, A.T. / Arslan, T. et al. | 2009
- 39
-
DPR in high energy physicsGao, Wenxue / Kugel, Andreas / Manner, Reinhard / Abel, Norbert / Meier, Nick / Kebschull, Udo et al. | 2009
- 45
-
A flexible layered architecture for accurate digital baseband algorithm development and verificationAlimohammad, Amirhossein / Fard, Saeed F. / Cockburn, Bruce F. et al. | 2009
- 51
-
Lifetime reliability-aware task allocation and scheduling for MPSoC platformsLin Huang, / Feng Yuan, / Qiang Xu, et al. | 2009
- 57
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Integrated scheduling and synthesis of control applications on distributed embedded systemsSamii, S. / Cervin, A. / Eles, P. / Zebo Peng, et al. | 2009
- 63
-
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitudeChengmo Yang, / Orailoglu, A. et al. | 2009
- 69
-
Pipelined data parallel task mapping/scheduling technique for MPSoCHoeseok Yang, / Soonhoi Ha, et al. | 2009
- 75
-
Joint logic restructuring and pin reordering against NBTI-induced performance degradationKai-Chiang Wu, / Marculescu, D. et al. | 2009
- 81
-
A self-adaptive system architecture to address transistor agingKhan, O. / Kundu, S. et al. | 2009
- 87
-
Masking timing errors on speed-paths in logic circuitsChoudhury, M.R. / Mohanram, K. et al. | 2009
- 93
-
WCRT algebra and interfaces for esterel-style synchronous processingMendler, M. / von Hanxleden, R. / Traulsen, C. et al. | 2009
- 99
-
Reliable mode changes in real-time systems with fixed priority or EDF schedulingStoimenov, N. / Perathoner, S. / Thiele, L. et al. | 2009
- 105
-
Improved worst-case response-time calculations by upper-bound conditionsPollex, Victor / Kollmann, Steffen / Albers, Karsten / Slomka, Frank et al. | 2009
- 111
-
A generalized scheduling approach for dynamic dataflow applicationsPlishker, William / Sane, Nimish / Bhattacharyya, Shuvra S. et al. | 2009
- 117
-
Optimizing data flow graphs to minimize hardware implementationGomez-Prado, D. / Ren, Q. / Ciesielski, M. / Guillot, J. / Boutillon, E. et al. | 2009
- 123
-
Multi-clock Soc design using protocol conversionSinha, R. / Roop, P.S. / Basu, S. / Salcic, Z. et al. | 2009
- 129
-
A formal approach to design space exploration of protocol convertersAvnit, Karin / Sowmya, Arcot et al. | 2009
- 135
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Model-based synthesis and optimization of static multi-rate image processing algorithmsKeinert, Joachim / Dutta, Hritam / Hannig, Frank / Haubelt, Christian / Teich, Jurgen et al. | 2009
- 141
-
Panel session - Consolidation, a modern “Moor of Venice” taleCasale-Rossi, M. / De Micheli, G. et al. | 2009
- 141
-
2.8 PANEL SESSION - Consolidation, a Modern ``Moor of Venice'' TaleCasale-Rossi, M. / De Micheli, G. et al. | 2009
- 142
-
Variation resilient adaptive controller for subthreshold circuitsMishra, Biswajit / Al-Hashimi, Bashir M. / Zwolinski, Mark et al. | 2009
- 148
-
Minimization of NBTI performance degradation using internal node controlBild, D.R. / Bok, G.E. / Dick, R.P. et al. | 2009
- 154
-
Physically clustered forward body biasing for variability compensation in nanometer CMOS designSathanur, Ashoka / Pullini, Antonio / Benini, Luca / De Micheli, Giovanni / Macii, Enrico et al. | 2009
- 160
-
An event-guided approach to reducing voltage noise in processorsGupta, M.S. / Reddi, V.J. / Holloway, G. / Gu-Yeon Wei, / Brooks, D.M. et al. | 2009
- 166
-
Design and implementation of a database filter for BLAST accelerationAfratis, P. / Galanakis, C. / Sotiriades, E. / Mplemenos, G.-G. / Chrysos, G. / Papaefstathiou, I. / Pnevmatikatos, D. et al. | 2009
- 172
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A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAsSiozios, Kostas / Pavlidis, Vasilis F. / Soudris, Dimitrios et al. | 2009
- 178
-
Priority-based packet communication on a bus-shaped structure for FPGA-systemsSander, O. / Glas, B. / Roth, C. / Becker, J. / Muller-Glaser, K.D. et al. | 2009
- 184
-
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processorAhmed, S.Z. / Eydoux, J. / Rouge, L. / Cuelle, J.-B. / Sassatelli, G. / Torres, L. et al. | 2009
- 190
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Functional qualification of TLM verificationBombieri, N. / Fummi, F. / Pravadelli, G. / Hampton, M. / Letombe, F. et al. | 2009
- 196
-
Solver technology for system-level to RTL equivalence checkingKoelbl, Alfred / Jacoby, Reily / Jain, Himanshu / Pixley, Carl et al. | 2009
- 202
-
A high-level debug environment for communication-centric debugGoossens, K. / Vermeulen, B. / Nejad, A.B. et al. | 2009
- 208
-
Cache aware compression for processor debug supportVishnoi, Anant / Panda, Preeti Ranjan / Balakrishnan, M. et al. | 2009
- 214
-
Fault insertion testing of a novel CPLD-based fail-safe systemGriessnig, G. / Mader, R. / Steger, C. / Weiss, R. et al. | 2009
- 220
-
Test architecture design and optimization for three-dimensional SoCsLi Jiang, / Lin Huang, / Qiang Xu, et al. | 2009
- 226
-
A co-design approach for embedded system modeling and code generation with UML and MARTEVidal, J. / de Lamotte, F. / Gogniat, G. / Soulard, P. / Diguet, J.-P. et al. | 2009
- 232
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Componentizing hardware/software interface designKecheng Hao, / Fei Xie, et al. | 2009
- 238
-
A UML frontend for IP-XACT-based IP managementSchattkowsky, Tim / Tao Xie, / Mueller, Wolfgang et al. | 2009
- 244
-
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGAArpinen, T. / Koskinen, T. / Salminen, E. / Hamalainen, T.D. / Hannikainen, M. et al. | 2009
- 250
-
Aelite: A flit-synchronous Network on Chip with composable and predictable servicesHansson, Andreas / Subburaman, Mahesh / Goossens, Kees et al. | 2009
- 256
-
Configurable links for runtime adaptive on-chip communicationAl Faruque, Mohammad Abdullah / Ebi, Thomas / Henkel, Jorg et al. | 2009
- 262
-
Synthesis of low-overhead configurable source routing tables for network interfacesLoi, I. / Angiolini, F. / Benini, L. et al. | 2009
- 268
-
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systemsJara-Berrocal, A. / Gordon-Ross, A. et al. | 2009
- 274
-
Analog layout synthesis - Recent advances in topological approachesGraeb, H. / Balasa, F. / Castro-Lopez, R. / Chang, Y.-W. / Fernandez, F.V. / Lin, P.-H. / Strasser, M. et al. | 2009
- 280
-
An accurate interconnect thermal model using equivalent transmission line circuitBaohua Wang, / Mazumder, P. et al. | 2009
- 284
-
Analogue mixed signal simulation using spice and SystemCKirchner, Tobias / Bannow, Nico / Grimm, Christoph et al. | 2009
- 288
-
Reliability aware through silicon via planning for 3D stacked ICsShayan, A. / Xiang Hu, / He Peng, / Chung-Kuan Cheng, / Wenjian Yu, / Popovich, M. / Toms, T. / Xiaoming Chen, et al. | 2009
- 292
-
A study on placement of post silicon clock tuning buffers for mitigating impact of process variationNagaraj, Kelageri / Kundu, Sandip et al. | 2009
- 296
-
Analysis and optimization of NBTI induced clock skew in gated clock treesChakraborty, Ashutosh / Ganesan, Gokul / Rajaram, Anand / Pan, David Z. et al. | 2009
- 300
-
Bitstream relocation with local clock domains for partially reconfigurable FPGAsFlynn, A. / Gordon-Ross, A. / George, A.D. et al. | 2009
- 304
-
Parallel transistor level full-chip circuit simulationPeng, He / Cheng, Chung-Kuan et al. | 2009
- 308
-
Performance-driven dual-rail insertion for chip-level pre-fabricated designFu-Wei Chen, / Yi-Yu Liu, et al. | 2009
- 312
-
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioningTrautmann, Martin / Mamagkakis, Stylianos / Bougard, Bruno / Declerck, Jeroen / Umans, Erik / Dejonghe, Antoine / Van der Perre, Liesbet / Catthoor, Francky et al. | 2009
- 316
-
Fast and accurate protocol specific bus modeling using TLM 2.0van Moll, H.W.M. / Corporaal, H. / Reyes, V. / Boonen, M. et al. | 2009
- 320
-
Incorporating graceful degradation into embedded system designGlass, Michael / Lukasiewycz, Martin / Haubelt, Christian / Teich, Jurgen et al. | 2009
- 324
-
Rewiring using IRredundancy Removal and AdditionChun-Chi Lin, / Chun-Yao Wang, et al. | 2009
- 328
-
Gate replacement techniques for simultaneous leakage and aging optimizationYu Wang, / Xiaoming Chen, / Wenping Wang, / Yu Cao, / Yuan Xie, / Huazhong Yang, et al. | 2009
- 334
-
Enabling concurrent clock and power gating in an industrial design flowBolzani, L. / Calimera, A. / Macii, A. / Macii, E. / Poncino, M. et al. | 2009
- 340
-
TRAM: A tool for Temperature and Reliability Aware Memory DesignKhajeh, Amin / Gupta, Aseem / Dutt, Nikil / Kurdahi, Fadi / Eltawil, Ahmed / Khouri, Kamal / Abadir, Magdy et al. | 2009
- 346
-
Aircraft integration real-time simulator modeling with AADL for architecture tradeoffsCasteres, J. / Ramaherirariny, T. et al. | 2009
- 352
-
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable ChipsSonza Reorda, M. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
- 352
-
A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable ChipsReorda, M.S. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
- 358
-
Communication minimization for in-network processing in body sensor networks: A buffer assignment techniqueGhasemzadeh, Hassan / Jain, Nisha / Sgroi, Marco / Jafari, Roozbeh et al. | 2009
- 364
-
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standardLarcher, L. / Brama, R. / Ganzerli, M. / Iannacci, J. / Bedani, M. / Gnudi, A. et al. | 2009
- 369
-
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharingDiaz-Madrid, J.A. / Neubauer, H. / Hauer, H. / Domenech-Asensi, G. / Ruiz-Merino, R. et al. | 2009
- 374
-
PANEL SESSION - Is the second wave of HLS the one industry will surf on?Le Toumelin, L. et al. | 2009
- 375
-
Analyzing the impact of process variations on parametric measurements: Novel models and applicationsReda, Sherief / Nassif, Sani R. et al. | 2009
- 381
-
On linewidth-based yield analysis for nanometer lithographySreedhar, Aswin / Kundu, Sandip et al. | 2009
- 387
-
Impact of voltage scaling on nanoscale SRAM reliabilityChandra, Vikas / Aitken, Robert et al. | 2009
- 393
-
A file-system-aware FTL design for flash-memory storage systemsPo-Liang Wu, / Yuan-Hao Chang, / Tei-Wei Kuo, et al. | 2009
- 399
-
FSAF: File system aware flash translation layer for NAND Flash MemoriesMylavarapu, Sai Krishna / Choudhuri, Siddharth / Shrivastava, Aviral / Jongeun Lee, / Givargis, Tony et al. | 2009
- 405
-
A set-based mapping strategy for flash-memory reliability enhancementYuan-Sheng Chu, / Hsieh, Jen-Wei / Chang, Yuan-Hao / Kuo, Tei-Wei et al. | 2009
- 411
-
Energy efficient multiprocessor task scheduling under input-dependent variationCong, Jason / Gururaj, Karthik et al. | 2009
- 417
-
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scalingJungsoo Kim, / Sungjoo Yoo, / Chong-Min Kyung, et al. | 2009
- 423
-
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space explorationKahng, A.B. / Bin Li, / Li-Shiuan Peh, / Samadi, K. et al. | 2009
- 429
-
PANEL SESSION - Open source hardware IP, are you serious?Parrish, P. et al. | 2009
- 430
-
HOT TOPIC - Concurrent SoC development and end-to-end planningAnghel, L. et al. | 2009
- 430
-
5.1 HOT TOPIC - Concurrent SoC Development and End-to-End PlanningAnghel, L. / Smith, G. et al. | 2009
- 431
-
Nano-electronics challenge chip designers meet real nano-electronics in 2010s?Shinobu Fujita, et al. | 2009
- 433
-
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issuesMatsunaga, Shoun / Hayakawa, Jun / Ikeda, Shoji / Miura, Katsuya / Endoh, Tetsuo / Ohno, Hideo / Hanyu, Takahiro et al. | 2009
- 436
-
Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect TtransistorsMitra, S. / Zhang, J. / Patil, N. / Wei, H. et al. | 2009
- 436
-
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect TransistorsMitra, S. / Jie Zhang, / Patil, N. / Hai Wei, et al. | 2009
- 442
-
Reconfigurable circuit design with nanomaterialsChen Dong, / Chilstedt, S. / Deming Chen, et al. | 2009
- 448
-
An architecture for secure software defined radioChunxiao Li, / Raghunathan, Anand / Jha, Niraj K. et al. | 2009
- 454
-
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storageXu Guo, / Schaumont, Patrick et al. | 2009
- 460
-
Hardware aging-based software meteringDabiri, Foad / Potkonjak, Miodrag et al. | 2009
- 466
-
On-chip communication architecture exploration for processor-pool-based MPSoCYoung-Pyo Joo, / Sungchan Kim, / Soonhoi Ha, et al. | 2009
- 472
-
Combined system synthesis and communication architecture exploration for MPSoCsLukasiewycz, Martin / Streubuhr, Martin / Glass, Michael / Haubelt, Christian / Teich, Jurgen et al. | 2009
- 478
-
UMTS MPSoC design evaluation using a system level design frameworkDensmore, D. / Simalatsar, A. / Davare, A. / Passerone, R. / Sangiovanni-Vincentelli, A. et al. | 2009
- 484
-
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chipsVayrynen, M. / Singh, V. / Larsson, E. et al. | 2009
- 490
-
Improving yield and reliability of chip multiprocessorsPan, Abhisek / Khan, Omer / Kundu, Sandip et al. | 2009
- 496
-
A unified online Fault Detection scheme via checking of Stability ViolationGuihai Yan, / Yinhe Han, / Xiaowei Li, et al. | 2009
- 502
-
Statistical fault injection: Quantified error and confidenceLeveugle, R. / Calvez, A. / Maistri, P. / Vanhauwaert, P. et al. | 2009
- 507
-
KAST: K-associative sector translation for NAND flash memory in real-time systemsCho, Hyunjin / Dongkun Shin, / Eom, Young Ik et al. | 2009
- 513
-
White box performance analysis considering static non-preemptive software schedulingViehl, Alexander / Pressler, Michael / Bringmann, Oliver / Rosenstiel, Wolfgang et al. | 2009
- 519
-
Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systemsKonig, F. / Boers, D. / Slomka, F. / Margull, U. / Niemetz, M. / Wirrer, G. et al. | 2009
- 524
-
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resourcesNegrean, M. / Schliecker, S. / Ernst, R. et al. | 2009
- 530
-
Light NUCA: A proposal for bridging the inter-cache latency gapSuarez, Dario / Monreal, Teresa / Vallejo, Fernando / Beivide, Ramon / Vinals, Victor et al. | 2009
- 536
-
ReSim, a trace-driven, reconfigurable ILP processor simulatorFytraki, Sotiria / Pnevmatikatos, Dionisios et al. | 2009
- 542
-
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing accelerationAnsaloni, G. / Bonzini, P. / Pozzi, L. et al. | 2009
- 548
-
Algorithms for the automatic extension of an instruction-setGaluzzi, Carlo / Theodoropoulos, Dimitris / Meeuws, Roel / Bertels, Koen et al. | 2009
- 554
-
Dimensioning heterogeneous MPSoCs via parallelism analysisRistau, B. / Limberg, T. / Arnold, O. / Fettweis, G. et al. | 2009
- 558
-
MPSoCs run-time monitoring through Networks-on-ChipFiorin, Leandro / Palermo, Gianluca / Silvano, Cristina et al. | 2009
- 562
-
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraintsLudovici, D. / Gilabert, F. / Medardoni, S. / Gomez, C. / Gomez, M.E. / Lopez, P. / Gaydadjiev, G.N. / Bertozzi, D. et al. | 2009
- 566
-
A hybrid packet-circuit switched on-chip network based on SDMModarressi, M. / Sarbazi-Azad, H. / Arjomand, M. et al. | 2009
- 570
-
SecBus: Operating System controlled hierarchical page-based memory bus protectionLifeng Su, / Courcambeck, Stephan / Guillemin, Pierre / Schwarz, Christian / Pacalet, Renaud et al. | 2009
- 574
-
A link arbitration scheme for quality of service in a latency-optimized network-on-chipDiemer, Jonas / Ernst, Rolf et al. | 2009
- 578
-
Flow regulation for on-chip communicationZhonghai Lu, / Millberg, M. / Jantsch, A. / Bruce, A. / van der Wolf, P. / Henriksson, T. et al. | 2009
- 582
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Customizing IP cores for system-on-chip designs using extensive external don't-caresChang, Kai-hui / Bertacco, Valeria / Markov, Igor L. et al. | 2009
- 586
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Extending IP-XACT to support an MDE based approach for SoC designEl Mrabti, Amin / Petrot, Frederic / Bouchhima, Aimen et al. | 2009
- 590
-
Overcoming limitations of the SystemC data introspectionGenz, C. / Drechsler, R. et al. | 2009
- 594
-
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakageHao Xu, / Vemuri, R. / Jone, W.-B. et al. | 2009
- 594
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Selective Light V~t~h Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power ReductionXu, H. / Vemuri, R. / Jone, W.-B. et al. | 2009
- 598
-
A power-efficient migration mechanism for D-NUCA cachesBardine, A. / Comparetti, M. / Foglia, P. / Gabrielli, G. / Prete, C. A. et al. | 2009
- 602
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PANEL SESSION - Vertical integration versus disaggregationZorian, Y. et al. | 2009
- 603
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Trends and challenges in wireless application processorsGarnier, P. et al. | 2009
- 604
-
System-level process variability analysis and mitigation for 3D MPSoCsGarg, S. / Marculescu, D. et al. | 2009
- 610
-
Co-design of signal, power, and thermal distribution networks for 3D ICsYoung-Joon Lee, / Yoon Jo Kim, / Gang Huang, / Bakir, M. / Joshi, Y. / Fedorov, A. / Sung Kyu Lim, et al. | 2009
- 616
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Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesisBobba, Shashikanth / Jie Zhang, / Pullini, Antonio / Atienza, David / De Micheli, Giovanni et al. | 2009
- 622
-
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesisBen Jamaa, M.H. / Mohanram, K. / De Micheli, G. et al. | 2009
- 628
-
Enhancing correlation electromagnetic attack using planar near-field cartographyReal, Denis / Valette, Frederic / Drissi, Mhamed et al. | 2009
- 634
-
Evaluation on FPGA of triple rail logic robustness against DPA and DEMALomne, Victor / Maurine, Philippe / Torres, Lionel / Robert, Michel / Soares, Rafael / Calazans, Ney et al. | 2009
- 640
-
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraintsSauvage, Laurent / Guilley, Sylvain / Danger, Jean-Luc / Mathieu, Yves / Nassar, Maxime et al. | 2009
- 646
-
Hardware Evaluation of the Stream Cipher-Based Hash Functions Radiogatun and irRUPTHenzen, L. / Carbognani, F. / Felber, N. / Fichtner, W. et al. | 2009
- 646
-
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPTHenzen, L. / Carbognani, F. / Felber, N. / Fichtner, W. et al. | 2009
- 652
-
Architectural support for low overhead detection of memory violationsGhose, Saugata / Gilgeous, Latoya / Dudnik, Polina / Aggarwal, Aneesh / Waxman, Corey et al. | 2009
- 658
-
Caspar: Hardware patching for multicore processorsWagner, I. / Bertacco, V. et al. | 2009
- 664
-
A new speculative addition architecture suitable for two's complement operationsCilardo, Alessandro et al. | 2009
- 670
-
Limiting the number of dirty cache linesde Langen, P. / Juurlink, B. et al. | 2009
- 676
-
Contactless testing: Possibility or pipe-dream?Marinissen, E.J. / Dae Young Lee, / Hayes, J.P. / Sellathamby, C. / Moore, B. / Slupsky, S. / Pujol, L. et al. | 2009
- 682
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Analysis and optimization of fault-tolerant embedded systems with hardened processorsIzosimov, Viacheslav / Polian, Ilia / Pop, Paul / Eles, Petru / Peng, Zebo et al. | 2009
- 688
-
On bounding response times under software transactional memory in distributed multiprocessor real-time systemsFahmy, S.F. / Ravindran, B. / Jensen, E.D. et al. | 2009
- 694
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An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systemsChuan-Yue Yang, / Jian-Jia Chen, / Tei-Wei Kuo, / Thiele, L. et al. | 2009
- 700
-
A graph grammar based approach to automated multi-objective analog circuit designDas, A. / Vemuri, R. et al. | 2009
- 706
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Massively multi-topology sizing of analog integrated circuitsPalmers, P. / McConnaghy, T. / Steyaert, M. / Gielen, G. et al. | 2009
- 712
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Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuitsAli, Sawal / Li Ke, / Wilcock, Reuben / Wilson, Peter et al. | 2009
- 718
-
Computation of IP3 using single-tone moments analysisTannir, D. / Khazaka, R. et al. | 2009
- 724
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Formal approaches to analog circuit verificationBarke, E. / Grabowski, D. / Graeb, H. / Hedrich, L. / Heinen, S. / Popp, R. / Steinhorst, S. / Yifan Wang, et al. | 2009
- 730
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Panel session - ESL methodology for SoCToda, L. / Rhines, W. et al. | 2009
- 730
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7.1 PANEL SESSION - ESL Methodology for SoCToda, L. / Rhines, W. et al. | 2009
- 731
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An overview of non-volatile memory technology and the implication for tools and architecturesHai Li, / Yiran Chen, et al. | 2009
- 737
-
Power and performance of read-write aware Hybrid Caches with non-volatile memoriesXiaoxia Wu, / Jian Li, / Lixin Zhang, / Speight, E. / Yuan Xie, et al. | 2009
- 743
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Using non-volatile memory to save energy in serversRoberts, David / Kgil, Taeho / Mudge, Trevor et al. | 2009
- 749
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aEqualized: A novel routing algorithm for the Spidergon Network On ChipConcer, Nicola / Iamundo, Salvatore / Bononi, Luciano et al. | 2009
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Group-caching for NoC based multicore cache coherent systemsWang Zuo, / Shi Feng, / Zuo Qi, / Ji Weixing, / Li Jiaxin, / Deng Ning, / Xue Licheng, / Tan Yuan, / Qiao Baojun, et al. | 2009
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A monitor interconnect and support subsystem for multicore processorsMadduri, Sailaja / Vadlamani, Ramakrishna / Burleson, Wayne / Tessier, Russell et al. | 2009
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A real-time application design methodology for MPSoCsBeltrame, Giovanni / Fossati, Luca / Sciuto, Donatella et al. | 2009
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Adaptive prefetching for shared cache based chip multiprocessorsKandemir, M. / Yuanrui Zhang, / Ozturk, O. et al. | 2009
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CUFFS: An instruction count based architectural framework for security of MPSoCsPatel, Krutartha / Parameswaran, Sri / Ragel, Roshan G. et al. | 2009
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Design as you see FIT: System-level soft error analysis of sequential circuitsHolcomb, D. / Wenchao Li, / Seshia, S.A. et al. | 2009
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Detecting errors using multi-cycle invariance informationAlves, N. / Nepal, K. / Dworak, J. / Bahar, R. I. et al. | 2009
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A novel approach to entirely integrate Virtual Test into test development flowLu, Ping / Glaser, Daniel / Uygur, Gurkan / Helmreich, Klaus et al. | 2009
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Robust non-preemptive hard real-time scheduling for clustered multicore platformsLombardi, Michele / Milano, Michela / Benini, Luca et al. | 2009
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Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchyMarongiu, A. / Benini, L. et al. | 2009
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Using randomization to cope with circuit uncertaintySafizadeh, H. / Tahghighi, M. / Ardestani, E.K. / Tavasoli, G. / Bazargan, K. et al. | 2009
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Process variation aware thread mapping for Chip MultiprocessorsHong, S. / Narayanan, S.H.K. / Kandemir, M. / Ozturk, O. et al. | 2009
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Gate sizing for large cell-based designsHeld, Stephan et al. | 2009
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Multi-domain clock skew scheduling-aware register placement to optimize clock distribution networkMohammadZadeh, Naser / Mirsaeedi, Minoo / Jahanian, Ali / Zamani, Morteza Saheb et al. | 2009
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Decoupling capacitor planning with analytical delay model on RLC power gridYe Tao, / Sung Kyu Lim, et al. | 2009
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Package routability- and IR-drop-aware finger/pad assignment in chip-package co-designChao-Hung Lu, / Hung-Ming Chen, / Liu, C.-N.J. / Wen-Yu Shih, et al. | 2009
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Learning early-stage platform dimensioning from late-stage timing verificationRichter, K. / Jersak, M. / Ernst, R. et al. | 2009
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The influence of real-time constraints on the design of FlexRay-based systemsReichelt, Stephan / Scheickl, Oliver / Tabanoglu, Gokhan et al. | 2009
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Time and memory tradeoffs in the implementation of AUTOSAR componentsFerrari, A. / Di Natale, M. / Gentile, G. / Reggiani, G. / Gai, P. et al. | 2009
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Systolic like soft-detection architecture for 4×4 64-QAM MIMO systemBhagawat, Pankaj / Dash, Rajballav / Choi, Gwan et al. | 2009
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Systolic Like Soft-Detection Architecture for 4x4 64-QAM MIMO SystemBhagawat, P. / Dash, R. / Choi, G. et al. | 2009
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Co-simulation based platform for wireless protocols design explorationsFourmigue, A. / Girodias, B. / Nicolescu, G. / Aboulhamid, E.-M. et al. | 2009
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How to speed-up your NLFSR-based stream cipherDubrova, E. et al. | 2009
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A high performance reconfigurable Motion Estimation hardware architectureTasdizen, O. / Kukner, H. / Akin, A. / Hamzaoglu, I. et al. | 2009
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Partition-based exploration for reconfigurable JPEG designsPotter, Philip G. / Luk, Wayne / Cheung, Peter et al. | 2009
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Automated synthesis of streaming C applications to process networks in hardwarevan Haastregt, Sven / Kienhuis, Bart et al. | 2009