Self-Test of Sequential Circuits with Deterministic Test Pattern Sequences (Unknown)
- New search for: Kunzmann, A.
- New search for: Boehland, F.
- New search for: Kunzmann, A.
- New search for: Boehland, F.
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- New search for: Ambler, T.
In:
Economics of Electronic Design, Manufacture and Test
2/3
;
307
;
1994
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ISSN:
- Article (Journal) / Print
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Title:Self-Test of Sequential Circuits with Deterministic Test Pattern Sequences
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Contributors:
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Published in:JOURNAL OF ELECTRONIC TESTING ; 5, 2/3 ; 307
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Publisher:
- New search for: KLUWER ACADEMIC PUBLISHERS BOSTON
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Publication date:1994-01-01
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Size:307 pages
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ISSN:
-
Type of media:Article (Journal)
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Type of material:Print
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Language:Unknown
- New search for: 621.3
- Further information on Dewey Decimal Classification
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Classification:
DDC: 621.3 -
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 5, Issue 2/3
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 127
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EditorialAgrawal, Vishwani D. et al. | 1994
- 129
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IntroductionAbadir, Magdy / Ambler, Tony et al. | 1994
- 131
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A tale of two designs: the cheapest and the most economicAgrawal, Vishwani D. et al. | 1994
- 137
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Test strategy planning using economic analysisDear, I. D. / Dislis, C. D. / Ambler, A. P. / Dick, J. et al. | 1994
- 157
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Economic modeling of board test strategiesDavis, Brendan et al. | 1994
- 171
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Economics of “design for test” to remain competitive in the 90sZarrinfar, Farzad et al. | 1994
- 179
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The economics of scan-path design for testabilityVarma, Prab / Gheewala, Tushar et al. | 1994
- 195
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High Level Test Economics Advisor (Hi-TEA)Abadir, Magdy / Parikh, Ashish / Bal, Linda / Sandborn, Peter / Murphy, Cynthia et al. | 1994
- 207
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Multichip systems trade-off analysis toolSandborn, Peter A. / Ghosh, Rajarshi / Drake, Ken / Abadir, Magdy / Bal, Linda / Parikh, Ashish et al. | 1994
- 219
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Trade-off Analysis on Cost and Manufacturing Technology of an Electronic ProductRao, S. / Haskell, B. / Yee, I. et al. | 1994
- 219
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Trade-off analysis on cost and manufacturing technology of an electronic product: Case studyRao, Shekar / Haskell, Bert / Yee, Ian et al. | 1994
- 229
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Cost based surface mount PCB design evaluationAlexander, M. / Sríhari, K. / Emerson, C. R. et al. | 1994
- 239
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Sensitivity analysis in economics based test strategy planningDick, J. H. / Trischler, E. / Dislis, C. / Ambler, A. P. et al. | 1994
- 253
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Improving quality: Yield versus test coverageMillman, Steven D. et al. | 1994
- 263
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Boundary scan in board manufacturingZiaja, Thomas A. / Swartzlander, Earl E. et al. | 1994
- 269
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Comparing quality assurance methods and the resulting design strategies: Experiences from complex designsv. Reventlow, C. et al. | 1994
- 273
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Trade-offs in scan path and BIST implementations for RAMsNicolaidis, M. / Kebichi, O. / Alves, V. Castro et al. | 1994
- 285
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Techniques for estimating test length under random testMajumdar, Amitava / Vrudhula, Sarma B. K. et al. | 1994
- 299
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Fuzzy optimization models for analog test decisionsFares, Mounir / Kaminska, Bozena et al. | 1994
- 307
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Self-test of sequential circuits with deterministic test pattern sequencesKunzmann, Arno / Boehland, Frank et al. | 1994