Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors (English)
- New search for: Lin, H.
- New search for: Fei, Y.
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- New search for: Shi, Z.J.
- New search for: Lin, H.
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- New search for: Guan, X.
- New search for: Shi, Z.J.
In:
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS
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18
, 11
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1519-1532
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2010
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ISSN:
- Article (Journal) / Print
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Title:Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors
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Contributors:
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Published in:IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS ; 18, 11 ; 1519-1532
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Publisher:
- New search for: INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS
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Publication date:2010-01-01
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Size:14 pages
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
- New search for: 321.395
- Further information on Dewey Decimal Classification
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Classification:
DDC: 321.395 -
Source:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Table of contents – Volume 18, Issue 11
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1505
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Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set ExtensionsO'Melia, Sean / Elbirt, Adam J et al. | 2010
- 1505
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Computer Security Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set ExtensionsO'Melia, S et al. | 2010
- 1519
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Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set ProcessorsHai Lin, / Yunsi Fei, / Xuan Guan, / Shi, Z J et al. | 2010
- 1533
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Selection of a Fault Model for Fault Diagnosis Based on Unique ResponsesPomeranz, Irith / Reddy, Sudhakar M et al. | 2010
- 1533
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Testing Selection of a Fault Model for Fault Diagnosis Based on Unique ResponsesPomeranz, I et al. | 2010
- 1544
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Wireless Communications A MIMO Decoder Accelerator for Next Generation Wireless CommunicationsMohammed, K et al. | 2010
- 1544
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A MIMO Decoder Accelerator for Next Generation Wireless CommunicationsMohammed, K / Daneshrad, B et al. | 2010
- 1556
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Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial MethodRuijing Shen, / Tan, Sheldon X.-D / Jian Cui, / Wenjian Yu, / Yici Cai, / Geng-Sheng Chen, et al. | 2010
- 1556
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Process Variations Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial MethodShen, R et al. | 2010
- 1567
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A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or GatesDadgour, Hamed F / Banerjee, Kaustav et al. | 2010
- 1578
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On Incremental Component Implementation Selection in System SynthesisGhiasi, Soheil et al. | 2010
- 1578
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System Synthesis On Incremental Component Implementation Selection in System SynthesisGhiasi, S et al. | 2010
- 1590
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Memory Design Yield-Driven Near-Threshold SRAM DesignChen, G et al. | 2010
- 1590
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Yield-Driven Near-Threshold SRAM DesignChen, G / Sylvester, D / Blaauw, D / Mudge, T et al. | 2010
- 1599
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Don't-Care Gating (DCG) TCAM Design Used in Network Routing TableYen-Jen Chang, et al. | 2010
- 1608
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Logic Synthesis Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature DependenceCalimera, A et al. | 2010
- 1608
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Temperature-Insensitive Dual-V~t~h Synthesis for Nanometer CMOS Technologies Under Inverse Temperature DependenceCalimera, A. / Bahar, R.I. / Macii, E. / Poncino, M. et al. | 2010
- 1608
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Temperature-Insensitive Dual- $V_{\rm th}$ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature DependenceCalimera, Andrea / Bahar, R Iris / Macii, Enrico / Poncino, Massimo et al. | 2010
- 1621
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Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI ToleranceYiran Chen, / Hai Li, / Cheng-Kok Koh, / Guangyu Sun, / Jing Li, / Yuan Xie, / Roy, Kaushik et al. | 2010
- 1621
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TRANSACTIONS BRIEFS Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI ToleranceChen, Y et al. | 2010
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Table of contents| 2010
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2010
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2010
- C4
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors| 2010