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    Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing (English)

    In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS ; 20 , 3 ; 551-563  ; 2012
    • ISSN:
      1063-8210
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    Table of contents – Volume 20, Issue 3

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    The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.

    393
    A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application
    Jungwon Han, / Kwisung Yoo, / Dongmyung Lee, / Kangyeop Park, / Wonseok Oh, / Sung Min Park, et al. | 2012
    393
    Analog Design - A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application
    Han, J et al. | 2012
    400
    A 3-5 GHz Current-Reuse -Boosted CG LNA for Ultrawideband in 130 nm CMOS
    Khurram, M. / Hasan, S.M.R. et al. | 2012
    400
    A 3–5 GHz Current-Reuse $g_{m}$-Boosted CG LNA for Ultrawideband in 130 nm CMOS
    Khurram, M. / Hasan, S. M. R. et al. | 2012
    410
    Testing - Test Pattern Generation of Relaxed n-Detect Test Sets
    Neophytou, S N et al. | 2012
    410
    Test Pattern Generation of Relaxed -Detect Test Sets
    Neophytou, S.N. / Michael, M.K. et al. | 2012
    410
    Test Pattern Generation of Relaxed $n$-Detect Test Sets
    Neophytou, S. N. / Michael, M. K. et al. | 2012
    424
    Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays
    Sanyal, A. / Ganeshpure, K. / Kundu, S. et al. | 2012
    437
    Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
    Nunez-Yanez, J. L. / Nabina, A. / Hung, E. / Vafiadis, G. et al. | 2012
    437
    VLSI Design - Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
    Nunez-Yanez, J L et al. | 2012
    449
    Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials
    Hasan, M. A. / Namin, A. H. / Negre, C. et al. | 2012
    459
    NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
    Ke-Ren Dai, / Wen-Hao Liu, / Yih-Lang Li, et al. | 2012
    459
    Physical Design - NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
    Dai, K-R et al. | 2012
    473
    SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems
    Jai-Ming Lin, / Zhi-Xiong Hung, et al. | 2012
    485
    ECOS: Stable Matching Based Metal-Only ECO Synthesis
    Jiang, Iris Hui-Ru / Hua-Yu Chang, et al. | 2012
    498
    A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization
    Jiying Xue, / Yangdong Deng, / Zuochang Ye, / Hongrui Wang, / Liu Yang, / Zhiping Yu, et al. | 2012
    512
    Low Power Design - Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs
    Chakraborty, K et al. | 2012
    512
    Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs
    Chakraborty, K. / Roy, S. et al. | 2012
    523
    Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks
    Chattopadhyay, A. / Zilic, Z. et al. | 2012
    523
    Clocking - Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks
    Chattopadhyay, A et al. | 2012
    537
    Raising FPGA Logic Density Through Synthesis-Inspired Architecture
    Anderson, J. H. / Qiang Wang, / Ravishankar, C. et al. | 2012
    537
    Architecture - Raising FPGA Logic Density Through Synthesis-Inspired Architecture
    Anderson, J H et al. | 2012
    551
    Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
    Xuan Guan, / Yunsi Fei, / Hai Lin, et al. | 2012
    564
    A 15 MHz to 600 MHz, 20 mW, 0.38 mm $^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$ m CMOS
    Hoyos, S. / Tsang, C. W. / Vanderhaegen, J. / Yun Chiu, / Aibara, Y. / Khorramabadi, H. / Nikolic, B. et al. | 2012
    564
    A 15 MHz to 600 MHz, 20 mW, 0.38 mm Split-Control, Fast Coarse Locking Digital DLL in 0.13 m CMOS
    Hoyos, S. / Tsang, C.W. / Vanderhaegen, J. / Chiu, Y. / Aibara, Y. / Khorramabadi, H. / Nikolic, B. et al. | 2012
    564
    TRANSACTIONS BRIEFS - A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 μm CMOS
    Hoyos, S et al. | 2012
    568
    High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes
    Garcia-Herrero, F. / Canet, M. J. / Valls, J. / Meher, P. K. et al. | 2012
    573
    Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence
    Dehbaoui, A. / Lomne, V. / Ordas, T. / Torres, L. / Robert, M. / Maurine, P. et al. | 2012
    578
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors
    | 2012
    579
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    | 2012
    580
    Quality without compromise [advertisement]
    | 2012
    C1
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    | 2012
    C2
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information
    | 2012
    C3
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information
    | 2012

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