A Hardware Processing Unit for Point Sets (English)

In: Graphics Hardware   ;  21-31  ;  2008

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We present a hardware architecture and processing unit for point sampled data. Our design is focused on fundamental and computationally expensive operations on point sets including k-nearest neighbors search, moving least squares approximation, and others. Our architecture includes a configurable processing module allowing users to implement custom operators and to run them directly on the chip. A key component of our design is the spatial search unit based on a kd-tree performing both kNN and eN searches. It utilizes stack recursions and features a novel advanced caching mechanism allowing direct reuse of previously computed neighborhoods for spatially coherent queries. In our FPGA prototype, both modules are multi-threaded, exploit full hardware parallelism, and utilize a fixed-function data path and control logic for maximum throughput and minimum chip surface. A detailed analysis demonstrates the performance and versatility of our design.

  • Title:
    A Hardware Processing Unit for Point Sets
  • Author / Creator:
  • Published in:
  • Publisher:
    The Eurographics Association
  • Place of publication:
    Postfach 8043, 38621 Goslar, Germany
  • Year of publication:
    2008
  • Size:
    11 pages
  • ISBN:
  • ISSN:
  • DOI:
  • Type of media:
    Conference paper
  • Type of material:
    Electronic Resource
  • Language:
    English
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Table of contents conference proceedings

The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.

1
Tracy: A Debugger and System Analyzer for Cross-Platform Graphics Development
Kyöstilä, Sami / Kangas, Kari J. / Pulli, Kari | 2008
13
Total Recall: A Debugging Framework for GPUs
Sharif, Ahmad / Lee, Hsien-Hsin S. | 2008
21
A Hardware Processing Unit for Point Sets
Heinzle, Simon / Guennebaud, Gaël / Botsch, Mario / Gross, Markus | 2008
33
Coherent Layer Peeling for Transparent High-Depth-Complexity Scenes
Carr, Nathan / Mech, Radomir / Miller, Gavin | 2008
41
Non-Uniform Fractional Tessellation
Munkberg, Jacob / Hasselgren, Jon / Akenine-Möller, Tomas | 2008
47
All-Pairs Shortest-Paths for Large Graphs on the GPU
Katz, Gary J. / Jr., Joseph T. Kider | 2008
57
On Dynamic Load Balancing on Graphics Processors
Cederman, Daniel / Tsigas, Philippas | 2008
65
GPU Accelerated Pathfinding
Bleiweiss, Avi | 2008
75
Floating-Point Buffer Compression in a Unified Codec Architecture
Ström, Jacob / Wennersten, Per / Rasmusson, Jim / Hasselgren, Jon / Munkberg, Jacob / Clarberg, Petrik / Akenine-Möller, Tomas | 2008
85
DHTC: An Effective DXTC-based HDR Texture Compression Scheme
Sun, Wen / Lu, Yan / Wu, Feng / Li, Shipeng | 2008
95
An Improved Shading Cache for Modern GPUs
Sitthi-amorn, Pitchaya / Lawrence, Jason / Yang, Lei / Sander, Pedro V. / Nehab, Diego | 2008
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