PANEL SESSION - Open source hardware IP, are you serious? (English)
- New search for: Parrish, P.
- New search for: Parrish, P.
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2009 Design, Automation & Test in Europe Conference & Exhibition
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429
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2009
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ISSN:
- Conference paper / Electronic Resource
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Title:PANEL SESSION - Open source hardware IP, are you serious?
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Contributors:Parrish, P. ( author )
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- New search for: IEEE
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Publication date:2009-04-01
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Size:75349 byte
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ISBN:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Has anything changed in electronic design since 1983?Muller, Mike et al. | 2009
- 743
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Using non-volatile memory to save energy in serversRoberts, D. / Kgil, T. / Mudge, T. et al. | 2009
- 1
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Selective state retention design using symbolic simulationDarbari, A. / Al Hashimi, B.M. / Flynn, D. / Biggs, J. et al. | 2009
- 3
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A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chipHuaxi Gu, / Jiang Xu, / Wei Zhang, et al. | 2009
- 1
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New simulation methodology of 3D surface roughness loss for interconnects modelingChen, Quan / Wong, Ngai et al. | 2009
- 706
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Massively multi-topology sizing of analog integrated circuitsPalmers, P. / McConnaghy, T. / Steyaert, M. / Gielen, G. et al. | 2009
- 1
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Predictive models for multimedia applications power consumption based on use-case and OS level analysisBellasi, P. / Fornaciari, W. / Siorpaes, D. et al. | 2009
- 1
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System-level hardware-based protection of memories against soft-errorsGherman, V. / Evain, S. / Cartron, M. / Seymour, N. / Bonhomme, Y. et al. | 2009
- 1
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On hierarchical statistical static timing analysisLi, Bing / Chen, Ning / Schmidt, M. / Schneider, W. / Schlichtmann, U. et al. | 2009
- 460
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Hardware aging-based software meteringDabiri, Foad / Potkonjak, Miodrag et al. | 2009
- 411
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Energy efficient multiprocessor task scheduling under input-dependent variationCong, Jason / Gururaj, Karthik et al. | 2009
- 262
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Synthesis of low-overhead configurable source routing tables for network interfacesLoi, I. / Angiolini, F. / Benini, L. et al. | 2009
- 1
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EMC-aware design on a microcontroller for automotive applicationsDoriol, P.J. / Villavicencio, Y. / Forzan, C. / Rotigni, M. / Graziosi, G. / Pandini, D. et al. | 2009
- 436
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Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect TransistorsMitra, Subhasish / Zhang, Jie / Patil, Nishant / Hai Wei, et al. | 2009
- 51
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Lifetime reliability-aware task allocation and scheduling for MPSoC platformsLin Huang, / Feng Yuan, / Qiang Xu, et al. | 2009
- 1
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The influence of real-time constraints on the design of FlexRay-based systemsReichelt, S. / Scheickl, O. / Tabanoglu, G. et al. | 2009
- 519
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Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systemsKonig, F. / Boers, D. / Slomka, F. / Margull, U. / Niemetz, M. / Wirrer, G. et al. | 2009
- 1
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On the relationship between stuck-at fault coverage and transition fault coverageSchat, J. et al. | 2009
- 1
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Automatically mapping applications to a self-reconfiguring platformBruneel, K. / Abouelella, F. / Stroobandt, D. et al. | 2009
- 1
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CAN+: a new backward-compatible controller area network (CAN) protocol with up to 16 x higher data ratesZiermann, T. / Wildermann, S. / Teich, J. et al. | 2009
- 610
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Co-design of signal, power, and thermal distribution networks for 3D ICsYoung-Joon Lee, / Yoon Jo Kim, / Gang Huang, / Bakir, M. / Joshi, Y. / Fedorov, A. / Sung Kyu Lim, et al. | 2009
- 1
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Visual quality analysis for dynamic backlight scaling in LCD systemsBartolini, A. / Ruggiero, M. / Benini, L. et al. | 2009
- 785
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Design as you see FIT: System-level soft error analysis of sequential circuitsHolcomb, D. / Wenchao Li, / Seshia, S.A. et al. | 2009
- 375
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Analyzing the impact of process variations on parametric measurements: Novel models and applicationsReda, S. / Nassif, S.R. et al. | 2009
- 1
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A novel LDPC decoder for DVB-S2 IPMuller, S. / Schreger, M. / Kabutz, M. / Alles, M. / Kienle, F. / Wehn, N. et al. | 2009
- 1
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A new design-for-test technique for SRAM core-cell stability faultsNey, A. / Dilillo, L. / Girard, P. / Pravossoudovitch, S. / Virazel, A. / Bastian, M. / Gouin, V. et al. | 2009
- 1
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Remote measurement of local oscillator drifts in FlexRay networksArmengaud, E. / Steininger, A. et al. | 2009
- 1
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Health-care electronics: the market, the challenges, the progressEberle, W. / Mecheri, A.S. / Thi Kim Thoa Nguyen / Gielen, G. / Campagnolo, R. / Burdett, A. / Toumazou, C. / Volckaerts, B. et al. | 2009
- 1
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Learning early-stage platform dimensioning from late-stage timing verificationRichter, K. / Jersak, M. / Ernst, R. et al. | 2009
- 454
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Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storageXu Guo, / Schaumont, Patrick et al. | 2009
- 387
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Impact of voltage scaling on nanoscale SRAM reliabilityChandra, V. / Aitken, R. et al. | 2009
- 172
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A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAsSiozios, K. / Pavlidis, V.F. / Soudris, D. et al. | 2009
- 1
-
Efficient reliability simulation of analog ICs including variability and time-varying stressMaricau, E. / Gielen, G. et al. | 2009
- 616
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Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesisBobba, Shashikanth / Jie Zhang, / Pullini, Antonio / Atienza, David / De Micheli, Giovanni et al. | 2009
- 1
-
Automatic generation of streaming datapaths for arbitrary fixed permutationsMilder, P.A. / Hoe, J.C. / Puschel, M. et al. | 2009
- 694
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An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systemsYang, Chuan-Yue / Chen, Jian-Jia / Kuo, Tei-Wei / Thiele, Lothar et al. | 2009
- 712
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Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuitsAli, S. / Li Ke, / Wilcock, R. / Wilson, P. et al. | 2009
- 381
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On linewidth-based yield analysis for nanometer lithographySreedhar, Aswin / Kundu, Sandip et al. | 2009
- 821
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Process variation aware thread mapping for Chip MultiprocessorsHong, S. / Narayanan, S.H.K. / Kandemir, M. / Ozturk, O. et al. | 2009
- 2
-
Embedded systems design - Scientific challenges and work directionsSifakis, Joseph et al. | 2009
- 9
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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chipsSeiculescu, Ciprian / Murali, Srinivasan / Benini, Luca / De Micheli, Giovanni et al. | 2009
- 15
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User-centric design space exploration for heterogeneous Network-on-Chip platformsChen-Ling Chou, / Marculescu, R. et al. | 2009
- 21
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A highly resilient routing algorithm for fault-tolerant NoCsFick, D. / DeOrio, A. / Chen, G. / Bertacco, V. / Sylvester, D. / Blaauw, D. et al. | 2009
- 27
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Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architectureWhitty, Sean / Sahlbach, Henning / Ernst, Rolf / Putzke-Roming, Wolfram et al. | 2009
- 33
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An ILP formulation for task mapping and scheduling on multi-core architecturesYing Yi, / Wei Han, / Xin Zhao, / Erdogan, A.T. / Arslan, T. et al. | 2009
- 39
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DPR in high energy physicsGao, W. / Kugel, A. / Manner, R. / Abel, N. / Meier, N. / Kebschull, U. et al. | 2009
- 45
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A flexible layered architecture for accurate digital baseband algorithm development and verificationAlimohammad, A. / Fard, S.F. / Cockburn, B.F. et al. | 2009
- 57
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Integrated scheduling and synthesis of control applications on distributed embedded systemsSamii, S. / Cervin, A. / Eles, P. / Zebo Peng, et al. | 2009
- 63
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Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitudeChengmo Yang, / Orailoglu, A. et al. | 2009
- 69
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Pipelined data parallel task mapping/scheduling technique for MPSoCHoeseok Yang, / Soonhoi Ha, et al. | 2009
- 75
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Joint logic restructuring and pin reordering against NBTI-induced performance degradationKai-Chiang Wu, / Marculescu, D. et al. | 2009
- 81
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A self-adaptive system architecture to address transistor agingKhan, Omer / Kundu, Sandip et al. | 2009
- 87
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Masking timing errors on speed-paths in logic circuitsChoudhury, M.R. / Mohanram, K. et al. | 2009
- 93
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WCRT algebra and interfaces for esterel-style synchronous processingMendler, M. / von Hanxleden, R. / Traulsen, C. et al. | 2009
- 99
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Reliable mode changes in real-time systems with fixed priority or EDF schedulingStoimenov, N. / Perathoner, S. / Thiele, L. et al. | 2009
- 105
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Improved worst-case response-time calculations by upper-bound conditionsPollex, Victor / Kollmann, Steffen / Albers, Karsten / Slomka, Frank et al. | 2009
- 111
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A generalized scheduling approach for dynamic dataflow applicationsPlishker, William / Sane, Nimish / Bhattacharyya, Shuvra S. et al. | 2009
- 117
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Optimizing data flow graphs to minimize hardware implementationGomez-Prado, D. / Ren, Q. / Ciesielski, M. / Guillot, J. / Boutillon, E. et al. | 2009
- 123
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Multi-clock Soc design using protocol conversionSinha, R. / Roop, P.S. / Basu, S. / Salcic, Z. et al. | 2009
- 129
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A formal approach to design space exploration of protocol convertersAvnit, K. / Sowmya, A. et al. | 2009
- 135
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Model-based synthesis and optimization of static multi-rate image processing algorithmsKeinert, Joachim / Dutta, Hritam / Hannig, Frank / Haubelt, Christian / Teich, Jurgen et al. | 2009
- 141
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Panel session - Consolidation, a modern “Moor of Venice” taleCasale-Rossi, M. / De Micheli, G. et al. | 2009
- 141
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2.8 PANEL SESSION - Consolidation, a Modern ``Moor of Venice'' TaleCasale-Rossi, M. / De Micheli, G. et al. | 2009
- 142
-
Variation resilient adaptive controller for subthreshold circuitsMishra, Biswajit / Al-Hashimi, Bashir M. / Zwolinski, Mark et al. | 2009
- 148
-
Minimization of NBTI performance degradation using internal node controlBild, D.R. / Bok, G.E. / Dick, R.P. et al. | 2009
- 154
-
Physically clustered forward body biasing for variability compensation in nanometer CMOS designSathanur, Ashoka / Pullini, Antonio / Benini, Luca / De Micheli, Giovanni / Macii, Enrico et al. | 2009
- 160
-
An event-guided approach to reducing voltage noise in processorsGupta, M.S. / Reddi, V.J. / Holloway, G. / Gu-Yeon Wei, / Brooks, D.M. et al. | 2009
- 166
-
Design and implementation of a database filter for BLAST accelerationAfratis, P. / Galanakis, C. / Sotiriades, E. / Mplemenos, G.-G. / Chrysos, G. / Papaefstathiou, I. / Pnevmatikatos, D. et al. | 2009
- 178
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Priority-based packet communication on a bus-shaped structure for FPGA-systemsSander, O. / Glas, B. / Roth, C. / Becker, J. / Muller-Glaser, K.D. et al. | 2009
- 184
-
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processorAhmed, Syed Zahid / Eydoux, Julien / Rouge, Laurent / Cuelle, Jean-Baptiste / Sassatelli, Gilles / Torres, Lionel et al. | 2009
- 190
-
Functional qualification of TLM verificationBombieri, N. / Fummi, F. / Pravadelli, G. / Hampton, M. / Letombe, F. et al. | 2009
- 196
-
Solver technology for system-level to RTL equivalence checkingKoelbl, Alfred / Jacoby, Reily / Jain, Himanshu / Pixley, Carl et al. | 2009
- 202
-
A high-level debug environment for communication-centric debugGoossens, Kees / Vermeulen, Bart / Nejad, Ashkan Beyranvand et al. | 2009
- 208
-
Cache aware compression for processor debug supportVishnoi, Anant / Panda, Preeti Ranjan / Balakrishnan, M. et al. | 2009
- 214
-
Fault insertion testing of a novel CPLD-based fail-safe systemGriessnig, Gerhard / Mader, Roland / Steger, Christian / Weiss, Reinhold et al. | 2009
- 220
-
Test architecture design and optimization for three-dimensional SoCsLi Jiang, / Lin Huang, / Qiang Xu, et al. | 2009
- 226
-
A co-design approach for embedded system modeling and code generation with UML and MARTEVidal, J. / de Lamotte, F. / Gogniat, G. / Soulard, P. / Diguet, J.-P. et al. | 2009
- 232
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Componentizing hardware/software interface designKecheng Hao, / Fei Xie, et al. | 2009
- 238
-
A UML frontend for IP-XACT-based IP managementSchattkowsky, Tim / Tao Xie, / Mueller, Wolfgang et al. | 2009
- 244
-
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGAArpinen, Tero / Koskinen, Tapio / Salminen, Erno / Hamalainen, Timo D. / Hannikainen, Marko et al. | 2009
- 250
-
Aelite: A flit-synchronous Network on Chip with composable and predictable servicesHansson, Andreas / Subburaman, Mahesh / Goossens, Kees et al. | 2009
- 256
-
Configurable links for runtime adaptive on-chip communicationAl Faruque, Mohammad Abdullah / Ebi, Thomas / Henkel, Jorg et al. | 2009
- 268
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SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systemsJara-Berrocal, A. / Gordon-Ross, A. et al. | 2009
- 274
-
Analog layout synthesis - Recent advances in topological approachesGraeb, H. / Balasa, F. / Castro-Lopez, R. / Chang, Y.-W. / Fernandez, F.V. / Lin, P.-H. / Strasser, M. et al. | 2009
- 280
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An accurate interconnect thermal model using equivalent transmission line circuitBaohua Wang, / Mazumder, P. et al. | 2009
- 284
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Analogue mixed signal simulation using spice and SystemCKirchner, T. / Bannow, N. / Grimm, C. et al. | 2009
- 288
-
Reliability aware through silicon via planning for 3D stacked ICsShayan, Amirali / Hu, Xiang / Peng, He / Cheng, Chung-Kuan / Wenjian Yu, / Popovich, Mikhail / Toms, Thomas / Chen, Xiaoming et al. | 2009
- 292
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A study on placement of post silicon clock tuning buffers for mitigating impact of process variationNagaraj, K. / Kundu, S. et al. | 2009
- 296
-
Analysis and optimization of NBTI induced clock skew in gated clock treesChakraborty, A. / Ganesan, G. / Rajaram, A. / Pan, D.Z. et al. | 2009
- 300
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Bitstream relocation with local clock domains for partially reconfigurable FPGAsFlynn, A. / Gordon-Ross, A. / George, A.D. et al. | 2009
- 304
-
Parallel transistor level full-chip circuit simulationPeng, He / Cheng, Chung-Kuan et al. | 2009
- 308
-
Performance-driven dual-rail insertion for chip-level pre-fabricated designFu-Wei Chen, / Yi-Yu Liu, et al. | 2009
- 312
-
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioningTrautmann, Martin / Mamagkakis, Stylianos / Bougard, Bruno / Declerck, Jeroen / Umans, Erik / Dejonghe, Antoine / Van der Perre, Liesbet / Catthoor, Francky et al. | 2009
- 316
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Fast and accurate protocol specific bus modeling using TLM 2.0van Moll, H.W.M. / Corporaal, H. / Reyes, V. / Boonen, M. et al. | 2009
- 320
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Incorporating graceful degradation into embedded system designGlass, Michael / Lukasiewycz, Martin / Haubelt, Christian / Teich, Jurgen et al. | 2009
- 324
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Rewiring using IRredundancy Removal and AdditionChun-Chi Lin, / Chun-Yao Wang, et al. | 2009
- 328
-
Gate replacement techniques for simultaneous leakage and aging optimizationWang, Yu / Xiaoming Chen, / Wang, Wenping / Cao, Yu / Xie, Yuan / Yang, Huazhong et al. | 2009
- 334
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Enabling concurrent clock and power gating in an industrial design flowBolzani, Leticia / Calimera, Andrea / Macii, Alberto / Macii, Enrico / Poncino, Massimo et al. | 2009
- 340
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TRAM: A tool for Temperature and Reliability Aware Memory DesignKhajeh, A. / Gupta, A. / Dutt, N. / Kurdahi, F. / Eltawil, A. / Khouri, K. / Abadir, M. et al. | 2009
- 346
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Aircraft integration real-time simulator modeling with AADL for architecture tradeoffsCasteres, J. / Ramaherirariny, T. et al. | 2009
- 352
-
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable ChipsSonza Reorda, M. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
- 352
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A Low-Cost SEE Mitigation Solution for Soft-Processors Embedded in Systems on Programmable ChipsReorda, M.S. / Violante, M. / Meinhardt, C. / Reis, R. et al. | 2009
- 358
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Communication minimization for in-network processing in body sensor networks: A buffer assignment techniqueGhasemzadeh, Hassan / Jain, Nisha / Sgroi, Marco / Jafari, Roozbeh et al. | 2009
- 364
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A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standardLarcher, Luca / Brama, Riccardo / Ganzerli, Marcello / Iannacci, Jacopo / Bedani, Marco / Gnudi, Antonio et al. | 2009
- 369
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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharingDiaz-Madrid, J.A. / Neubauer, H. / Hauer, H. / Domenech-Asensi, G. / Ruiz-Merino, R. et al. | 2009
- 374
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PANEL SESSION - Is the second wave of HLS the one industry will surf on?Le Toumelin, L. et al. | 2009
- 393
-
A file-system-aware FTL design for flash-memory storage systemsPo-Liang Wu, / Yuan-Hao Chang, / Kuo, Tei-Wei et al. | 2009
- 399
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FSAF: File system aware flash translation layer for NAND Flash MemoriesMylavarapu, Sai Krishna / Choudhuri, Siddharth / Shrivastava, Aviral / Jongeun Lee, / Givargis, Tony et al. | 2009
- 405
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A set-based mapping strategy for flash-memory reliability enhancementYuan-Sheng Chu, / Jen-Wei Hsieh, / Yuan-Hao Chang, / Tei-Wei Kuo, et al. | 2009
- 417
-
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scalingKim, Jungsoo / Sungjoo Yoo, / Chong-Min Kyung, et al. | 2009
- 423
-
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space explorationKahng, A.B. / Bin Li, / Li-Shiuan Peh, / Samadi, K. et al. | 2009
- 429
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PANEL SESSION - Open source hardware IP, are you serious?Parrish, P. et al. | 2009
- 430
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HOT TOPIC - Concurrent SoC development and end-to-end planningAnghel, L. et al. | 2009
- 430
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5.1 HOT TOPIC - Concurrent SoC Development and End-to-End PlanningAnghel, L. / Smith, G. et al. | 2009
- 431
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Nano-electronics challenge chip designers meet real nano-electronics in 2010s?Fujita, S. et al. | 2009
- 433
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MTJ-based nonvolatile logic-in-memory circuit, future prospects and issuesMatsunaga, Shoun / Hayakawa, Jun / Ikeda, Shoji / Miura, Katsuya / Endoh, Tetsuo / Ohno, Hideo / Hanyu, Takahiro et al. | 2009
- 436
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Imperfection-Immune VLSI Logic Circuits Using Carbon Nanotube Field Effect TtransistorsMitra, S. / Zhang, J. / Patil, N. / Wei, H. et al. | 2009
- 442
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Reconfigurable circuit design with nanomaterialsChen Dong, / Chilstedt, S. / Deming Chen, et al. | 2009
- 448
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An architecture for secure software defined radioChunxiao Li, / Raghunathan, A. / Jha, N.K. et al. | 2009
- 466
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On-chip communication architecture exploration for processor-pool-based MPSoCYoung-Pyo Joo, / Sungchan Kim, / Soonhoi Ha, et al. | 2009
- 472
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Combined system synthesis and communication architecture exploration for MPSoCsLukasiewycz, M. / Streubuhr, M. / Glass, M. / Haubelt, C. / Teich, J. et al. | 2009
- 478
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UMTS MPSoC design evaluation using a system level design frameworkDensmore, D. / Simalatsar, A. / Davare, A. / Passerone, R. / Sangiovanni-Vincentelli, A. et al. | 2009
- 484
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Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chipsVayrynen, M. / Singh, V. / Larsson, E. et al. | 2009
- 490
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Improving yield and reliability of chip multiprocessorsPan, A. / Khan, O. / Kundu, S. et al. | 2009
- 496
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A unified online Fault Detection scheme via checking of Stability ViolationYan, Guihai / Han, Yinhe / Li, Xiaowei et al. | 2009
- 502
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Statistical fault injection: Quantified error and confidenceLeveugle, R. / Calvez, A. / Maistri, P. / Vanhauwaert, P. et al. | 2009
- 507
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KAST: K-associative sector translation for NAND flash memory in real-time systemsCho, Hyunjin / Dongkun Shin, / Eom, Young Ik et al. | 2009
- 513
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White box performance analysis considering static non-preemptive software schedulingViehl, Alexander / Pressler, Michael / Bringmann, Oliver / Rosenstiel, Wolfgang et al. | 2009
- 524
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Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resourcesNegrean, M. / Schliecker, S. / Ernst, R. et al. | 2009
- 530
-
Light NUCA: A proposal for bridging the inter-cache latency gapSuarez, Dario / Monreal, Teresa / Vallejo, Fernando / Beivide, Ramon / Vinals, Victor et al. | 2009
- 536
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ReSim, a trace-driven, reconfigurable ILP processor simulatorFytraki, Sotiria / Pnevmatikatos, Dionisios et al. | 2009
- 542
-
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing accelerationAnsaloni, G. / Bonzini, P. / Pozzi, L. et al. | 2009
- 548
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Algorithms for the automatic extension of an instruction-setGaluzzi, Carlo / Theodoropoulos, Dimitris / Meeuws, Roel / Bertels, Koen et al. | 2009
- 554
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Dimensioning heterogeneous MPSoCs via parallelism analysisRistau, Bastian / Limberg, Torsten / Arnold, Oliver / Fettweis, Gerhard et al. | 2009
- 558
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MPSoCs run-time monitoring through Networks-on-ChipFiorin, L. / Palermo, G. / Silvano, C. et al. | 2009
- 562
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Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraintsLudovici, D. / Gilabert, F. / Medardoni, S. / Gomez, C. / Gomez, M.E. / Lopez, P. / Gaydadjiev, G.N. / Bertozzi, D. et al. | 2009
- 566
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A hybrid packet-circuit switched on-chip network based on SDMModarressi, Mehdi / Sarbazi-Azad, Hamid / Arjomand, Mohammad et al. | 2009
- 570
-
SecBus: Operating System controlled hierarchical page-based memory bus protectionLifeng Su, / Courcambeck, Stephan / Guillemin, Pierre / Schwarz, Christian / Pacalet, Renaud et al. | 2009
- 574
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A link arbitration scheme for quality of service in a latency-optimized network-on-chipDiemer, Jonas / Ernst, Rolf et al. | 2009
- 578
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Flow regulation for on-chip communicationZhonghai Lu, / Millberg, M. / Jantsch, A. / Bruce, A. / van der Wolf, P. / Henriksson, T. et al. | 2009
- 582
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Customizing IP cores for system-on-chip designs using extensive external don't-caresChang, Kai-hui / Bertacco, Valeria / Markov, Igor L. et al. | 2009
- 586
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Extending IP-XACT to support an MDE based approach for SoC designEl Mrabti, Amin / Petrot, Frederic / Bouchhima, Aimen et al. | 2009
- 590
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Overcoming limitations of the SystemC data introspectionGenz, Christian / Drechsler, Rolf et al. | 2009
- 594
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Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakageHao Xu, / Vemuri, R. / Jone, W.-B. et al. | 2009
- 594
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Selective Light V~t~h Hopping (SLITH): Bridging the Gap between Run-Time Dynamic and Leakage Power ReductionXu, H. / Vemuri, R. / Jone, W.-B. et al. | 2009
- 598
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A power-efficient migration mechanism for D-NUCA cachesBardine, A. / Comparetti, M. / Foglia, P. / Gabrielli, G. / Prete, C. A. et al. | 2009
- 602
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PANEL SESSION - Vertical integration versus disaggregationZorian, Y. et al. | 2009
- 603
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Trends and challenges in wireless application processorsGarnier, P. et al. | 2009
- 604
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System-level process variability analysis and mitigation for 3D MPSoCsGarg, Siddharth / Marculescu, Diana et al. | 2009
- 622
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Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesisBen Jamaa, M. Haykel / Mohanram, Kartik / De Micheli, Giovanni et al. | 2009
- 628
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Enhancing correlation electromagnetic attack using planar near-field cartographyReal, D. / Valette, F. / Drissi, M. et al. | 2009
- 634
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Evaluation on FPGA of triple rail logic robustness against DPA and DEMALomne, V. / Maurine, P. / Torres, L. / Robert, M. / Soares, R. / Calazans, N. et al. | 2009
- 640
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