Laser processing - the future of HDI manufacturing (English)
- New search for: Venkat, S.
- New search for: Hannon, T.
- New search for: Venkat, S.
- New search for: Hannon, T.
In:
27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium
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149-153
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2002
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ISBN:
- Conference paper / Electronic Resource
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Title:Laser processing - the future of HDI manufacturing
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Contributors:Venkat, S. ( author ) / Hannon, T. ( author )
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Published in:
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Publisher:
- New search for: IEEE
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Publication date:2002-01-01
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Size:414026 byte
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1
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Solder bumping via paste reflow for area array packagesBenlib Huang, / Ning-Cheng Lee, et al. | 2002
- 18
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Semiconductor backend flip chip processing, inspection requirements and challengesAsgari, R. et al. | 2002
- 23
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Material and process considerations for reliable overniolded flip chip PBGAsHing Chan, / Alvarez, S. / Carson, G. et al. | 2002
- 23
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Material and Process Considerations for Reliable Overmolded Flip Chip PBGAsChan, H. / Alvarez, S. / IEEE et al. | 2002
- 27
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Lead-free low-cost flip-chip process chain: layout, process, reliabilityWoflick, P. / Feldmann, K. et al. | 2002
- 35
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PATCHWORK smart power thick-film hybrids for automotive under hood applicationsWilczek, P.K. et al. | 2002
- 41
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Tape based CSP package supports fine pitch wirebondingGeissinger, J. / Keller, F. / Trevino, S. / Kamei, T. et al. | 2002
- 46
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Chip-in-polymer: volumetric packaging solution using PCB technologyJung, E. / Wojakowski, D. / Neumann, A. / Landesberger, C. / Ostmann, A. / Aschenbrenner, R. / Reichl, H. et al. | 2002
- 50
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Silicon thinning and stacked packagesNew, D. et al. | 2002
- 53
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Wafer level underfill - processing and reliabilityNguyen, L. / Nguyen, H. / Negasi, A. / Tong, Q. / Hong, S.H. et al. | 2002
- 63
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Chip scale packaging techniques for RF SAW devicesGoetz, M. / Jones, C. et al. | 2002
- 67
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Innovations in defluxing engineered chemistries for removing flux residue on back end solder reflowed bumped wafersBixenman, M. et al. | 2002
- 73
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Reliability issues in direct chip attach assemblies using reflow or no-flow underfillPatwardhan, V. / Blass, D. / Borgesen, P. / Srihari, K. et al. | 2002
- 78
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Flux-underfill compatibility and failure mode analysis in high yield flip chip processingHouston, P.N. / Baldwin, D.F. / Tsai, W.M. et al. | 2002
- 85
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High reliability non-flow underfill material with filler loadingKatsurayama, S. / Sakamoto, Y. et al. | 2002
- 88
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Possibilities and limitations of no-flow fluxing underfillHurley, J.M. / Xiaoyun Ye, / Berfield, T. et al. | 2002
- 94
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Effect of underfill staging time on fillet depressionCheong, Y.W. / Then, E. / Cheong Huat Ng, / Giam Seng Lee, / Diaz, M. / De Guia, G. / Mon Leong Loke, et al. | 2002
- 97
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Automatic wedge bonding with ribbon wire for high frequency applicationsIvy Wei Qin, / Reid, P. / Werner, R.E. / Doerr, D. et al. | 2002
- 105
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cLGA® Sockets: Qualification, Production, and Performance ReadyNeidich, D. / IEEE et al. | 2002
- 105
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cLGA/spl reg/ sockets: qualification, production, and performance readyNeidich, D. et al. | 2002
- 110
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Gold stud bump in flip-chip applicationsJordan, J. et al. | 2002
- 115
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Cost and manufacturing optimization of high performance communication hardware using a daughter moduleCamerlo, S. / Priore, S. / Brillhart, M. / Wheling Cheng, / Lekhanh Dang, / Chen, J. et al. | 2002
- 123
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Optimization of nanocomposite integral capacitor fabrication using neural networks and genetic algorithmsThongvigitmanee, T. / May, G.S. et al. | 2002
- 130
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A virtual prototyping test bed for electronics assemblyCecil, J. / Kanchanapiboon, A. / Kanda, P. / Muthaiyan, A. et al. | 2002
- 136
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Decision support for test and debug areas in RF manufacturingBalasubramanian, S. / Arbulich, J. / Craik, J. / Srihari, K. et al. | 2002
- 140
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Requirement specifications for an enterprise level collaborative, data collection, quality management and manufacturing tool for an EMS providerBahl, S. / Venkatesh, R.S. / Craik, J. / Bedi, R. / Uriarte, H. / Srihari, K. et al. | 2002
- 149
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Laser processing - the future of HDI manufacturingVenkat, S. / Hannon, T. et al. | 2002
- 154
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Improving yield, productivity, and quality in test assembly and packaging through direct part marking and unit level traceabilityAgapakis, J. / Figarella, L. et al. | 2002
- 159
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A study of solder paste release from small stencil apertures of different geometries with constant volumesAravamudhan, S. / Santos, D. / Pham-Van-Diep, G. / Andres, F. et al. | 2002
- 166
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Processing strategies for high speed 0201 implementationHouston, P.N. / Bentley, J. / Lewis, B.J. / Smith, B.A. / Baldwin, D.F. et al. | 2002
- 173
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Ultra-low profile CSPs - new packaging solutions for 300 mm based high-speed, mobile and wireless memory applicationsRitzmann, H. et al. | 2002
- 177
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Overcoming the Key Barriers in 35 mum Pitch Wire Bond Packaging: Probe, Mold, and Substrate Solutions and Trade-OffsChylak, B. / Tang, S. / Smith, L. / Keller, F. / IEEE et al. | 2002
- 177
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Overcoming the key barriers in 35 /spl mu/m pitch wire bond packaging: probe, mold, and substrate solutions and trade-offsChylak, B. / Tang, S. / Smith, L. / Keller, F. et al. | 2002
- 183
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Encapsulation of 1-Up fpBGA from design to productionSze, H.M.W. / Tsang, R. / Jaramillo, Y. et al. | 2002
- 190
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Removable tape using thermoplastic adhesive for QFN assembly processKawai, T. / Nagoya, T. / Matsuura, H. et al. | 2002
- 193
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Reliability testing of single diffused planar InP/InGaAs avalanche photodiodesJihoun Jung, / Yong Hwan Kwon, / Kyung Sook Hyun, / Ilgu Yun, et al. | 2002
- 195
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Elimination of polyimide stress buffer on integrated circuits using advanced packaging materialsPatten, D. / Phou, J. et al. | 2002
- 200
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Ball shear versus ball pull test methods for evaluating interfacial failures in area array packagesCoyle, R.J. / Serafino, A.J. / Solan, P.P. et al. | 2002
- 206
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Adhesion and Reliability of Underfill/Substrate Interfaces in Flip Chip BGA Packages: Metrology and CharacterizationNagarajan, K. / Dauskardt, R. H. / IEEE et al. | 2002
- 206
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Adhesion and reliability of underfill/subtrate interfaces in flip chip BGA packages: metrology and characterizationNagarajan, K. / Dauskardt, R.H. et al. | 2002
- 215
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A structured approach to lead-free IC assembly transitioningNguyen, L. / Walberg, R. / Lin, Z. / Koh, T. / Bong, Y.Y. / Chua, M.C. / Chuah, S. / Yeoh, J.J. et al. | 2002
- 223
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Characterization of Lead-Free Solder Pastes for Low Cost Flip-Chip BumpingJackson, G. J. / Durairaj, R. / Ekere, N. N. / IEEE et al. | 2002
- 223
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Characterisation of lead-free solder pastes for low cost flip-chip bumpingJackson, G.J. / Durairaj, R. / Ekere, N.N. et al. | 2002
- 229
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Effect of flux quantity on Sn-Pb and Pb-free BGA solder shear strengthPainaik, M. / Santos, D.L. / McLenaghan, A.J. / Chouta, P. / Johnson, S.K. et al. | 2002
- 238
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Pressfit technology for 3-D molded interconnect devices (MID) - A lead-free alternative to solder joints - challenges and solutions conceptsEisenbarth, M. / Feldmann, K. et al. | 2002
- 245
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Design and characterization of a high-performance wire-bond ball-grid-array packageChing-Chao Huang, / Secker, D. / Ling Yang, / June Feng, / Nirmal Jain, et al. | 2002
- 250
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Electrical Modeling and Analysis of Lead-Bonded and Wire-Bonded muBGA® Packages for High-Speed Memory ApplicationsSeol, B.-S. / Pflughaupt, L. E. / IEEE et al. | 2002
- 250
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Electrical modeling and analysis of lead-bonded and wire-bonded /spl mu/BGA/sup /spl reg// packages for high-speed memory applicationsByong-Su Seol, / Pflughaupt, L.E. et al. | 2002
- 259
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Investigation of 3-D embedded inductors using Monte Carlo analysisSeogoo Lee, / Jongseong Choi, / May, G.S. / Ilgu Yun, et al. | 2002
- 264
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Equivalent driver model for fast system simulationJune Feng, / Ching-Chao Huang, et al. | 2002
- 267
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Finite element analysis of novel substrate design for high performance and cost reduction stacked die CSPYueh, W.R. / Lee, J.C.C. / Wu, A.B.L. / Chen, J.C.M. et al. | 2002
- 274
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Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array packageZahn, B.A. et al. | 2002
- 285
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Co-simulation of dynamic compact models of packages with the detailed models of printed circuit boardsRencz, M. / Szekely, V. / Poppe, A. / Courtois, B. et al. | 2002
- 291
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Effect of underfill fillet configuration on flip chip package reliabilityNguyen, L. / Nguyen, H. et al. | 2002
- 304
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Experimental and Computational Modeling Characterization of Fine Particle Pb-Free Solder Paste Volumes for Flip Chip Assembly ApplicationsJackson, G. J. / Ekere, N. N. / Hendricksen, M. W. / Lu, H. / IEEE et al. | 2002
- 304
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Experimental and computational modelling characterisation of fine particle Pb-free solder paste volumes for flip chip assembly applicationsJackson, G.J. / Hendriksen, M.W. / Lu, H. / Ekere, N.N. et al. | 2002
- 310
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Processing and reliability of flip chip with lead-free solders on halogen-free microvia substratesBaldwin, D.F. / Baynham, G. / Boustedt, K. / Wennerholm, C. et al. | 2002
- 316
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Flux technology for lead-free alloys and its impact on cleaningNing-Cheng Lee, / Bixenman, M. et al. | 2002
- 323
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Reliability of CSP/lead free solder joints with different surface finishes and reflow profilesMe, D. / Geiger, D. / Arra, M. / Dongkai Shangguan, / Hoang Phan, et al. | 2002
- 329
-
Optimizing wire bonding processes for maximum factory portabilityGillotti, G. / Cathcart, R. et al. | 2002
- 335
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A novel process for protecting wire bonds from sweep during moldingHmiel, A.F. / Wicen, R. / Tang, S. et al. | 2002
- 342
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Achieving a world record in ultra high speed wire bonding through novel technologyBarp, M. / Vischer, D. et al. | 2002
- 348
-
The use of pre-molded leadframe cavity package technologies in photonic and RF applicationsLongford, A. / Radloff, B. et al. | 2002
- 353
-
Measurement challenges for on-wafer RF-SOC testWai Yuen Lau, et al. | 2002
- 360
-
Managing test complexity through a comprehensive design-to-test strategyKondrat, M.J. et al. | 2002
- 364
-
Optimizing test strategies during PCB design for boards with limited ICT accessVerma, A. et al. | 2002
- 372
-
Bringing test to design: testing in the designer's event based environmentRajsuman, R. et al. | 2002
- 376
-
Addressing emerging test challenges for multilevel signaling devicesSchroeder, G. et al. | 2002
- 382
-
Characteristics of silver-plated film on the second wire bondabilityLin, T.Y. / Davison, K.L. / Leong, W.S. / Chua, S. / Robin, O. / Yao, Y.F. / Pan, J.S. / Chai, J.W. / Toh, K.C. / Tjiu, W.C. et al. | 2002
- 389
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Environmentally friendly, high thermal resistant, low CTE substrate material for semiconductor packagingBaba, T. et al. | 2002
- 391
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Solving wire bond process challenges for QFN packagingMcDivitt, E. et al. | 2002
- 398
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A new architecture for equipment and clusters for backend processesLichtveld, M. / van der Zon, B. et al. | 2002
- 403
-
A two-step process for achieving an open test-development environmentLam, H. et al. | 2002
- 407
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Achieving higher margins by solving the mobile flash test challengeTrexler, T. et al. | 2002
- 410
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Applications of intelligent control in improving dynamics of precision motion systems used in microelectronics manufacturingTian He, et al. | 2002
- 415
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High Density Photolithographic Advanprobe™ TechnologyYu, D. / Zhou, Y. / Aldaz, B. / Lee, K. / IEEE et al. | 2002
- 415
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High density photolithographic Advanprobe/spl trade/ technologyYu, D. / Zhou, Yu. / Aldaz, B. / Lee, K. et al. | 2002
- 418
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Inspection challenges of leadless packagesBertz, R. / Leahy, P. et al. | 2002
- 423
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Novel techniques for wideband RF testLukez, J. et al. | 2002
- 426
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Techno-economic analysis of competing IC packaging protocolsHannibal, T.A. / Al Capote, M. et al. | 2002
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Twenty Seventh Annual IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium (Cat. No.02CH37299)| 2002