Memristive Threshold Logic Circuit Design of Fast Moving Object Detection (English)
- New search for: Maan, Akshay Kumar
- New search for: Kumar, Dinesh Sasi
- New search for: Sugathan, Sherin
- New search for: James, Alex Pappachen
- New search for: Maan, Akshay Kumar
- New search for: Kumar, Dinesh Sasi
- New search for: Sugathan, Sherin
- New search for: James, Alex Pappachen
In:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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23
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2337-2341
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2015
- Article (Journal) / Electronic Resource
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Title:Memristive Threshold Logic Circuit Design of Fast Moving Object Detection
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Contributors:Maan, Akshay Kumar ( author ) / Kumar, Dinesh Sasi ( author ) / Sugathan, Sherin ( author ) / James, Alex Pappachen ( author )
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Published in:IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; 23, 10 ; 2337-2341
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Publisher:
- New search for: IEEE
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Publication date:2015-10-01
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Size:2042334 byte
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ISSN:
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DOI:
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Type of media:Article (Journal)
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Type of material:Electronic Resource
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Language:English
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Source:
Table of contents – Volume 23, Issue 10
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1973
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A Scalable MIMO Detector Processor With Near-ASIC Energy EfficiencyFasthuber, Robert / Raghavan, Praveen / Van der Perre, Liesbet / Catthoor, Francky et al. | 2015
- 1987
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FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET ImplementationLin, Ting-Jung / Zhang, Wei / Jha, Niraj K. et al. | 2015
- 2001
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Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder CircuitBhattacharyya, Partha / Kundu, Bijoy / Ghosh, Sovan / Kumar, Vinay / Dandapat, Anup et al. | 2015
- 2009
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Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive GranularityVezyrtzis, Christos / Tsividis, Yannis / Nowick, Steven M. et al. | 2015
- 2023
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A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOSChung, Sang-Hye / Kim, Lee-Sup et al. | 2015
- 2034
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A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMsTeman, Adam / Visotsky, Roman et al. | 2015
- 2043
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Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime ReliabilityYu, Jianming / Zhou, Wei / Yang, Yueming / Zhang, Xiaodong / Yu, Zhiyi et al. | 2015
- 2054
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Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCsMohammad, Baker S. / Saleh, Hani / Ismail, Mohammed et al. | 2015
- 2065
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Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout MechanismsChen, Chang-Chih / Milor, Linda et al. | 2015
- 2077
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Experimental Analysis of Thermal Coupling in 3-D Integrated CircuitsSavidis, Ioannis / Vaisband, Boris / Friedman, Eby G. et al. | 2015
- 2090
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Systolic Array Architectures for Sunar–Koç Optimal Normal Basis Type II MultiplierIbrahim, Atef / Gebali, Fayez / Al-Somani, Turki F. et al. | 2015
- 2103
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Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles ArchitectureBobba, Shashikanth / De Micheli, Giovanni et al. | 2015
- 2116
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PFMAP: Exploitation of Particle Filters for Network-on-Chip MappingBayar, Salih / Yurdakul, Arda et al. | 2015
- 2128
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Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube InterconnectsFarahani, Esmat Kishani / Sarvari, Reza et al. | 2015
- 2135
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Two-Port PCM Architecture for Network ProcessingLi, Jiayin / Dgien, David B. / Hunter, Nathan Altay / Zhao, Yirong / Mohanram, Kartik et al. | 2015
- 2149
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High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware PoliciesLin, Ing-Chao / Chiou, Jeng-Nian et al. | 2015
- 2162
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Efficient Memory-Addressing Algorithms for FFT Processor DesignLuo, Hsin-Fu / Liu, Yi-Jun / Shieh, Ming-Der et al. | 2015
- 2173
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Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIPChen, Xiaolin / Minwegen, Andreas / Hussain, Syed Bilal / Chattopadhyay, Anupam / Ascheid, Gerd / Leupers, Rainer et al. | 2015
- 2187
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A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic CellsGaillardon, Pierre-Emmanuel / Tang, Xifan / Kim, Gain / De Micheli, Giovanni et al. | 2015
- 2198
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SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space ApplicationsDi Carlo, Stefano / Gambardella, Giulio / Prinetto, Paolo / Rolfo, Daniele / Trotta, Pascal et al. | 2015
- 2209
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FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing ReconstructionRabah, Hassan / Amira, Abbes / Mohanty, Basant Kumar / Almaadeed, Somaya / Meher, Pramod Kumar et al. | 2015
- 2221
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Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGAVenkateshan, Sriram / Patel, Alap / Varghese, Kuruvilla et al. | 2015
- 2233
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Feedbacks in QCA: A Quantitative ApproachVacca, Marco / Wang, Juanchi / Graziano, Mariagrazia / Roch, Massimo Ruo / Zamboni, Maurizio et al. | 2015
- 2244
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Domain-Alternated Optimization for Passive MacromodelingYe, Zuochang / Wang, Tianshi / Li, Yang et al. | 2015
- 2256
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Multimode Radix-4 SISO Kernel Design for Turbo/LDPC DecodingLin, Cheng-Hung / Yu, Chih-Shiang et al. | 2015
- 2268
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Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit DecisionYuan, Bo / Parhi, Keshab K. et al. | 2015
- 2281
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VLSI Design of a Depth Map Estimation Circuit Based on Structured Light AlgorithmFan, Yu-Cheng / Huang, Pin-Kang / Liu, Hung-Kuan et al. | 2015
- 2295
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Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS TechnologiesPeng, Chih-Hsiang / Kuan, Ta-Wen / Lin, Po-Chuan / Wang, Jhing-Fa / Wu, Guo-Ji et al. | 2015
- 2307
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HS3-DPG: Hierarchical Simulation for 3-D P/G NetworkWang, Yu / Yao, Song / Tao, Shuai / Chen, Xiaoming / Ma, Yuchun / Shi, Yiyu / Yang, Huazhong et al. | 2015
- 2312
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Implementation of Compact Polyphase Channel-Select Filters for Multistandard BroadcastingAlzaher, Hussain A. / Alghamdi, Mohammad K. et al. | 2015
- 2317
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A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage ReferenceTan, Xiao Liang / Chan, Pak Kwong / Dasgupta, Uday et al. | 2015
- 2322
-
Efficient Scalable Serial Multiplier Over GF( \textbf ^} ) Based on TrinomialGebali, Fayez et al. | 2015
- 2322
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Efficient Scalable Serial Multiplier Over GF( $\textbf {2}^{\boldsymbol {m}}$ ) Based on TrinomialGebali, Fayez / Ibrahim, Atef et al. | 2015
- 2327
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T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis ToolLi, Di-An / Marek-Sadowska, Malgorzata / Nassif, Sani R. et al. | 2015
- 2332
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MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error CorrectionSaiz-Adalid, Luis-J. / Reviriego, Pedro / Gil, Pedro / Pontarelli, Salvatore / Maestro, Juan Antonio et al. | 2015
- 2337
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Memristive Threshold Logic Circuit Design of Fast Moving Object DetectionMaan, Akshay Kumar / Kumar, Dinesh Sasi / Sugathan, Sherin / James, Alex Pappachen et al. | 2015
- 2342
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Low-Complexity High-Throughput QR Decomposition Design for MIMO SystemsLin, Jing-Shiun / Hwang, Yin-Tsung / Fang, Shih-Hao / Chu, Po-Han / Shieh, Ming-Der et al. | 2015
- 2347
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An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic InterferenceSawada, Takuya / Yoshikawa, Kumpei / Takata, Hidehiro / Nii, Koji / Nagata, Makoto et al. | 2015
- 2352
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A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular AutomataPudi, Vikramkumar / Sridharan, K. et al. | 2015
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Table of contents| 2015
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2015
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information| 2015