An Energy Efficient Layered Decoding Architecture for LDPC Decoder (English)
- New search for: Jin, J
- New search for: Jin, J
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In:
IEEE transactions on very large scale integration (VLSI) systems
;
18
, 8
; 1185-1196
;
2010
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ISSN:
- Article (Journal) / Print
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Title:An Energy Efficient Layered Decoding Architecture for LDPC Decoder
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 18, 8 ; 1185-1196
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2010
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ISSN:
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ZDBID:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Source:
Table of contents – Volume 18, Issue 8
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 1145
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A High-Performance Unified-Field Reconfigurable Cryptographic ProcessorJun-Hong Chen, / Ming-Der Shieh, / Wen-Ching Lin, et al. | 2010
- 1145
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Computer Security A High-Performance Unified-Field Reconfigurable Cryptographic ProcessorChen, J-H et al. | 2010
- 1159
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Time-Multiplexed Compressed Test of SOC DesignsKinsman, Adam B / Nicolici, Nicola et al. | 2010
- 1159
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Testing Time-Multiplexed Compressed Test of SOC DesignsKinsman, A B et al. | 2010
- 1173
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Variation-Aware System-Level Power AnalysisChandra, Saumya / Lahiri, Kanishka / Raghunathan, Anand / Dey, Sujit et al. | 2010
- 1173
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Power Analysis and Optimization Variation-Aware System-Level Power AnalysisChandra, S et al. | 2010
- 1185
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An Energy Efficient Layered Decoding Architecture for LDPC DecoderJie Jin, / Chi-ying Tsui, et al. | 2010
- 1196
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C-Pack: A High-Performance Microprocessor Cache Compression AlgorithmXi Chen, / Lei Yang, / Dick, Robert P / Li Shang, / Lekatsas, Haris et al. | 2010
- 1196
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Microprocessors C-Pack: A High-Performance Microprocessor Cache Compression AlgorithmChen, X et al. | 2010
- 1209
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A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance ProcessorsNdai, Patrick / Goel, Ashish / Roy, Kaushik et al. | 2010
- 1220
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On Reducing Test Power and Test Volume by Selective Pattern Compression SchemesChia-Yi Lin, / Hsiu-Chuan Lin, / Hung-Ming Chen, et al. | 2010
- 1220
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TRANSACTIONS BRIEFS On Reducing Test Power and Test Volume by Selective Pattern Compression SchemesLin, C-Y et al. | 2010
- 1225
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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal ProcessingNing Zhu, / Wang Ling Goh, / Weija Zhang, / Kiat Seng Yeo, / Zhi Hui Kong, et al. | 2010
- 1230
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Robust Fault Models Where Undetectable Faults Imply Logic RedundancyPomeranz, Irith / Reddy, Sudhakar M et al. | 2010
- 1234
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Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over ${\rm GF}(2^{m})$ Using Multiple Parity Prediction SchemesChiou-Yng Lee, / Meher, Pramod Kumar / Patra, Jagdish Chandra et al. | 2010
- 1234
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Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over Using Multiple Parity Prediction SchemesLee, C.-Y. / Meher, P.K. / Patra, J.C. et al. | 2010
- 1234
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Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction SchemesLee, C-Y et al. | 2010
- 1238
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Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System IntegrationNiitsu, Kiichi / Kohama, Yoshinori / Sugimori, Yasufumi / Kasuga, Kazutaka / Osada, Kenichi / Irie, Naohiko / Ishikuro, Hiroki / Kuroda, Tadahiro et al. | 2010
- 1243
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On the Power Management of Simultaneous Multithreading ProcessorsYoussef, Ahmed / Zahran, Mohamed / Anis, Mohab / Elmasry, Mohamed et al. | 2010
- 1248
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Register File Partitioning and Compiler Support for Reducing Embedded Processor Power ConsumptionXuan Guan, / Yunsi Fei, et al. | 2010
- 1253
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An Adaptive Algorithm for Single-Electron Device and Circuit SimulationAllec, Nicholas / Knobel, Robert G / Li Shang, et al. | 2010
- 1257
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Low-Cost and Energy-Efficient Distributed Synchronization for Embedded MultiprocessorsChenjie Yu, / Petrov, Peter et al. | 2010
- 1262
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Corrections to "Unified Logical Effort — A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect"Morgenshtein, A et al. | 2010
- 1262
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Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696]Morgenshtein, Arkadiy / Friedman, Eby G. / Ginosar, Ran / Kolodny, Avinoam et al. | 2010
- 1263
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Over 1 million scientific documents| 2010
- 1264
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