Architecture - Raising FPGA Logic Density Through Synthesis-Inspired Architecture (English)
- New search for: Anderson, J H
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In:
IEEE transactions on very large scale integration (VLSI) systems
;
20
, 3
; 537-551
;
2012
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ISSN:
- Article (Journal) / Print
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Title:Architecture - Raising FPGA Logic Density Through Synthesis-Inspired Architecture
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Contributors:
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Published in:IEEE transactions on very large scale integration (VLSI) systems ; 20, 3 ; 537-551
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Publisher:
- New search for: Institute of Electrical and Electronics Engineers
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Place of publication:New York, NY
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Publication date:2012
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ISSN:
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Type of media:Article (Journal)
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Type of material:Print
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Language:English
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Table of contents – Volume 20, Issue 3
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 393
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A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its ApplicationJungwon Han, / Kwisung Yoo, / Dongmyung Lee, / Kangyeop Park, / Wonseok Oh, / Sung Min Park, et al. | 2012
- 393
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Analog Design - A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its ApplicationHan, J et al. | 2012
- 400
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A 3-5 GHz Current-Reuse -Boosted CG LNA for Ultrawideband in 130 nm CMOSKhurram, M. / Hasan, S.M.R. et al. | 2012
- 400
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A 3–5 GHz Current-Reuse $g_{m}$-Boosted CG LNA for Ultrawideband in 130 nm CMOSKhurram, M. / Hasan, S. M. R. et al. | 2012
- 410
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Testing - Test Pattern Generation of Relaxed n-Detect Test SetsNeophytou, S N et al. | 2012
- 410
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Test Pattern Generation of Relaxed $n$-Detect Test SetsNeophytou, S. N. / Michael, M. K. et al. | 2012
- 410
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Test Pattern Generation of Relaxed -Detect Test SetsNeophytou, S.N. / Michael, M.K. et al. | 2012
- 424
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Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate DelaysSanyal, A. / Ganeshpure, K. / Kundu, S. et al. | 2012
- 437
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VLSI Design - Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video CodingNunez-Yanez, J L et al. | 2012
- 437
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Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video CodingNunez-Yanez, J. L. / Nabina, A. / Hung, E. / Vafiadis, G. et al. | 2012
- 449
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Toeplitz Matrix Approach for Binary Field Multiplication Using QuadrinomialsHasan, M. A. / Namin, A. H. / Negre, C. et al. | 2012
- 459
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Physical Design - NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global RoutingDai, K-R et al. | 2012
- 459
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NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global RoutingKe-Ren Dai, / Wen-Hao Liu, / Yih-Lang Li, et al. | 2012
- 473
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SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning ProblemsJai-Ming Lin, / Zhi-Xiong Hung, et al. | 2012
- 485
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ECOS: Stable Matching Based Metal-Only ECO SynthesisJiang, Iris Hui-Ru / Hua-Yu Chang, et al. | 2012
- 498
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A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit OptimizationJiying Xue, / Yangdong Deng, / Zuochang Ye, / Hongrui Wang, / Liu Yang, / Zhiping Yu, et al. | 2012
- 512
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Stack Aware Threshold Voltage Assignment in 3-D Multicore DesignsChakraborty, K. / Roy, S. et al. | 2012
- 512
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Low Power Design - Stack Aware Threshold Voltage Assignment in 3-D Multicore DesignsChakraborty, K et al. | 2012
- 523
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Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution NetworksChattopadhyay, A. / Zilic, Z. et al. | 2012
- 523
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Clocking - Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution NetworksChattopadhyay, A et al. | 2012
- 537
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Raising FPGA Logic Density Through Synthesis-Inspired ArchitectureAnderson, J. H. / Qiang Wang, / Ravishankar, C. et al. | 2012
- 537
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Architecture - Raising FPGA Logic Density Through Synthesis-Inspired ArchitectureAnderson, J H et al. | 2012
- 551
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Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT ProcessingXuan Guan, / Yunsi Fei, / Hai Lin, et al. | 2012
- 564
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TRANSACTIONS BRIEFS - A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 μm CMOSHoyos, S et al. | 2012
- 564
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A 15 MHz to 600 MHz, 20 mW, 0.38 mm $^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$ m CMOSHoyos, S. / Tsang, C. W. / Vanderhaegen, J. / Yun Chiu, / Aibara, Y. / Khorramabadi, H. / Nikolic, B. et al. | 2012
- 564
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A 15 MHz to 600 MHz, 20 mW, 0.38 mm Split-Control, Fast Coarse Locking Digital DLL in 0.13 m CMOSHoyos, S. / Tsang, C.W. / Vanderhaegen, J. / Chiu, Y. / Aibara, Y. / Khorramabadi, H. / Nikolic, B. et al. | 2012
- 568
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High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS CodesGarcia-Herrero, F. / Canet, M. J. / Valls, J. / Meher, P. K. et al. | 2012
- 573
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Enhancing Electromagnetic Analysis Using Magnitude Squared IncoherenceDehbaoui, A. / Lomne, V. / Ordas, T. / Torres, L. / Robert, M. / Maurine, P. et al. | 2012
- 578
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors| 2012
- 579
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- 580
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Table of contents| 2012
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information| 2012
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