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In the design of digital systems for many applications timing is a given constraint. This can be a very general constraint like a given clock cycle range or a rather detailed one as a given bus protocoll. The consequence is that timing forms an essential part of circuit specification, e.g. EDIF: 'In the design of a circuit, it is often necessary to specify the specific timing requirements of a path, or a set of paths'. How are these requirements considered in modern design tools? Timing constraints are often not considered in 'synthesizing' tools such as placement and routing, silicon compilers or behavioural level synthesizers. We present an approach to include timing information in behavioural level specifications, to check its consistency and to use it in the automatic synthesis of circuit structures. Timing is specified in DSL (digital system specification language) by imposing constraints on single operations or on groups of them. This information is represented by attributed graphs. An algorithm to check consistency using these graphs is described. Synthesis requires this timing information during module allocation but also when eventually rearranging operations to increase parallelism or to achieve a better hardware allocation.