Quiescent current estimation based on quality requirements (English)
- New search for: Vargas, F.L.
- New search for: Nicolaidis, M.
- New search for: Hamdi, B.
- New search for: Vargas, F.L.
- New search for: Nicolaidis, M.
- New search for: Hamdi, B.
In:
Annual IEEE VLSI Test Symposium, 11
;
33-39
;
1993
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ISBN:
- Conference paper / Print
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Title:Quiescent current estimation based on quality requirements
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Additional title:Ruhestromschätzung auf Basis von Qualitätsanforderungen
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Contributors:
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Published in:
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Publisher:
- New search for: IEEE Computer Society Press
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Place of publication:Los Alamitos, Washington
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Publication date:1993
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Size:7 Seiten, 7 Bilder, 2 Tabellen, 15 Quellen
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ISBN:
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DOI:
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Type of media:Conference paper
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Type of material:Print
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Language:English
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Keywords:
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Source:
Table of contents conference proceedings
The tables of contents are generated automatically and are based on the data records of the individual contributions available in the index of the TIB portal. The display of the Tables of Contents may therefore be incomplete.
- 0_1
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Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium (Cat. No.93TH0537-1)| 1993
- 4
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A distributed BIST control scheme for complex VLSI devicesZorian, Y. et al. | 1993
- 10
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A new built-in self-test method based on prestored testingEdirisooriya, G. / Edirisooriya, S. / Robinson, J.P. et al. | 1993
- 17
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Minimal hardware multiple signature analysis for BISTYuejian Wu, / Ivanov, A. et al. | 1993
- 21
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Analysis of redundant structures in combinational circuitsIsern, E. / Figueras, J. et al. | 1993
- 25
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Simulation and generation of I/sub DDQ/ tests for bridging faults in combinational circuitsChakravarty, S. / Thadikaran, P.J. et al. | 1993
- 25
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Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational CircuitsChakravarty, S. / Thadikaran, P. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 33
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Quiescent current estimation based on quality requirementsVargas, F.L. / Nicolaidis, M. / Hamdi, B. et al. | 1993
- 40
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An IEEE 1149.1 based voltmeter/oscilloscope in a chipWhetsel, L. et al. | 1993
- 48
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Input and output encoding techniques for on-line error detection in combinational logic circuitsBusaba, F.Y. / Lala, P.K. et al. | 1993
- 55
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Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processingGuoning Liao, et al. | 1993
- 62
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On the check base selection problem for fast addersSparmann, U. et al. | 1993
- 66
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Finitely self-checking circuits and their application on current sensorsNicolaidis, M. et al. | 1993
- 71
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Parallelization methods for circuit partitioning based parallel automatic test pattern generationKlenke, R.H. / Williams, R.D. / Aylor, J.H. et al. | 1993
- 79
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CCSTG: an efficient test pattern generator for sequential circuitsKim, K. / Saluja, K.K. et al. | 1993
- 85
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Explorations of sequential ATPG using Boolean satisfiabilityKonuk, H. / Larrabee, T. et al. | 1993
- 92
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Carafe: an inductive fault analysis tool for CMOS VLSI circuitsJee, A. / Ferguson, F.J. et al. | 1993
- 99
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The effect of defect clustering on test transparency and defect levelsSingh, A.D. / Krishna, C.M. et al. | 1993
- 106
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Computer-aided failure analysis of VLSI circuits using I/sub DDQ/ testingNaik, S. / Maly, W. et al. | 1993
- 106
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Computer-Aided Failure Analysis of VLSI Circuits Using IDDQ TestingNaik, S. / Maly, W. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 109
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Fault injection scan design for enhanced VLSI design verificationChau, S. et al. | 1993
- 112
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Classification of bridging faults in CMOS circuits: experimental results and implications for testMidkiff, S.F. / Bollinger, S.W. et al. | 1993
- 116
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On CMOS bridge fault modeling and test pattern evaluationchennian Di, / Jess, J.A.G. et al. | 1993
- 120
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Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probingTaenzler, F. / Novak, T. / Kubalek, E. et al. | 1993
- 124
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Generation of testable designs from behavioral descriptions using high level synthesis toolsVarma, K.K. / Vishakantaiah, P. / Abraham, J.A. et al. | 1993
- 131
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Testability preserving Boolean transforms for logic synthesisKundu, S. / Pramanick, A.K. et al. | 1993
- 139
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Testability analysis based on structural and behavioral informationLee, J. / Patel, J.H. et al. | 1993
- 147
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On the design for testability of sequential circuitsSun, X. / Lombardi, F. et al. | 1993
- 151
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Revisiting shift register realization for ease of test generation and testingToida, S. et al. | 1993
- 154
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Controllability and observability measures for functional-level testability evaluationJamoussi, M. / Kaminska, B. et al. | 1993
- 159
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Defect-tolerant cache memory designLamet, D. / Frenzel, J.F. et al. | 1993
- 164
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Design SRAMs for burn-inReohr, W. / Yuen Chan, / Plass, D. / Pelella, A. / Wu, P. et al. | 1993
- 171
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ECC design of a custom DRAM storage unitPeter, J.-L. et al. | 1993
- 174
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Concurrent error correction in iterative circuits by recomputing with partitioning and votingAl-Asaad, H. / Czeck, E. et al. | 1993
- 178
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Testability of one dimensional ILAs under multiple faultsGala, M.M.R. / Watson, K.L. / Ross, D.E. et al. | 1993
- 182
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Degrading fault model for WSI interconnection linesAbujbara, H.Y. / Al-Arian, S.A. et al. | 1993
- 187
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Worst-case analysis for pseudorandom testingMarculescu, R. et al. | 1993
- 194
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Signal probability calculations using partial functional manipulationKodavarti, R. / Ross, D.E. et al. | 1993
- 201
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LFSR based deterministic hardware for at-speed BISTVasudevan, B. / Ross, D.E. / Gala, M. / Watson, K.L. et al. | 1993
- 208
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LFSROM an algorithm for automatic design synthesis of hardware test pattern generatorDufaza, C. / Chevalier, C. / Lew Yan Voon, L.F.C. et al. | 1993
- 215
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Does High Test Quality Mean High Cost Testers?Wu, D. / Hall, F. / Dervisoglu, B. / Miranda, J. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 216
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What's Ahead for Synthesis for Testability?Cheng, K. / Jha, N. / Devadas, S. / Ma, T. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 218
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Improvement of analog circuit fault detectability using fault detection observersVermeiren, W. / Straube, B. / Elst, G. et al. | 1993
- 225
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Hard faults diagnosis in analog circuits using sensitivity analysisYunsheng Lu, / Dandapani, R. et al. | 1993
- 230
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Automatic synthesis of DUT board circuits for testing of mixed signal ICsKao, W.H. / Xia, J.Q. et al. | 1993
- 238
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A neural inverse function for automatic test pattern generation using strictly digital neural networksArai, M. / Nakagawa, T. / Kitagawa, H. et al. | 1993
- 244
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Incremental test pattern generationSang-Hoon Song, / Kinney, L.L. et al. | 1993
- 251
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Combinational circuit ATPG using binary decision diagramsSrinivasan, S. / Swaminathan, G. / Aylor, J.H. / Mercer, M.R. et al. | 1993
- 260
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Aliasing-free error detection (ALFRED)Chakrabarty, K. / Hayes, J.P. et al. | 1993
- 267
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On the maximum value of aliasing probabilities for single input signature registersShou-ping Feng, / Fujiwara, T. / Kasami, T. / Iwasaki, K. et al. | 1993
- 275
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Time and space correlated errors in signature analysisEdirisooriya, G. / Edirisooriya, S. / Robinson, J.P. et al. | 1993
- 282
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Aliasing computation using fault simulation with fault droppingPomeranz, I. / Reddy, S.M. et al. | 1993
- 290
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Physical design for testability for bridges in CMOS circuitsFerguson, F.J. et al. | 1993
- 296
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Testable design for BiCMOS stuck-open fault detectionMenon, S.M. / Jayasumana, A.P. / Malaiya, Y.K. et al. | 1993
- 303
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On diagnosis of faults in a scan-chainKundu, S. et al. | 1993
- 309
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Impact of high level functional constraints on testabilityLee, J. / Chickermane, V. / Patel, J.H. et al. | 1993
- 313
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Partial scan testing with single clock controlAgrawal, V.D. / Charkraborty, T.J. et al. | 1993
- 316
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National Center for Dependable SystemsDebany, W. / Abraham, J. / Iyer, R. / Levendel, Y. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 317
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Has Sequential ATPG Come of Age?Varma, P. / Bennets, B. / Chakraborty, T. / Chandramouli, R. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 319
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Estimation of reject ratio in testing of combinatorial circuitsGaitonde, D.D. / Khare, J. / Walker, D.M.H. / Maly, W. et al. | 1993
- 326
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Functional verification and simulation of FSM networksHasan, Z. / Ciesielski, M.J. et al. | 1993
- 326
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Functional Verification & Simulation of FSM NetworksHasan, Z. / Ciesielski, M. / IEEE Computer Society; Test Technology Technical Committee / Institute of Electrical and Electronics Engineers; Philadelphia Section et al. | 1993
- 333
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A structured design for test methodologyVenkat, K. et al. | 1993
- 337
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A model for testing reliable VLSI routing architecturesStivaros, C. et al. | 1993
- 341
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On parallel switch level fault simulationRyan, C.A. / Tront, J.G. et al. | 1993
- 348
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Evaluation of test generation algorithmsYinghua Min, / Zhongcheng Li, et al. | 1993
- 351
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Simulation of non-classical faults on the gate level-fault modelingAlt, J. / Mahlstedt, U. et al. | 1993
- 355
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Sensitivity analysis of a radiation immune CMOS logic family under defect conditionsIngermann, E.H. / Frenzel, J.F. et al. | 1993
- 358
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Pattern generator card, emulation, and debugDunn, S.M. / Balazich, D.G. / Lange, L.K. / Montillo, C.C. et al. | 1993