Bandwidth extension, linearity enhancement, and cost reduction techniques for continuous‐time channel‐select filters (English)

Achieving a wide bandwidth in a conventional active‐RC filter requires large power consumption and is often accompanied by significant performance degradation. In this paper, a new structure to implement active‐RC continuous‐time filters and also a new frequency compensation scheme for the operational amplifiers that are the main building blocks of active‐RC filters are proposed. Exploiting these techniques increases the maximum possible bandwidth with lower power consumption in comparison with the conventional architectures, reduces die area, and enhances the dynamic range. The effectiveness of these methods has been verified by analysis and simulation of the conventional and proposed filters under identical conditions. Both the analytical investigations and extensive simulation results prove that the adopted techniques improve the performance of continuous‐time filters considerably in terms of bandwidth and linearity while reducing the die area. Simulations have been carried out in a standard 90‐nm CMOS process by using Advanced Design System (ADS), and the proposed filter features 11.08‐dB spurious‐free dynamic range improvement and 5.9 times bandwidth enhancement. Also, the total on‐chip capacitance is made 2.4 times smaller by using the new biquad structure. Copyright © 2016 John Wiley & Sons, Ltd.