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Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration
British Library Online Contents | 2016| -
Investigation of Local Bending Stress Effect on Complementary Metal-Oxide-Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration (5 pages)
British Library Conference Proceedings | 2013| -
MOSFET nonvolatile memory with a high-density tungsten nanodot floating gate formed by self-assembled nanodot deposition
British Library Online Contents | 2009| -
3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration
British Library Online Contents | 2017| -
MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and $hbox{HfO} {bf 2}$ High-k Blocking Dielectric
British Library Online Contents | 2011| -
Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film
British Library Online Contents | 2014| -
Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film
British Library Online Contents | 2014| -
Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice
British Library Online Contents | 2014| -
Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice
British Library Online Contents | 2014| -
The Formation of Lateral Interconnections Extending over 100-μm-Thick Chips
British Library Conference Proceedings | 2008|
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