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Formal Semantics and Proof Techniques for Optimizing VHDL Models [1999]
- 1
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Introduction
- 7
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Related Work
- 17
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The Static Model
- 31
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A Well-Formed VHDL Model
- 43
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The Reduction Algebra
- 55
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Completeness of the Reduced Form
- 65
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Interval Temporal Logic
- 69
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The Dynamic Model
- 89
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Applications of the Dynamic Model
- 99
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A Framework for Proving Equivalences using PVS
- 123
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Conclusions
