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Field Programmable Logic and Applications [1999]

1
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
11
Auditory Signal Processing in Hardware
21
SONIC – A Plug-In Architecture for Video Processing
31
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems
41
Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework
51
Optimal Finite Field Multipliers for FPGAs
61
Memory Access Optimization and RAM Inference for Pipeline Vectorization
71
Analysis and Optimization of 3-D FPGA Design Parameters
81
Tabu Search: Ultra-Fast Placement for FPGAs
91
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies
101
Hierarchical Interactive Approach to Partition Large Designs into FPGAs
111
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
124
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
134
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic
144
Self Controlling Dynamic Reconfiguration: A Case Study
155
An Internet Based Development Framework for Reconfigurable Computing
165
On Tool Integration in High-Performance FPGA Design Flows
175
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
185
Serial Hardware Libraries for Reconfigurable Designs
195
Reconfigurable Computing in Remote and Harsh Environments
205
Communication Synthesis for Reconfigurable Embedded Systems
215
Run-Time Parameterizable Cores
223
Rendering PostScript <Superscript>TM</Superscript> Fonts on FPGAs
233
Implementing PhotoShop<Superscript>TM</Superscript> Filters in Virtex<Superscript>TM</Superscript>
243
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler
253
Quantitative Analysis of Run-Time Reconfigurable Database Search
264
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing
274
A New Switch Block for Segmented FPGAs
282
PulseDSP – A Signal Processing Oriented Programmable Architecture
291
FPGA Viruses
301
Genetic Programming Using Self-Reconfigurable FPGAs
313
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs
323
<Emphasis Type="Italic">Synthia</Emphasis>: Synthesis of Interacting Automata Targeting LUT-based FPGAs
333
An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes
339
An FPGA Implementation of Goertzel Algorithm
347
Pipelined Multipliers and FPGA Architectures
353
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding
359
Reconfigurable Multiplier for Virtex FPGA Family
365
Pipelined Floating Point Arithmetic Optimised for FPGA Architectures
371
SL – A Structural Hardware Design Language
377
High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules
385
Mapping Applications onto Reconfigurable KressArrays
391
Global Routing Models
396
Power Modelling in Field Programmable Gate Arrays (FPGA)
405
NEBULA: A Partially and Dynamically Reconfigurable Architecture
411
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects
417
AHA-GRAPE: Adaptive Hydrodynamic Architecture – GRAvity PipE
425
DIME – The First Module Standard for FPGA Based High Performance Computing
431
The Proteus Processor — A Conventional CPU with Reconfigurable Functionality
438
Logic Circuit Speeding up through Multiplexing
444
A Wildcarding Mechanism for Acceleration of Partial Configurations
450
Hardware Implementation Techniques for Recursive Calls and Loops
456
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation
462
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis
469
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array’s: An Integrated Approach Based on Reconfigurable Virtual Architectures
475
A Concept for an Evaluation Framework for Reconfigurable Systems
481
Debugging Application-Specific Programmable Products
487
IP Validation for FPGAs Using Hardware Object Technology<Superscript>TM</Superscript>
495
A Processor for Artificial Life Simulation
501
A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGA’s
507
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching
514
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing
520
Seeking (the Right) Problems for the Solutions of Reconfigurable Computing
526
A Runtime Reconfigurable Implementation of the GSAT Algorithm
532
Accelerating Boolean Implications with FPGAs
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