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1
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Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
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11
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Auditory Signal Processing in Hardware
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21
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SONIC – A Plug-In Architecture for Video Processing
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31
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DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems
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41
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Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework
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51
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Optimal Finite Field Multipliers for FPGAs
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61
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Memory Access Optimization and RAM Inference for Pipeline Vectorization
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71
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Analysis and Optimization of 3-D FPGA Design Parameters
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81
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Tabu Search: Ultra-Fast Placement for FPGAs
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91
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Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies
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101
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Hierarchical Interactive Approach to Partition Large Designs into FPGAs
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111
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Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
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124
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DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
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134
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A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic
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144
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Self Controlling Dynamic Reconfiguration: A Case Study
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155
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An Internet Based Development Framework for Reconfigurable Computing
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165
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On Tool Integration in High-Performance FPGA Design Flows
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175
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Hardware-Software Codesign for Dynamically Reconfigurable Architectures
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185
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Serial Hardware Libraries for Reconfigurable Designs
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195
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Reconfigurable Computing in Remote and Harsh Environments
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205
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Communication Synthesis for Reconfigurable Embedded Systems
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215
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Run-Time Parameterizable Cores
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223
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Rendering PostScript <Superscript>TM</Superscript> Fonts on FPGAs
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233
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Implementing PhotoShop<Superscript>TM</Superscript> Filters in Virtex<Superscript>TM</Superscript>
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243
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Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler
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253
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Quantitative Analysis of Run-Time Reconfigurable Database Search
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264
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An On-Line Arithmetic Based FPGA for Low-Power Custom Computing
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274
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A New Switch Block for Segmented FPGAs
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282
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PulseDSP – A Signal Processing Oriented Programmable Architecture
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291
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FPGA Viruses
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301
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Genetic Programming Using Self-Reconfigurable FPGAs
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313
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Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs
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323
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<Emphasis Type="Italic">Synthia</Emphasis>: Synthesis of Interacting Automata Targeting LUT-based FPGAs
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333
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An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes
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339
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An FPGA Implementation of Goertzel Algorithm
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347
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Pipelined Multipliers and FPGA Architectures
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353
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FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding
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359
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Reconfigurable Multiplier for Virtex FPGA Family
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365
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Pipelined Floating Point Arithmetic Optimised for FPGA Architectures
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371
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SL – A Structural Hardware Design Language
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377
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High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules
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385
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Mapping Applications onto Reconfigurable KressArrays
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391
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Global Routing Models
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396
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Power Modelling in Field Programmable Gate Arrays (FPGA)
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405
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NEBULA: A Partially and Dynamically Reconfigurable Architecture
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411
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High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects
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417
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AHA-GRAPE: Adaptive Hydrodynamic Architecture – GRAvity PipE
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425
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DIME – The First Module Standard for FPGA Based High Performance Computing
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431
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The Proteus Processor — A Conventional CPU with Reconfigurable Functionality
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438
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Logic Circuit Speeding up through Multiplexing
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444
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A Wildcarding Mechanism for Acceleration of Partial Configurations
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450
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Hardware Implementation Techniques for Recursive Calls and Loops
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456
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A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation
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462
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An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis
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469
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Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array’s: An Integrated Approach Based on Reconfigurable Virtual Architectures
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475
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A Concept for an Evaluation Framework for Reconfigurable Systems
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481
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Debugging Application-Specific Programmable Products
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487
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IP Validation for FPGAs Using Hardware Object Technology<Superscript>TM</Superscript>
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495
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A Processor for Artificial Life Simulation
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501
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A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGA’s
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507
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Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching
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514
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A Reconfigurable Architecture for High Speed Computation by Pipeline Processing
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520
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Seeking (the Right) Problems for the Solutions of Reconfigurable Computing
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526
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A Runtime Reconfigurable Implementation of the GSAT Algorithm
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532
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Accelerating Boolean Implications with FPGAs