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Defect and Fault Tolerance in VLSI Systems [1990]
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Fault-Free or Fault-Tolerant VLSI Manufacture
- 15
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Yield Models - Comparative Study
- 33
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A Unified Approach to Yield Analysis of Defect Tolerant Circuits
- 47
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Systematic Extraction of Critical Areas From IC Layouts
- 63
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The Effect on Yield of Clustering and Radial Variations in Defect Density
- 75
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Practical Experiences in the Design of a Wafer Scale 2-D Array
- 89
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Yield Evaluation of a Soft-Configurable WSI Switch Network
- 99
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ASP Modules: WSI Building-Blocks for Cost-Effective Parallel Computing
- 111
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Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection
- 123
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Extended Duplex Fault Tolerant System With Integrated Control Flow Checking
- 135
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Experience in Functional Test and Fault Coverage in a Silicon Compiler
- 149
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APES: An Evaluation Environment of Fault-Tolerance Capabilities of Array Processors
- 161
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Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays
- 173
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An Integer Linear Programming Approach to General Fault Covering Problems
- 185
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Probabilistic Analysis of Memory Repair and Reconfiguration Heuristics
- 197
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Arithmetic-Based Diagnosis in VLSI Array Processors
- 209
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Yield Improvement Through X-RAY Lithography
- 219
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Reliability Analysis of Application-Specific Architectures
- 227
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Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processor
- 241
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Yield Model with Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis with Confidence Limits
- 253
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SRAM/TEG Yield Methodology
- 267
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A Fault Detection and Tolerance Tradeoff Evaluation Methodology for VLSI Systems
- 283
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A Hyhpercube Design on WSI
- 295
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An Efficient Reconfiguration Scheme for WSI of Cube-Connected Cycles with Bounded Channel Width
- 305
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A Communication Scheme for Defect Tolerant Arrays