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3D Interconnect Architectures for Heterogeneous Technologies [2022]
- 1
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Introduction to 3D Technologies
- 2
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Interconnect Architectures for 3D Technologies
- 3
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High-Level Formulas for the 3D-Interconnect Power Consumption and Performance
- 4
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High-Level Estimation of the 3D-Interconnect Capacitances
- 5
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Models for Application Traffic and 3D-NoC Simulation
- 6
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Estimation of the Bit-Level Statistics
- 7
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Ratatoskr: A Simulator for NoCs in Heterogeneous 3D SoCs
- 8
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Low-Power Technique for 3D Interconnects
- 9
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Low-Power Technique for High-Performance 3D Interconnects
- 10
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Low-Power Technique for High-Performance 3D Interconnects in the Presence of Temporal Misalignment
- 11
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Low-Power Technique for Yield-Enhanced 3D Interconnects
- 12
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Heterogeneous Buffering for 3D NoCs
- 13
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Heterogeneous Routing for 3D NoCs
- 14
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Heterogeneous Virtualisation for 3D NoCs
- 15
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Network Synthesis and SoC Floor Planning
- 16
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Conclusion