IEEE Design & Test of Computers
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
Inhaltsverzeichnis
- 4
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Panel Summaries| 1995
- 6
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The EDA business model dialogue part 1Prabhu, A. et al. | 1995
- 6
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Management Perspectives in EDA| 1995
- 8
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News| 1995
- 9
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Testing embedded memories [New Products]| 1995
- 9
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VLSI test system [New Products]| 1995
- 9
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SCSI emulation system [New Products]| 1995
- 9
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New Products| 1995
- 9
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Embedded MPU emulator [New Products]| 1995
- 10
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Conference reportsSheppard, J.W. et al. | 1995
- 10
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SCC20 to work with IECSheppard, J.W. et al. | 1995
- 11
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1995 Workshop on Electronic Design ProcessesRosenthal, C.W. et al. | 1995
- 12
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Accelerating the pace of R&D in AsiaYamada, T. et al. | 1995
- 12
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Guest Editor's Introduction: Accelerating the Pace of R&D in AsiaYamada, Teruhiko et al. | 1995
- 14
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Identifying untestable faults in sequential circuitsHsing-Chung Liang, / Chung Len Lee, / Chen, J.E. et al. | 1995
- 15
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Identifying faults| 1995
- 22
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Design and test in Taiwan| 1995
- 24
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Concurrent error detection using monitoring machinesParekhji, R. / Venkatesh, G. / Sherlekar, S.D. et al. | 1995
- 28
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Design and test in India| 1995
- 32
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Call for Articles| 1995
- 34
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Localizing multiple faults in a protocol implementationKakuda, Y. / Yukitomo, H. / Kusumoto, S. et al. | 1995
- 38
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Protocol testing research| 1995
- 42
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Moving Coupon| 1995
- 43
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Editorial Calendar| 1995
- 44
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Multiple fault diagnosis by sensitizing input pairsYanagida, N. / Takahashi, H. / Takamatsu, Y. et al. | 1995
- 45
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Fault diagnosis in Japan| 1995
- 47
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Subcircuit diagnostic process| 1995
- 48
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Value deduction algorithm| 1995
- 53
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Plug-and-Play IDDQ Testing for Test FixturesBaker, Keith et al. | 1995
- 53
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Plug-and-play I/sub DDQ/ Testing for test fixturesBaker, K. / Hales, A. et al. | 1995
- 54
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Total observability| 1995
- 57
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QTAG| 1995
- 62
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Achieving IDDQ-ISSQ Production Testing with QuiC-MonWallquist, Kenneth M. et al. | 1995
- 62
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Achieving I/sub DDQ/I/sub SSQ/ production testing with QuiC-Wallquist, K.M. et al. | 1995
- 70
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Profile-driven behavioral synthesis for low-power VLSI systemsKumar, N. / Katkoori, S. / Rader, L. et al. | 1995
- 71
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Behavioral synthesis| 1995
- 85
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CS Information Page| 1995
- 86
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Industrial BIST of embedded RAMsCamurati, P. / Prinetto, P. / Reorda, M.S. et al. | 1995
- 92
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Derivation of P/sub 3F/| 1995
- 96
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A D&T Roundtable: Applying Formal Verification| 1995
- 96
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The practical application of formal verification| 1995
- 103
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Metrics - Jack Woida [Conference Reports]| 1995
- 103
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Self-empowered teams - Margarida Jacome [Conference Reports]| 1995
- 103
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Process modeling and management - Naresh Sehgal [Conference Reports]| 1995
- 104
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Timing verification [New Products]| 1995
- 104
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DIMMs for portables, printers [New Products]| 1995
- 104
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Real-time SPOX operating system [New Products]| 1995
- 104
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ADC for wireless LANs [New Products]| 1995
- 104
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VxWorks, Version 5.2 [New Products]| 1995
- 104
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i960 support [New Products]| 1995
- 105
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Sbus system interface [New Products]| 1995
- 105
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Embedded systems cards [New Products]| 1995
- 105
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LAN/WAN analyzer [New Products]| 1995
- 108
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DATC Newsletter| 1995
- 110
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TTTC Newsletter| 1995