IEEE Design & Test of Computers
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
Inhaltsverzeichnis
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DEPARTMENTS - From the EIC| 1999
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Origin of the stuck-at model [Letter to the Editor]Bennetts, B. et al. | 1999
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DEPARTMENTS - News -- ITC99 Two Associate EICs announced; IBM's SOC technology, DAC 99; real-time multimedia| 1999
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DEPARTMENTS - Letter to the Editor| 1999
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System-on-chip design: impact on education and researchDe Man, H. et al. | 1999
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FEATURES - Guest Editors' Introduction: Test and the Product Life CycleAmbler, Tony et al. | 1999
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Guest Editor's Introduction: test and product life cycleAmbler, T. / Bennetts, B. et al. | 1999
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Introduction: Test and the Product Life CycleAmbler, T. / Bennetts, B. et al. | 1999
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FEATURES - Design for Test and rime to Market: A Personal Perspective - Just what is DM Why is it still such an important aspect of IC design?Turino, Jon et al. | 1999
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Design for test and time to market: a personal perspectiveTurino, J. et al. | 1999
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FEATURES - Board Test and the Product Life Cycle: Get Wise to Board Test Strategies - To understand the challenges ahead in board test, we need to change our thinkingSutton, Bernard et al. | 1999
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Board test and the product life cycle. Get wise to board test strategiesSutton, B. et al. | 1999
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FEATURES - Boundary Scan: The Internet of Test - Once we incorporate boundary scan, there is little or no barrier to porting the same tests to another design level or life cycle phaseWondolowski, Mike et al. | 1999
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Boundary scan: the Internet of testWondolowski, M. / Bennetts, B. / Ley, A. et al. | 1999
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FEATURES - Automating PBX System Testing - TTCN-based tests are automatic, effective, reusable, robust, and easy to maintainWeber, Bertram et al. | 1999
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Automating PBX system testingWeber, B. et al. | 1999
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FEATURES - Generating Functional Design Verification Tests - Ford engineers successfully apply this strategy in a cost-conscious environment demanding high quality and fast test turnaroundStoica, Susana et al. | 1999
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Generating functional design verification testsStoica, S. et al. | 1999
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Test and reliability: partners in IC manufacturing. 1Hawkins, C.F. / Segura, J. et al. | 1999
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SPECIAL FEATURES - Test and Reliability: Partners in IC Manufacturing, Part I - Part I of this two-part series discusses the dominant metal-failure mechanismsHawkins, Charles F. et al. | 1999
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Test and reliability: partners in IC manufacturing. IHawkins, C.F. / Segura, J. et al. | 1999
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Test and Reliability: Partners in IC Manufacturing, Part 1Hawkins, C. F. / Segura, J. et al. | 1999
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Unveiling the ISCAS-85 Benchmarks: Reverse EngineeringHansen, M. C. / Yalcin, H. / Hayes, J. P. et al. | 1999
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SPECIAL FEATURES - Unveiling the ISCAS-85 Benchmarks A Case Study in Reverse Engineering - The lack of usable high-level benchmark circuits to evaluate tool quality and performance handicaps requires new CAD tool researchHansen, Mark C. et al. | 1999
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Unveiling the ISCAS-85 benchmarks: a case study in reverse engineeringHansen, M.C. / Yalcin, H. / Hayes, J.P. et al. | 1999
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Economic online self-test in the time-triggered architectureSteininger, A. / Temple, C. et al. | 1999
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SPECIAL FEATURES - Economic Online Self-Test in the Time-Triggered Architecture - The properties of this time-driven architecture facilitate cost-efficient self-testing without compromising system responsivenessSteininger, Andreas et al. | 1999
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Fault-Secure Parity Prediction Bomb MultipliersNicolaidis, M. / Duarte, R. O. et al. | 1999
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Fault-secure parity prediction Booth multipliersNicolaidis, M. / Duarte, R.O. et al. | 1999
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SPECIAL FEATURES - Fault-Secure Parity Prediction Booth Multipliers - Hardware efficiency for a wide range of multiplier sizes is possible with this self-checking structureNicolaidis, Michael et al. | 1999
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Testing methodology for FireWireMelatii, L. / Blancha, B. et al. | 1999
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SPECIAL FEATURES - Testing Methodology for FireWire - To achieve cost-effective production, short execution time, and accurate test result goals, use this test methodology for the IEEE 1394 bus interfaceMelatti, Lee et al. | 1999
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RF integration into CMOS and deep-submicron challenges| 1999
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SPECIAL FEATURES - A D&T Roundtable: RF Integration Into CMOS and Deep-Submicron Challenges| 1999
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DEPARTMENTS - Panel Summary -- CAD Tools for Core Test, Moore's Law| 1999
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DEPARTMENTS - Conference Report -- MSTW 99| 1999
- 121
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DEPARTMENTS - Standards -- STIL extension; 1149 updates; SCC20 status| 1999
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DEPARTMENTS - Subscription form| 1999
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DEPARTMENTS - DATC Newsletter| 1999
- 125
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DEPARTMENTS - Computer Society Information| 1999
- 126
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DEPARTMENTS - MC Newsletter| 1999
- 128
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DEPARTMENTS - The Last Byte -- Analog, digital, and mixed-signal people| 1999