Programmable Deterministic Built-in Self-test (Englisch)
- Neue Suche nach: Hakmi, A.-W.
- Neue Suche nach: Wunderlich, H.-J.
- Neue Suche nach: Zoellin, C.G.
- Neue Suche nach: Glowatz, A.
- Neue Suche nach: Hapke, F.
- Neue Suche nach: Schloeffel, J.
- Neue Suche nach: Souef, L.
- Neue Suche nach: Institute of Electrical and Electronics Engineers
- Neue Suche nach: Hakmi, A.-W.
- Neue Suche nach: Wunderlich, H.-J.
- Neue Suche nach: Zoellin, C.G.
- Neue Suche nach: Glowatz, A.
- Neue Suche nach: Hapke, F.
- Neue Suche nach: Schloeffel, J.
- Neue Suche nach: Souef, L.
- Neue Suche nach: Institute of Electrical and Electronics Engineers
In:
IEEE international test conference
;
476-484
;
2007
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:Programmable Deterministic Built-in Self-test
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Beteiligte:Hakmi, A.-W. ( Autor:in ) / Wunderlich, H.-J. ( Autor:in ) / Zoellin, C.G. ( Autor:in ) / Glowatz, A. ( Autor:in ) / Hapke, F. ( Autor:in ) / Schloeffel, J. ( Autor:in ) / Souef, L. ( Autor:in ) / Institute of Electrical and Electronics Engineers
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Kongress:IEEE international test conference ; 2007 ; Santa Clara, CA
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Erschienen in:IEEE international test conference ; 476-484INTERNATIONAL TEST CONFERENCE ; 476-484
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsort:Piscataway
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Erscheinungsdatum:01.01.2007
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Format / Umfang:9 pages
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Anmerkungen:Includes bibliographical references and index. Part 1 of 2
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Which defects are most critical? optimizing test sets to minimize failures due to test escapesDworak, Jennifer L. et al. | 2007
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X-canceling MISR — An X-tolerant methodology for compacting output responses with unknowns using a MISRTouba, Nur A. et al. | 2007
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Finding power/ground defects on connectors — a new approachParker, Kenneth P. / Hird, Stephen et al. | 2007
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Pattern-directed circuit virtual partitioning for test power reductionQiang Xu, / Dianwei Hu, / Dong Xiang, et al. | 2007
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A novel scheme to reduce power supply noise for high-quality at-speed scan testingXiaoqing Wen, / Kohei Miyase, / Seiji Kajihara, / Tatsuya Suzuki, / Yuta Yamato, / Girard, Patrick / Yuji Ohsumi, / Laung-Terng Wang, et al. | 2007
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A methodology for detecting performance faults in microprocessors via performance monitoring hardwareHatzimihail, M. / Psarakis, M. / Gizopoulos, D. / Paschalis, A. et al. | 2007
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Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patternsBhargava, Gaurav / Meehl, Dale / Sage, James et al. | 2007
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Sigma-delta ADC characterization using noise transfer function pole-zero trackingHochul Kim, / Kye-shin Lee, et al. | 2007
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At-speed scan tests: A reality at LSIKrishnamurthy, Prabhu et al. | 2007
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How can the results of silicon debug justify the investment in design-for- debug infrastructure?Gottlieb, Bob et al. | 2007
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Design-for-debug to address next-generation soc debug concernsVermeulen, Bart et al. | 2007
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Panel synopsis: Where is car IC testing going?Yukio Okuda, et al. | 2007
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How to ensure zero defects from the beginning with semiconductor test methodsGessner, Bernd et al. | 2007
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Fully X-tolerant combinational scan compressionWohl, P. / Waicukauski, J.A. / Ramnath, S. et al. | 2007
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High throughput non-contact SiP testingMoore, B. / Sellathamby, C. / Cauvet, P. / Fleury, H. / Paulson, M. / Reja, M. / Fu, L. / Bai, B. / Reid, E. / Filanovsky, I. et al. | 2007
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Programmable deterministic Built-In Self-TestHakmi, Abdul-Wahid / Wunderlich, Hans-Joachim / Zoellin, Christian G. / Glowatz, Andreas / Hapke, Friedrich et al. | 2007
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SPARTAN: a spectral and information theoretic approach to partial-scanKhan, Omar I. / Bushnell, Michael L. / Devanathan, Suresh K. / Agrawal, Vishwani D. et al. | 2007
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Does test have a greater role to play in the DFM process?Venkataraman, Srikanth et al. | 2007
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Fast and effective fault simulation for path delay faults based on selected testable pathsDong Xiang, / Yang Zhao, / Kaiwei Li, / Hideo Fujiwara, et al. | 2007
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Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled DefectsGeuzebroek, Jeroen / Marinissen, Erik Jan / Majhi, Ananta / Glowatz, Andreas / Hapke, Friedrich et al. | 2007
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At-speed scan tests: Reality or fantasy?Dhiraj Goswami, / Nilanjan Mukherjee, et al. | 2007
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At-speed scan tests are a reality (and a necessity)Giles, Grady et al. | 2007
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Is IEEE Std 1149.1 running out of gas? no way!Parker, Kenneth P. et al. | 2007
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ITC 2007 panel session the new ATE: Protocol awareEvans, Andrew C. et al. | 2007
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Protocol-aware ATE: Complement or competitor for structural testing?Sunter, Stephen et al. | 2007
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Statistical test: A new paradigm to improve test effectiveness & efficiencyO'Neill, Peter M. et al. | 2007
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Silicon evaluation of longest path avoidance testing for small delay defectsRitesh Turakhia, / Daasch, W. Robert / Ward, Mark / Van Slyke, John et al. | 2007
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A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan testDevanathan, V.R. / Ravikumar, C.P. / Kamakoti, V. et al. | 2007
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A bead probe CAD strategy for in-circuit testParker, Kenneth P. / DeMille, Don et al. | 2007
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Achieving high transition delay fault coverage with partial DTSFF scan chainsGefu Xu, / Singh, Adit D. et al. | 2007
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Management of common-mode currents in semiconductor ATEBowhers, William J. et al. | 2007
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Using built-in sensors to cope with long duration transient faults in future technologiesLisboa, C. A. / Kastensmidt, F. L. / Henes Neto, E. / Wirht, G. / Carro, L. et al. | 2007
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A universal DC to logic performance correlationMarshall, Andrew et al. | 2007
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Design for test features of the ARM clock control macroFrederick, Frank / McLaurin, Teresa et al. | 2007
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Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chipAbuhamdeh, Zahi / D'Alassandro, Vincent / Pico, Richard / Montrone, Dale / Crouch, Alfred / Tracy, Andrew et al. | 2007
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Efficient power droop aware delay fault testingBin Li, / Lei Fang, / Hsiao, Michael S. et al. | 2007
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Functional testing of digital microfluidic biochipsTao Xu, / Chakrabarty, Krishnendu et al. | 2007
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A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTsJing Li, / Ghosh, Swaroop / Roy, Kaushik et al. | 2007
- 1
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Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching networkGray, C.E. / Ladouceur, O. Liboiron- / Keezer, D.C. / Bergman, K. et al. | 2007
- 1
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Power-aware test: Challenges and solutionsSrivaths Ravi, et al. | 2007
- 1
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Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutionsBhunia, Swarup / Roy, Kaushik et al. | 2007
- 1
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Circuit failure prediction to overcome scaled CMOS reliability challengesSubhasish Mitra, / Mridul Agarwal, et al. | 2007
- 1
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A practical approach to comprehensive system test & debug using boundary scan based test architectureChakraborty, Tapan J. / Chen-Huan Chiang, / Van Treuren, Bradford G. et al. | 2007
- 1
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At-speed structural test: Getting more real every dayButler, Kenneth M. et al. | 2007
- 1
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Position paper: boundary-scan: built to last?Whetsel, Lee et al. | 2007
- 1
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Protocol-Aware ATE enables cooperative test between DUT and ATE for improved TTM and test qualityRivoir, Jochen et al. | 2007
- 1
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On-chip timing uncertainty measurements on IBM microprocessorsFranch, R. / Restle, P. / James, N. / Huott, W. / Friedrich, J. / Dixon, R. / Weitzel, S. / Van Goor, K. / Salem, G. et al. | 2007
- 1
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New methods for receiver internal jitter measurementLi, Mike P. / Jinhua Chen, et al. | 2007
- 1
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Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCsQiang Xu, / Yubin Zhang, / Krishnendu Chakrabarty, et al. | 2007
- 1
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Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniquesLeininger, Andreas / Fischer, Martin / Braun, Michael / Richter, Michael / Goessel, Michael et al. | 2007
- 1
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A complete test set to diagnose scan chain failuresRuifeng Guo, / Yu Huang, / Wu-Tung Cheng, et al. | 2007
- 1
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Multi-GHz loopback testing using MEMs switches and SiGe logicKeezer, D.C. / Minier, D. / Ducharme, P. / Viens, D. / Flynn, G. / McKillop, J. S. et al. | 2007
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Mining-guided state justification with partitioned navigation tracksAnkur Parikh, / Weixin Wu, / Hsiao, Michael S. et al. | 2007
- 1
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Measurement ratio testing for improved quality and outlier detectionRoehr, Jeffrey L. et al. | 2007
- 1
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California scan architecture for high quality and low power testingKyoung Youn Cho, / Mitra, Subhasish / McCluskey, Edward J. et al. | 2007
- 1
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On the saturation of n-detection test sets with increased nPomeranz, Irith / Reddy, Sudhakar M. et al. | 2007
- 1
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A fully digital-compatible BIST strategy for ADC linearity testingHanqing Xing, / Hanjun Jiang, / Degang Chen, / Geiger, Randall et al. | 2007
- 1
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Protocol requirements in an SJTAG/IJTAG environmentCarlsson, Gunnar / Holmqvist, Johan / Larsson, Erik et al. | 2007
- 1
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How much insurance can you afford?Cory, Bruce et al. | 2007
- 1
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Diagnosis for MRAM write disturbance faultChin-Lung Su, / Chih-Wea Tsai, / Cheng-Wen Wu, / Ji-Jan Chen, / Wen-Ching Wu, / Chien-Chung Hung, / Ming-Jer Kao, et al. | 2007
- 1
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Redefining and testing interconnect faults in Mesh NoCsCota, Erika / Kastensmidt, Fernanda Lima / Amory, Alexandre / Cassel, Maico / Lubasweski, Marcelo / Meirelles, Paulo et al. | 2007
- 1
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Analyzing the risk of timing modeling based on path delay tests.Bastani, Pouria / Lee, Benjamin N. / Wang, Li-C. / Sundareswaran, Savithri / Abadir, Magdy S. et al. | 2007
- 1
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On using lossless compression of debug data in embedded logic analysisAnis, Ehab / Nicolici, Nicola et al. | 2007
- 1
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The new ATE: Protocol awareEvans, Andrew C. et al. | 2007
- 1
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Modeling facet roughening errors in self-assembly by snake tile setsMa, X. / Huang, J. / Lombardi, F. et al. | 2007
- 1
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Test yield estimation for analog/RF circuits over multiple correlated measurementsFang Liu, / Acar, Erkan / Ozev, Sule et al. | 2007
- 1
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JTAG system test in a MicroTCA worldVan Treuren, Bradford G. / Ley, Adam et al. | 2007
- 1
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Cost effective manufacturing test using mission mode testsAggarwal, Parmod et al. | 2007
- 1
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GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologiesNicolaidis, Michael et al. | 2007
- 1
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Design-for-reliability: A soft error case studyMing Zhang, et al. | 2007
- 1
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COT flow imposes added requirements for debugAbuhamdeh, Zahi et al. | 2007
- 1
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Welcome message| 2007
- 1
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Test cost reduction for the AMD™ Athlon processor using test partitioningAnuja Sehgal, / Fitzgerald, Jeff / Rearick, Jeff et al. | 2007
- 1
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Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chipMolyneaux, Robert / Ziaja, Tom / Hong Kim, / Shahryar Aryani, / Sungbae Hwang, / Hsieh, Alex et al. | 2007
- 1
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Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applicationsQuach, Minh / Hinton, Mark / Petaja, Regee et al. | 2007
- 1
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An efficient SAT-based path delay fault ATPG with an unified sensitization modelShun-Yen Lu, / Ming-Ting Hsieh, / Jing-Jia Liou, et al. | 2007
- 1
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Testing for systematic defects based on DFM guidelinesDongok Kim, / Amyeen, M. Enamul / Srikanth Venkataraman, / Pomeranz, Irith / Swagato Basumallick, / Landau, Berni et al. | 2007
- 1
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An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test timeYamaguchi, Takahiro J. / Masahiro Ishida, / Hou, Harry X. / Armstrong, Dave / Koji Takayama, / Mani Soma, et al. | 2007
- 1
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Low cost characterization of RF transceivers through IQ data analysisAcar, Erkan / Ozev, Sule et al. | 2007
- 1
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Dependable clock distribution for crosstalk aware designYukiya Miura, et al. | 2007
- 1
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Boundary-scan: Built to last? panel positionNejedlo, Jay et al. | 2007
- 1
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Position statementMadge, Robert et al. | 2007
- 1
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Signature based diagnosis for logic BISTWu-Tung Cheng, / Manish Sharma, / Rinderknecht, Thomas / Liyang Lai, / Hill, Chris et al. | 2007
- 1
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On ATPG for multiple aggressor crosstalk faults in presence of gate delaysGaneshpure, Kunal P. / Kundu, Sandip et al. | 2007
- 1
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Data jitter measurement using a delta-time-to-voltage converter methodKiyotaka Ichiyama, / Masahiro Ishida, / Yamaguchi, Takahiro J. / Mani Soma, et al. | 2007
- 1
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PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan testDevanathan, V.R. / Ravikumar, C.P. / Rajat Mehrotra, / Kamakoti, V. et al. | 2007
- 1
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Implementing bead probe technology for in-circuit test: A case studyFarrell, Mike / Leinbach, Glen et al. | 2007
- 1
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Fundamentals of timing information for test: How simple can we get?Kapur, Rohit / Zejda, Jindrich / Williams, T. W. et al. | 2007
- 1
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A low cost test data compression technique for high n-detection fault coverageSeongmoon Wang, / Wenlong Wei, / Chakradhar, Srimat T. / Zhanglei Wang, et al. | 2007
- 1
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A matched expansion MEMS probe card with low CTE LTCC substrateSeong-Hun Choe, / Shuji Tanaka, / Masayoshi Esashi, et al. | 2007
- 1
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Estimating stuck fault coverage in sequential logic using state traversal and entropy analysisBose, Soumitra / Agrawal, Vishwani D. et al. | 2007
- 1
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Novel compensation scheme for local clocks of high performance microprocessorsMetra, C. / Omana, M. / Mak, TM / Tam, S. et al. | 2007
- 1
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A comparative study of continuous sampling plans for functional board testingAntila, Jukka / Karhu, Timo et al. | 2007
- 1
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Boundary-scan: Built to last? Panel synopsisEklow, Bill et al. | 2007
- 1
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JTAG: Is it still up to snuff?Crouch, Alfred L. et al. | 2007
- 1
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Well-targeted design-for-manufacturability[DFM] through testGattiker, Anne et al. | 2007
- 1
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The essential role of test in DFMWalker, D. M. H. et al. | 2007
- 1
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Is a Protocol Aware test system feasible?Conner, George et al. | 2007
- 1
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A selt-testing BOST for high-frequency PLLs, DLLs, and SerDesSunter, Stephen / Roy, Aubin et al. | 2007
- 1
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Gate delay ratio model for unified path delay analysisYukio Okuda, et al. | 2007
- 1
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A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failuresGuo Yu, / Peng Li, et al. | 2007
- 1
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Faster defect localization in nanometer technology based on defective cell diagnosisManish Sharma, / Wu-Tung Cheng, / Ting-Pu Tai, / Cheng, Y.S. / Will Hsu, / Chen Liu, / Reddy, Sudhakar M. / Mann, Albert et al. | 2007
- 1
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Efficient simulation of parametric faults for multi-stage analog circuitsFang Liu, / Ozev, Sule et al. | 2007
- 1
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Enhanced testing of clock faultsMcLaurin, Teresa L. / Slobodnik, Richard / Kun-Han Tsai, / Keim, Ana et al. | 2007
- 1
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SiP-test: Predicting delivery qualityBiewenga, Alex / de Jong, Frans et al. | 2007
- 1
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A stereo audio Σ∑ ADC architecture with embedded SNDR self-testRolindez, Luis / Carbonero, Jean-Louis / Goguet, Dimitri / Mir, Salvador / Chouba, Nabil et al. | 2007
- 1
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IJTAG: The path to organized instrument connectivityCrouch, Alfred L. et al. | 2007
- 1
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Protocol aware test .. It has a role, but where? And how?Burlison, / Crouch, / Ritchie, et al. | 2007
- 1
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SiP testing strategy for automobile LSIHideyuki Aoki, et al. | 2007
- 1
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Where is car IC testing going?Comen, Steve et al. | 2007
- 1
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A concurrent approach for testing address decoder faults in eFlash memoriesGinez, O. / Girard, P. / Landrault, C. / Pravossoudovitch, S. / Virazel, A. / Daga, J.-M. et al. | 2007
- 1
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A heuristic for thermal-safe SoC test schedulingZhiyuan He, / Zebo Peng, / Petru Eles, et al. | 2007
- 1
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Testing of Vega2, a chip multi-processor with spare processors.Makar, Samy / Altinis, Tony / Patkar, Niteen / Wu, Janet et al. | 2007
- 1
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IEEE P1581 can solve your board level memory cluster test problemsEhrenberg, Heiko et al. | 2007
- 1
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ACCE: Automatic correction of control-flow errorsVemu, Ramtilak / Gurumurthy, Sankar / Abraham, Jacob A. et al. | 2007
- 1
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ERTG: A test generator for error-rate testingShideh Shahidi, / Gupta, Sandeep K. et al. | 2007
- 1
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An algorithm to evaluate wide-band quadrature mixersKoji Asami, et al. | 2007
- 1
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Automotive IC's: less testing, more preventionAppello, Davide et al. | 2007
- 1
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Diagnose compound scan chain and system logic defectsYu Huang, / Will Hsu, / Yuan-Shih Chen, / Wu-Tung Cheng, / Ruifeng Guo, / Man, Albert et al. | 2007
- 1
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The design-for-testability features of a general purpose microprocessorDa Wang, / Xiaoxin Fan, / Xiang Fu, / Hui Liu, / Ke Wen, / Rui Li, / Huawei Li, / Yu Hu, / Xiaowei Li, et al. | 2007
- 1
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Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQKunhyuk Kang, / Muhammad Ashraful Alam, / Kaushik Roy, et al. | 2007
- 1
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Real-time signal processing - a new PLL test approachHideo Okawara, et al. | 2007
- 1
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Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generationUzzaman, Anis / Bibo Li, / Snethen, Tom / Keller, Brion / Grise, Gary et al. | 2007
- 1
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Statistical analysis and optimization of parametric delay testWu, Sean H. / Lee, Benjamin N. / Wang, Li-C. / Abadir, Magdy S. et al. | 2007
- 1
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Backside E-Beam Probing on Nano scale devicesSchalangen, R. / Leihkauf, R. / Kerst, U. / Boit, C. et al. | 2007
- 1
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Verification and debugging of IDDQ test of low power chipsLaisne, M. / Nguyen, T. / Zuo, S. / Pan, X. / Cui, H. / Bai, C. / Street, A. / Parley, M. / Agrawal, N. / Sundararaman, K. et al. | 2007
- 1
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Low cost automatic mixed-signal board test using IEEE 1149.4Sundar, Srividya / Kim, Bruce C. / Byrd, Toby / Toledo, Felipe / Wokhlu, Sudhir / Beskar, Erika / Rousselin, Raul / Cotton, David / Kendall, Gary et al. | 2007
- 1
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Car IC test changing but the same quality goalWittie, Gary et al. | 2007
- 2
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Steering Committee and Subcommittees| 2007
- 4
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ITC 2006 paper awards| 2007
- 5
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Technical Program Committee| 2007
- 10
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ITC technical paper evaluation and selection process| 2007
- 11
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Call for papers| 2007
- 12
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Keynote address| 2007
- 16
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Test Cost Reduction for the AMDTM Athlon Processor using Test Partitioning1Sehgal, A. / Fitzgerald, J. / Rearick, J. / Institute of Electrical and Electronics Engineers et al. | 2007
- 16
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TTTC: test technology technical council| 2007
- 18
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2007 Technical paper reviewers| 2007
- 24
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Author index| 2007
- 89
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New Methods for Receiver Internal Jitter MeasurementsLi, M.P. / Chen, J. / Institute of Electrical and Electronics Engineers et al. | 2007
- 99
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A Self-Testing BOST for High-Frequency PLLs, DLLs, and SerDesSunter, S. / Roy, A. / Institute of Electrical and Electronics Engineers et al. | 2007
- 717
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Delay Fault Simulation with Bounded Gate Delay ModelBose, S. / Grimes, H. / Agrawal, V.D. / Institute of Electrical and Electronics Engineers et al. | 2007
- 812
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On the Saturation of n-Detection Test Sets with Increased etaPomeranz, I. / Reddy, S.M. / Institute of Electrical and Electronics Engineers et al. | 2007
- 865
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A Stereo Audio S. ADC Architecture with Embedded SNDR Self-TestRolindez, L. / Mir, S. / Carbonero, J.-L. / Goguet, D. / Chouba, N. / Institute of Electrical and Electronics Engineers et al. | 2007
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Cover 1| 2007
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Copyright| 2007
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Table of contents| 2007