Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources (Englisch)
- Neue Suche nach: Gan, K.-J.
- Neue Suche nach: Liang, D.-S.
- Neue Suche nach: Chen, Y.-W.
- Neue Suche nach: Institute of Electrical and Electronics Engineers
- Neue Suche nach: Gan, K.-J.
- Neue Suche nach: Liang, D.-S.
- Neue Suche nach: Chen, Y.-W.
- Neue Suche nach: Kameyama, M.
- Neue Suche nach: Institute of Electrical and Electronics Engineers
In:
IEEE international symposium on multiple-valued logic
8
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2068-2072
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2010
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ISSN:
- Aufsatz (Konferenz) / Print
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Titel:Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
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Beteiligte:Gan, K.-J. ( Autor:in ) / Liang, D.-S. ( Autor:in ) / Chen, Y.-W. ( Autor:in ) / Kameyama, M. / Institute of Electrical and Electronics Engineers
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Kongress:39th, IEEE international symposium on multiple-valued logic ; 2009 ; Okinawa, Japan
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Erschienen in:IEEE international symposium on multiple-valued logic , 8 ; 2068-2072IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E SERIES D ; 93, 8 ; 2068-2072
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Verlag:
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Erscheinungsdatum:01.01.2010
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Format / Umfang:5 pages
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
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