International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (Englisch)
- Neue Suche nach: International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems
- Weitere Informationen zu International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems:
- http://d-nb.info/gnd/10070155-3
- Neue Suche nach: Veidenbaum, Alexander V.
- Neue Suche nach: International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems
- Weitere Informationen zu International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems:
- http://d-nb.info/gnd/10070155-3
2002
- Konferenzband / Elektronische Ressource
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Titel:International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems
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Beteiligte:
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Verlag:
- Neue Suche nach: IEEE Computer Soc.
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Erscheinungsort:Los Alamitos, Calif.
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Erscheinungsdatum:2002
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Anmerkungen:"This edited volume contains a collection of papers that originated from presentations at the 2002 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'02) which was held on the Big Island of Hawai'i in January of 2002. -- Preface
"IEEE Computer Society Order Number PR01635"--Title page verso
Cover title
Includes bibliographical references and index -
ISBN:
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Medientyp:Konferenzband
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Format:Elektronische Ressource
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 3
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Power and performance fitting in nanometer designSato, T. / Koushiro, T. / Chiyonobu, A. / Arita, I. et al. | 2002
- 11
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Reducing power with an L0 instruction cache using history-based predictionWeiyu Tang, / Veidenbaum, A.V. / Nicolau, A. et al. | 2002
- 21
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Tight non-linear loop timing estimationvan Engelen, R.A. / Gallivan, K.A. et al. | 2002
- 27
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Exploring advanced architectures using performance predictionKerbyson, D.J. / Wasserman, H.J. / Hoisie, A. et al. | 2002
- 41
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Trading bandwidth for latency: managing continuations through a carpet bag cacheMurphy, R.C. / Kogge, P.M. et al. | 2002
- 50
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Architecture and compiler co-optimization for high performance computingNakamura, H. / Kondo, M. / Ohneda, T. / Fujita, M. / Chiba, S. / Sato, M. / Boku, T. et al. | 2002
- 57
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Multigrain parallel processing for JPEG encoding on a single chip multiprocessorKodaka, T. / Kimura, K. / Kasahara, H. et al. | 2002
- 67
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Branch classification to control instruction fetch in simultaneous multithreaded architecturesKnijnenburg, P.M.W. / Ramirez, A. / Latorre, F. / Larriba, J. / Valero, M. et al. | 2002
- 77
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Preliminary evaluation of a binary translation system for multithreaded processorsOotsu, K. / Yokota, T. / Ono, T. / Baba, T. et al. | 2002
- 87
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A low latency high bandwidth network interface prototype for PC clusterTanabe, N. / Hamada, Y. / Nakajo, H. / Imashiro, H. / Yamamoto, J. / Kudoh, T. / Amano, H. et al. | 2002
- 95
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Design and implementation of interrupt packaging mechanismNakashima, K. / Kusakabe, S. / Taniguchi, H. / Amamiya, M. et al. | 2002
- 103
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A networking oriented data-driven processor: CUENishikawa, H. / Kurebayashi, R. et al. | 2002
- 113
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Author index| 2002
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International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems| 2002