HPCA : the seventh International Symposium on High-Performance Computer Architecture : proceedings, 19-24 January 2001, Monterrey, Nuevo Leon, México (Englisch)
- Neue Suche nach: International Symposium on High-Performance Computer Architecture
- Neue Suche nach: IEEE Computer Society
- Neue Suche nach: International Symposium on High-Performance Computer Architecture
- Neue Suche nach: IEEE Computer Society
2010
-
ISBN:
- Konferenzband / Elektronische Ressource
-
Titel:HPCA : the seventh International Symposium on High-Performance Computer Architecture : proceedings, 19-24 January 2001, Monterrey, Nuevo Leon, México
-
Weitere Titelangaben:High-performance computer architecture
High-Performance Computer Architecture, 2001, HPCA, The Seventh International Symposium on -
Beteiligte:
-
Kongress:International Symposium on High-Performance Computer Architecture ; 7th
-
Verlag:
- Neue Suche nach: IEEE Computer Society
-
Erscheinungsort:Los Alamitos, Calif
-
Erscheinungsdatum:2010
-
Format / Umfang:1 Online-Ressource (xv, 318 pages)
-
Anmerkungen:illustrations
"IEEE Computer Society order number PR01019"--Title page verso
"ISSN 1530-0897"--Title page verso
Includes bibliographical references and index
Use copy Restrictions unspecified star MiAaHDL -
ISBN:
-
Medientyp:Konferenzband
-
Format:Elektronische Ressource
-
Sprache:Englisch
- Neue Suche nach: 004.2/2
- Weitere Informationen zu Dewey Decimal Classification
-
Schlagwörter:
-
Klassifikation:
DDC: 004.2/2 -
Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 5
-
Stack value file: custom microarchitecture for the stackLee, H.H.-S. / Smelyanskiy, M. / Newburn, C.J. / Tyson, G.S. et al. | 2001
- 15
-
Register renaming and scheduling for dynamic execution of predicated codeWang, P.H. / Hong Wang, / Kling, R.M. / Ramakrishnan, K. / Shen, J.P. et al. | 2001
- 27
-
Data-flow prescheduling for large instruction windows in out-of-order processorsMichaud, P. / Seznec, A. et al. | 2001
- 37
-
Speculative data-driven multithreadingRoth, A. / Sohi, G.S. et al. | 2001
- 51
-
Towards virtually-addressed memory hierarchiesXiaogang Qiu, / Dubois, M. et al. | 2001
- 63
-
Reevaluating online superpage promotion with hardware supportZhen Fang, / Lixin Zhang, / Carter, J.B. / Hsieh, W.C. / McKee, S.A. et al. | 2001
- 73
-
Performance of hardware compressed main memoryAbali, B. / Franke, H. / Xiaowei Shen, / Poff, D.E. / Smith, T.B. et al. | 2001
- 85
-
JETTY: filtering snoops for reduced energy consumption in SMP serversMoshovos, A. / Memik, G. / Falsafi, B. / Choudhary, A. et al. | 2001
- 97
-
A new scalable directory architecture for large-scale multiprocessorsAcacio, M.E. / Gonzalez, J. / Garcia, J.M. / Duato, J. et al. | 2001
- 107
-
Self-tuned congestion control for multiprocessor networksThottethodi, M. / Lebeck, A.R. / Mukherjee, S.S. et al. | 2001
- 121
-
Automatically mapping code on an intelligent memory architectureJaejin Lee, / Solihin, Y. / Torrettas, J. et al. | 2001
- 133
-
CARS: a new code generation framework for clustered ILP processorsKailas, K. / Ebcioglu, K. / Agrawala, A. et al. | 2001
- 147
-
An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-cachesYang, S. / Powell, M.D. / Falsafi, B. / Roy, K. / Vijaykumar, T.N. et al. | 2001
- 159
-
DRAM energy management using software and hardware directed power mode controlDelaluz, V. / Kandemir, M. / Vijaykrishnan, N. / Sivasubramaniam, A. / Irwin, M.J. et al. | 2001
- 171
-
Dynamic thermal management for high-performance microprocessorsBrooks, D. / Martonosi, M. et al. | 2001
- 185
-
Dynamic prediction of critical path instructionsTune, E. / Dongning Liang, / Tullsen, D.M. / Calder, B. et al. | 2001
- 197
-
Dynamic branch prediction with perceptronsJimenez, D.A. / Lin, C. et al. | 2001
- 207
-
Differential FCM: increasing value prediction accuracy by improving table usage efficiencyGoeman, B. / Vandierendonck, H. / de Bosschere, K. et al. | 2001
- 219
-
DLP+TLP processors for the next generation of media workloadsCorbal, J. / Espasa, R. / Valero, M. et al. | 2001
- 229
-
An architectural evaluation of Java TPC-WCain, H.W. / Rajwar, R. / Marden, M. / Lipasti, M.H. et al. | 2001
- 241
-
A programmable co-processor for profilingZilles, C.B. / Sohi, G.S. et al. | 2001
- 255
-
A delay model and speculative architecture for pipelined routersPeh, L.-S. / Dally, W.J. et al. | 2001
- 267
-
Quantifying the impact of architectural scaling on communicationHeath, T. / Kaur, S. / Martin, R.P. / Nguyen, T.D. et al. | 2001
- 281
-
Call graph prefetching for database applicationsAnnavaram, M. / Patel, J.M. / Davidson, E.S. et al. | 2001
- 291
-
Branch history guided instruction prefetchingSrinivasan, V. / Davidson, E.S. / Tyson, G.S. / Charney, M.J. / Puzak, T.R. et al. | 2001
- 301
-
Reducing DRAM latencies with an integrated memory hierarchy designWei-Fen Lin, / Reinhardt, S.K. / Burger, D. et al. | 2001
- 317
-
Author index| 2001
- iii
-
Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture| 2001