1990 proceedings : International Conference on Wafer Scale Integration, January 23-25, 1990, San Francisco, California, USA (Englisch)
- Neue Suche nach: International Conference on Wafer Scale Integration
- Neue Suche nach: IEEE Computer Society
- Neue Suche nach: IEEE Components, Hybrids, and Manufacturing Technology Society
- Neue Suche nach: Brewer, Joe E.
- Neue Suche nach: Little, Michael J.
- Neue Suche nach: International Conference on Wafer Scale Integration
- Neue Suche nach: IEEE Computer Society
- Neue Suche nach: IEEE Components, Hybrids, and Manufacturing Technology Society
2011
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ISBN:
- Konferenzband / Elektronische Ressource
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Titel:1990 proceedings : International Conference on Wafer Scale Integration, January 23-25, 1990, San Francisco, California, USA
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Weitere Titelangaben:Wafer Scale Integration, 1990, proceedings, (2nd) International Conference on
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Beteiligte:
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Kongress:International Conference on Wafer Scale Integration ; 2nd
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Verlag:
- Neue Suche nach: IEEE Computer Society Press
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Erscheinungsort:Los Alamitos, Calif
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Erscheinungsdatum:2011
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Format / Umfang:1 Online-Ressource (xiv, 342 pages)
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Anmerkungen:illustrations
Includes bibliographical references and index
Use copy Restrictions unspecified star MiAaHDL -
ISBN:
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Medientyp:Konferenzband
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Format:Elektronische Ressource
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Sprache:Englisch
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Schlagwörter:
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Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2)| 1990
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200-Mb wafer scale memoryBaba, F. / Sinclair, A. et al. | 1990
- 13
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Progress in WSI SRAM developmentBourassa, R. / Coffman, T. / Brewer, J.E. et al. | 1990
- 20
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The Lincoln programmable image-processing waferBerger, R. / Bertapelli, A. / Frankel, R. / Hunt, J.J. / Mann, J. / Raffel, J.I. / Rhodes, F.M. / Soares, A. / Woodward, C. et al. | 1990
- 27
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MUSE: a wafer-scale systolic DSPAllen, D.L. / Anderson, A.H. / Rader, C.M. / Woodward, C. et al. | 1990
- 36
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WASP: a wafer-scale massively parallel processorLea, R.M. et al. | 1990
- 43
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The WASP demonstrator programme: the engineering of a wafer-scale systemJalowiecki, I.P. / Hedge, S.J. et al. | 1990
- 50
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Re-wafer scale integration: a new approach to active phased arraysWhicker, L.R. / Zingaro, J.J. / Driver, M.C. / Clarke, R.C. et al. | 1990
- 57
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A 64 Mb MROM with good pair selection architectureNakahara, K. / Hatanaka, H. / Kura, S. / Suminaga, Y. / Hotta, Y. / Okada, M. / Miyata, K. et al. | 1990
- 60
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A high performance single chip FFT array processor for wafer scale integrationJaehee You / Wong, S.S. et al. | 1990
- 68
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Implementation of configurable hardware using wafer scale integrationKean, T. / Gray, J. / Pruniaux, B. et al. | 1990
- 75
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Crosspoint Arithmetic Processor architecture for wafer scale integrationArcos, J.T. / Evans, B. / Kung, S.Y. et al. | 1990
- 85
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A linear-array WSI architecture for improved yield and performanceHorst, R.W. et al. | 1990
- 92
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Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integrationNunally, P. et al. | 1990
- 102
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WSI architecture for L-U decomposition: a radar array processorJain, V.K. / Landis, D.L. et al. | 1990
- 109
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Defect tolerance scheme for gigaFLOP WSI architecturesSingh, A.D. / Hee yong Youn et al. | 1990
- 116
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A general configurable architecture for WSI implementation for neural netsDistante, F. / Sami, M.G. / Storti Gajani, G. et al. | 1990
- 124
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WSI architecture of a neurocomputer moduleRamacher, U. / Wesseling, M. / Goser, K. et al. | 1990
- 131
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Defect tolerant sorting networks for WSI implementationSheng-Chiech Liang / Sy-Yen Kuo et al. | 1990
- 138
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Data manipulator network for WSI designsWills, J.M. / Jain, V.K. et al. | 1990
- 145
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Multiple fault detection and location in WSI baseline interconnection networksFeng, C. / Huang, W.K. / Lombardi, F. et al. | 1990
- 152
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Effects of switch failure on soft-configurable WSI yieldBlatt, M. et al. | 1990
- 160
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Defect tolerant implementations of feed-forward and recurrent neural networksFranzon, P. / Bout, D. van den / Paulos, J. / Miller, T. III / Snyder, W. / Nagle, T. / Wentai Liu et al. | 1990
- 167
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A visually oriented architectural fault simulation environment for WSIRyan, P.G. / Saab, D.G. / Kent Fuchs, W. et al. | 1990
- 174
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Hierarchical fault tolerance for 3D microelectronicsCampbell, M. / Little, M. / Yung, M. et al. | 1990
- 189
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Distributed diagnosis for wafer scale systemsYoon-Hwa Choi et al. | 1990
- 196
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Fault tolerance performance of WSI systolic sorterHoriguchi, S. et al. | 1990
- 203
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Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic unitsPiuri, V. et al. | 1990
- 213
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A defect and fault tolerant design of WSI static RAM modulesTsuda, N. et al. | 1990
- 220
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A methodology for wafer scale integration of linear pipelined arraysRamaswamy, R. / Brebner, G. / Aspinall, D. et al. | 1990
- 229
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Some new algorithms for reconfiguring VLSI/WSI arraysVarvarigou, T. / Roychowdhury, V.P. / Kailath, T. et al. | 1990
- 236
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Soft-programmable bypass switch design for defect-tolerant arraysWalker, D.M.H. et al. | 1990
- 243
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Yield enhancement for WSI array processors using two-and-half-track switchesJean, J.S.N. / Fu, H.C. / Kung, S.Y. et al. | 1990
- 251
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Testing wafer scale arrays: constant testability under multiple faultsSciuto, D. / Lombardi, F. et al. | 1990
- 258
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A self-test methodology for restructurable WSILandis, D.L. et al. | 1990
- 265
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Divide-and-conquer in wafer scale array testingChoi, Y.H. / Jung, T. et al. | 1990
- 273
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Yield modeling and optimization of large redundant RAMsGanapathy, K.N. / Singh, A.D. / Pradhan, D.K. et al. | 1990
- 288
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Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuitsJagau, U. / Dyck, K.P. / Grabinski, H. / Iden, H.J. / Kuboschek, M. et al. | 1990
- 298
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Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizationsHartmann, H.D. / Hillmann-Ruge, T. et al. | 1990
- 308
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Hybrid wafer scale interconnection inventing a new technologySchmidt, R. et al. | 1990
- 317
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WSI implemented with button board interconnectionArcos, J.T. / Kamiyama, W.T. / Swartzlander, E.E. / Young, W.E. et al. | 1990
- 322
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A study of high density multilayer LSIMatsunami, M. / Koba, M. / Miyake, R. et al. | 1990
- 329
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Wafer scale integration (WSI) of programmable gate arrays (PGA's)McDonald, J.F. / Dabral, S. / Philhower, R. / Russinovich, M.E. et al. | 1990