Proceedings, 32nd International Symposium on Computer Architecture : Madison, Wisconsin, June 4-8, 2005 (Englisch)
- Neue Suche nach: International Symposium on Computer Architecture
- Neue Suche nach: IEEE Computer Society
- Neue Suche nach: Sigarch
- Neue Suche nach: International Symposium on Computer Architecture
- Neue Suche nach: IEEE Computer Society
- Neue Suche nach: Sigarch
2005
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ISBN:
- Konferenzband / Elektronische Ressource
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Titel:Proceedings, 32nd International Symposium on Computer Architecture : Madison, Wisconsin, June 4-8, 2005
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Weitere Titelangaben:32nd International Symposium on Computer Architecture
ISCA 2005
Proceedings of the 32nd Annual International Symposium on Computer Architecture
Computer Architecture, 2005, ISCA '05, proceedings, 32nd International Symposium on
ISCA '05 -
Beteiligte:
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Kongress:International Symposium on Computer Architecture ; 32nd
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Erschienen in:Computer architecture news ; v. 33, no. 2 (May 2005)
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Verlag:
- Neue Suche nach: IEEE Computer Society
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Erscheinungsort:Los Alamitos, Calif
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Erscheinungsdatum:2005
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Format / Umfang:1 Online-Ressource (xviii, 557 pages)
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Anmerkungen:illustrations
"IEEE Computer Society Order Number P2270 ; ACM Order Number 415054"--Title page verso
Includes bibliographical references and author index -
ISBN:
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Medientyp:Konferenzband
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Format:Elektronische Ressource
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Architecture for protecting critical secrets in microprocessorsLee, R.B. / Kwan, P.C.S. / McGregor, J.P. / Dwoskin, J. / Zhenghong Wang, et al. | 2005
- 14
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High efficiency counter mode security architecture via prediction and precomputationWeidong Shi, / Lee, H.S. / Ghosh, M. / Chenghuai Lu, / Boldyreva, A. et al. | 2005
- 25
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Design and Implementation of the AEGIS Single-Chip Processor Using Physical Random FunctionsSuh, G. / O Donnell, C. / Sachdev, I. / Devadas, S. / IEEE Computer Society et al. | 2005
- 25
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Design and implementation of the AEGIS single-chip secure processor using physical random functionsSuh, G.E. / O'Donnell, C.W. / Ishan Sachdev, / Srinivas Devadas, et al. | 2005
- 38
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Disk drive roadmap from the thermal perspective: a case for dynamic thermal managementGurumurthi, S. / Sivasubramaniam, A. / Natarajan, V.K. et al. | 2005
- 50
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Direct cache access for high bandwidth network I/OHuggahalli, R. / Iyer, R. / Tetrick, S. et al. | 2005
- 60
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Deconstructing commodity storage clustersGunawi, H.S. / Agrawal, N. / Arpaci-Dusseau, A.C. / Schindler, J. / Arpaci-Dusseau, R.H. et al. | 2005
- 74
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A robust main-memory compression schemeEkman, M. / Stenstrom, P. et al. | 2005
- 86
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Continuous optimizationFahs, B. / Rafacz, T. / Patel, S.J. / Lumetta, S.S. et al. | 2005
- 98
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RENO: a rename-based instruction optimizerPetric, V. / Sha, T. / Roth, A. et al. | 2005
- 112
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A high throughput string matching architecture for intrusion detection and preventionLin Tan, / Sherwood, T. et al. | 2005
- 123
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A tree based router search engine architecture with single port memoriesBaboescu, F. / Tullsen, D.M. / Rosu, G. / Singh, S. et al. | 2005
- 134
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An integrated memory array processor architecture for embedded image recognition systemsKyo, S. / Okazaki, S. / Arai, T. et al. | 2005
- 148
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Design and evaluation of hybrid fault-detection systemsReis, G.A. / Chang, J. / Vachharajani, N. / Mukherjee, S.S. / Rangan, R. / August, D.I. et al. | 2005
- 160
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Rescue: a microarchitecture for testability and defect toleranceSchuchman, E. / Vijaykumar, T.N. et al. | 2005
- 172
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Opportunistic transient-fault detectionGomaa, M.A. / Vijaykumar, T.N. et al. | 2005
- 186
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An evaluation framework and instruction set architecture for ion-trap based quantum micro-architecturesBalensiefer, S. / Kregor-Stickles, L. / Oskin, M. et al. | 2005
- 197
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Energy optimization of subthreshold-voltage sensor network processorsNazhandali, L. / Zhai, B. / Olson, A. / Reeves, A. / Minuth, M. / Helfand, R. / Sanjay Pant, / Austin, T. / Blaauw, D. et al. | 2005
- 208
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An ultra low power system architecture for sensor network applicationsHempstead, M. / Tripathi, N. / Mauro, P. / Gu-Yeon Wei, / Brooks, D. et al. | 2005
- 222
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Temporal streaming of shared memoryWenisch, T.F. / Somogyi, S. / Hardavellas, N. / Jangwoo Kim, / Ailamaki, A. / Babak Falsafi, et al. | 2005
- 234
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RegionScout: exploiting coarse grain sharing in snoop-based coherenceMoshovos, A. et al. | 2005
- 246
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Improving multiprocessor performance with coarse-grain coherence trackingCantin, J.F. / Lipasti, M.H. / Smith, J.E. et al. | 2005
- 260
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Improving program efficiency by packing instructions into registersHines, S. / Green, J. / Tyson, G. / Whalley, D. et al. | 2005
- 272
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An architecture framework for transparent instruction set customization in embedded processorsClark, N. / Blome, J. / Chu, M. / Mahlke, S. / Biles, S. / Flautner, K. et al. | 2005
- 284
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BugNet: continuously recording program execution for deterministic replay debuggingNarayanasamy, S. / Pokam, G. / Calder, B. et al. | 2005
- 298
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Mitigating Amdahl's law through EPI throttlingAnnavaram, M. / Grochowski, E. / Shen, J. et al. | 2005
- 310
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Increased scalability and power efficiency by using multiple speed pipelinesTalpes, E. / Marculescu, D. et al. | 2005
- 322
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Energy-effectiveness of pre-execution and energy-aware p-thread selectionPetric, V. / Roth, A. et al. | 2005
- 336
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Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessorsZhang, M. / Asanovic, K. et al. | 2005
- 346
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Adaptive mechanisms and policies for managing cache hierarchies in chip multiprocessorsSpeight, E. / Shafi, H. / Lixin Zhang, / Rajamony, R. et al. | 2005
- 357
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Optimizing replication, communication, and capacity allocation in CMPsChishti, Z. / Powell, M.D. / Vijaykumar, T.N. et al. | 2005
- 370
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Techniques for efficient processing in runahead execution enginesOnur Mutlu, / Hyesoon Kim, / Patt, Y.N. et al. | 2005
- 382
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Piecewise linear branch predictionJimenez, D.A. et al. | 2005
- 394
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Analysis of the O-GEometric history length branch predictorSeznec, A. et al. | 2005
- 408
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Interconnections in multi-core architectures: understanding mechanisms, overheads and scalingKumar, R. / Zyuban, V. / Tullsen, D.M. et al. | 2005
- 420
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Microarchitecture of a high radix routerKim, J. / Dally, W.J. / Towles, B. / Gupta, A.K. et al. | 2005
- 432
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Near-optimal worst-case throughput routing for two-dimensional mesh networksDaeho Seo, / Akif Ali, / Won-Taek Lim, / Rafique, N. et al. | 2005
- 446
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Scalable load and store processing in latency tolerant processorsGandhi, A. / Akkary, H. / Rajwar, R. / Srinivasasn, S.T. / Lai, K. et al. | 2005
- 458
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Store vulnerability window (SVW): re-execution filtering for enhanced load optimizationRoth, A. et al. | 2005
- 469
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Store buffer design in first-level multibanked data cachesTorres, E.F. / Ibanez, P. / Vinals, V. / Llaberia, J.M. et al. | 2005
- 482
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Dynamic verification of sequential consistencyMeixner, A. / Sorin, D.J. et al. | 2005
- 494
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Virtualizing transactional memoryRajwar, R. / Herlihy, M. / Lai, K. et al. | 2005
- 506
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The impact of performance asymmetry in emerging multicore architecturesBalakrishnan, S. / Ravi Rajwar, / Upton, M. / Lai, K. et al. | 2005
- 520
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Exploiting structural duplication for lifetime reliability enhancementSrinivasan, J. / Adve, S.V. / Pradip Bose, / Rivers, J.A. et al. | 2005
- 532
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Computing architectural vulnerability factors for address-based structuresBiswas, A. / Racunas, P. / Cheveresan, R. / Emer, J. / Mukherjee, S.S. / Rangan, R. et al. | 2005
- 544
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The V-Way cache: demand-based associativity via global replacementQureshi, M.K. / Thompson, D. / Patt, Y.N. et al. | 2005
- 556
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Author index| 2005
- i
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32nd International Symposium on Computer Architecture - Title Page| 2005
- iv
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32nd International Symposium on Computer Architecture - Copyright Page| 2005
- ix
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General Chair’s Message| 2005
- v
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32nd International Symposium on Computer Architecture - Table of Contents| 2005
- x
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Program Chair’s Message| 2005
- xvi
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Committees| 2005
- xvii
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list-reviewer| 2005
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Proceedings. 32nd International Symposium on Computer Architecture| 2005