Hierarchical propagation of geometric constraints for full-custom physical design of ICs (Englisch)
- Neue Suche nach: Mittag, Maximilian
- Neue Suche nach: Krinke, Andreas
- Neue Suche nach: Jerke, Goran
- Neue Suche nach: Rosenstiel, Wolfgang
- Neue Suche nach: Mittag, Maximilian
- Neue Suche nach: Krinke, Andreas
- Neue Suche nach: Jerke, Goran
- Neue Suche nach: Rosenstiel, Wolfgang
In:
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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1471-1474
;
2012
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ISSN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Hierarchical propagation of geometric constraints for full-custom physical design of ICs
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Beteiligte:Mittag, Maximilian ( Autor:in ) / Krinke, Andreas ( Autor:in ) / Jerke, Goran ( Autor:in ) / Rosenstiel, Wolfgang ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.03.2012
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Format / Umfang:2791955 byte
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Table of contents| 2011
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Evaluating energy consumption of homogeneous MPSoCs using spare tilesAmory, A M / Ost, L C / Marcon, César A M / Moraes, F G / Lubaszewski, M S et al. | 2011
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Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architecturesTino, A / Khan, G N et al. | 2011
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Optical Ring Network-on-Chip (ORNoC): Architecture and design methodologyLe Beux, S / Trajkovic, J / O'Connor, I / Nicolescu, G / Bois, G / Paulin, P et al. | 2011
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State of the art verification methodologies in 2015Crone, A / Bringmann, O / Chevallaz, C / Dickman, B / Esen, V / Rohleder, M et al. | 2011
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Design automation for IEEE P1687Zadegan, F G / Ingelsson, U / Carlsson, G / Larsson, E et al. | 2011
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Call for papers| 2011
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DATE Executive Committee| 2011
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Design space exploration for 3D-stacked DRAMsWeis, C / Wehn, N / Igor, L / Benini, L et al. | 2011
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VESPA: Variability emulation for System-on-Chip performance analysisKozhikkottu, V J / Venkatesan, R / Raghunathan, A / Dey, S et al. | 2011
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[Title page]Lukasiewycz, M / Chakraborty, S / Milbredt, P et al. | 2011
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A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systemsCheng-Yang Fu, / Meng-Huan Wu, / Ren-Song Tsay, et al. | 2011
- 1
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A novel tag access scheme for low power L2 cacheHyunsun Park, / Sungjoo Yoo, / Sunggu Lee, et al. | 2011
- 1
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Robustness analysis of 6T SRAMs in memory retention mode under PVT variationsVatajelu, E I / Figueras, J et al. | 2011
- 1
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Energy analysis methods and tools for modelling and Optimizing monitoring tyre systemsBonanno, A / Bocea, A / Sabatini, M et al. | 2011
- 1
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Understanding the role of buildings in a smart microgridAgarwal, Y / Weng, T / Gupta, R K et al. | 2011
- 1
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Arithmetic logic units with high error detection rates to counteract fault attacksMedwed, M / Mangard, S et al. | 2011
- 1
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Architectural exploration of 3D FPGAs towards a better balance between area and delayChia-I Chen, / Bau-Cheng Lee, / Juinn-Dar Huang, et al. | 2011
- 1
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Multi-level attacks: An emerging security concern for cryptographic hardwareAli, S S / Chakraborty, R S / Mukhopadhyay, D / Bhunia, S et al. | 2011
- 1
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An approach for dynamic selection of synthesis transformations based on Markov Decision ProcessesWelp, T / Kuehlmann, A et al. | 2011
- 1
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Resynchronization of Cyclo-Static Dataflow graphsHausmans, J P H M / Bekooij, M J G / Corporaal, H et al. | 2011
- 1
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Timing error statistics for energy-efficient robust DSP systemsAbdallah, R A / Yu-Hung Lee, / Shanbhag, N R et al. | 2011
- 1
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Automated debugging of SystemVerilog assertionsKeng, B / Safarpour, S / Veneris, A et al. | 2011
- 1
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Achieving composability in NoC-based MPSoCs through QoS management at software levelCarara, E / Almeida, G M / Sassatelli, G / Moraes, F G et al. | 2011
- 1
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Run-time deadlock detection in networks-on-chip using coupled transitive closure networksAl-Dujaily, R / Mak, T / Fei Xia, / Yakovlev, A / Palesi, M et al. | 2011
- 1
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Controlled timing-error acceptance for low energy IDCT designKu He, / Gerstlauer, A / Orshansky, M et al. | 2011
- 1
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Transition-Time-Relation based capture-safety checking for at-speed scan test generationMiyase, K / Wen, X / Aso, M / Furukawa, H / Yamato, Y / Kajihara, S et al. | 2011
- 1
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Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial exampleHashempour, H / Dohmen, J / Tasić, Bratislav / Kruseman, B / Hora, C / van Beurden, M / Yizi Xing, et al. | 2011
- 1
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Sponsors| 2011
- 1
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Analytical heat transfer model for thermal through-silicon viasHu Xu, / Pavlidis, V F / De Micheli, G et al. | 2011
- 1
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Correlating inline data with final test outcomes in analog/RF devicesKupp, N / Slamani, M / Makris, Y et al. | 2011
- 1
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Efficient validation input generation in RTL by hybridized source code analysisLingyi Liu, / Vasudevan, S et al. | 2011
- 1
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Ensuring correctness of analog circuits in presence of noise and process variations using pattern matchingNarayanan, R / Zaki, M H / Tahar, Sofiène et al. | 2011
- 1
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Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysisMerrett, M / Asenov, P / Yangang Wang, / Zwolinski, M / Reid, D / Millar, C / Roy, S / Zhenyu Liu, / Furber, S / Asenov, A et al. | 2011
- 1
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A workflow for runtime adaptive task allocation on heterogeneous MPSoCsJia Huang, / Raabe, A / Buckl, C / Knoll, A et al. | 2011
- 1
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Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodesWeddell, A S / Merrett, G V / Al-Hashimi, B M et al. | 2011
- 1
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jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-ChipFunchal, G / Moy, M et al. | 2011
- 1
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Coordinate strip-mining and kernel fusion to lower power consumption on GPUGuibin Wang, et al. | 2011
- 1
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SoC infrastructures for predictable system integrationvan der Wolf, P / Geuzebroek, J et al. | 2011
- 1
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Trigonometric method to handle realistic error probabilities in logic circuitsChien-Chih Yu, / Hayes, J P et al. | 2011
- 1
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Host-compiled multicore RTOS simulator for embedded real-time software developmentRazaghi, P / Gerstlauer, A et al. | 2011
- 1
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Embedded software debug and test: Needs and requirements for innovations in debuggingWinterholer, M et al. | 2011
- 1
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Power-driven global routing for multi-supply voltage domainsTai-Hsuan Wu, / Davoodi, A / Linderoth, J T et al. | 2011
- 1
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Redressing timing issues for speed-independent circuits in deep submicron ageYu Li, / Mak, T / Yakovlev, A et al. | 2011
- 1
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Error correcting code analysis for cache memory high reliability and performanceRossi, D / Timoncini, N / Spica, M / Metra, C et al. | 2011
- 1
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Thermal-aware on-line task allocation for 3D multi-core processor throughput optimizationChiao-Ling Lung, / Yi-Lun Ho, / Ding-Ming Kwai, / Shih-Chieh Chang, et al. | 2011
- 1
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2D and 3D integration with organic and silicon electronicsLandrock, C K / Omrane, B / Yindar Chuo, / Kaminska, B / Aristizabal, J et al. | 2011
- 1
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Fast statistical analysis of RC nets subject to manufacturing variabilitiesYu Bi, / van der Kolk, Kees-Jan / Villena, Jorge Fernández / Silveira, Luís Miguel / van der Meijs, Nick et al. | 2011
- 1
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Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulationAlorda, B / Torrens, G / Bota, S / Segura, J et al. | 2011
- 1
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Systematic design of a programmable low-noise CMOS neural interface for cell activity recordingLópez, C M / Musa, S / Bartic, C / Puers, R / Gielen, G / Eberle, W et al. | 2011
- 1
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Challenges in designing high speed memory subsystem for mobile applicationsYip, T G / Yeung, P / Ming Li, / Dressler, D et al. | 2011
- 1
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Time redundant parity for low-cost transient error detectionPalframan, D J / Nam Sung Kim, / Lipasti, M H et al. | 2011
- 1
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Logic synthesis and physical design: Quo vadis?De Micheli, G et al. | 2011
- 1
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A global postsynthesis optimization method for combinational circuitsVasicek, Z / Sekanina, L et al. | 2011
- 1
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Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidanceJin-Tai Yan, / Zhi-Wei Chen, et al. | 2011
- 1
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Guaranteed service virtual channel allocation in NoCs for run-time task schedulingWinter, M / Fettweis, G P et al. | 2011
- 1
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Flow-based partitioning and position constraints in VLSI placementStruzyna, M et al. | 2011
- 1
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A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicoresBartolini, A / Cacciari, M / Tilli, A / Benini, L et al. | 2011
- 1
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A new distributed event-driven gate-level HDL simulation by accurate predictionDusung Kim, / Ciesielski, M / Seiyang Yang, et al. | 2011
- 1
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A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clustersRahimi, A / Loi, I / Kakoee, M R / Benini, L et al. | 2011
- 1
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A real-time compressed sensing-based personal electrocardiogram monitoring systemKanoun, K / Mamaghanian, H / Khaled, N / Atienza, D et al. | 2011
- 1
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A high-performance parallel implementation of the Chambolle algorithmAkin, A / Beretta, I / Nacci, A A / Rana, V / Santambrogio, M D / Atienza, D et al. | 2011
- 1
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Speeding-up SIMD instructions dynamic binary translation in embedded processor simulationMichel, L / Fournel, N / Pétrot, Frédéric et al. | 2011
- 1
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Priority division: A high-speed shared-memory bus arbitration with bounded latencyShah, H / Raabe, A / Knoll, A et al. | 2011
- 1
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A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design featuresFerent, C / Doboli, A et al. | 2011
- 1
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Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memoryJingtong Hu, / Xue, C J / Qingfeng Zhuge, / Wei-Che Tseng, / Sha, E H.-M et al. | 2011
- 1
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Stochastic circuit reliability analysisMaricau, E / Gielen, G et al. | 2011
- 1
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SHARC: A streaming model for FPGA accelerators and its application to SaliencyKestur, S / Dantara, D / Narayanan, V et al. | 2011
- 1
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SAT-based fault coverage evaluation in the presence of unknown valuesKochte, M A / Wunderlich, H-J et al. | 2011
- 1
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An energy-efficient 3D CMP design with fine-grained voltage scalingJishen Zhao, / Xiangyu Dong, / Yuan Xie, et al. | 2011
- 1
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A low-power VLIW processor for 3GPP-LTE complex numbers processingBernard, C / Clermidy, F et al. | 2011
- 1
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Interpolation sequences revisitedCabodi, G / Nocco, S / Quer, S et al. | 2011
- 1
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An all-digital built-in self-test technique for transfer function characterization of RF PLLsPing-Ying Wang, / Hsiu-Ming Chang, / Kwang-Ting Cheng, et al. | 2011
- 1
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FARM: Fault-aware resource management in NoC-based multiprocessor platformsChen-Ling Chou, / Marculescu, R et al. | 2011
- 1
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A new reversible design of BCD adderThapliyal, H / Ranganathan, N et al. | 2011
- 1
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Early chip planning cockpitJeonghee Shin, / Darringer, J A / Guojie Luo, / Weger, A J / Johnson, C L et al. | 2011
- 1
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Floorplanning exploration and performance evaluation of a new Network-on-ChipLicheng Xue, / Weixing Ji, / Qi Zuo, / Yang Zhang, et al. | 2011
- 1
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Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitrationIndrusiak, L S / dos Santos, Osmar Marchi et al. | 2011
- 1
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Reviewers| 2011
- 1
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Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limitsDrmanac, D / Sumikawa, N / Winemberg, L / Wang, Li-C / Abadir, M S et al. | 2011
- 1
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Low-power smart industrial controlBilgic, A / Pichot, V / Gerding, M / Bruns, F et al. | 2011
- 1
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System-assisted analog mixed-signal designShanbhag, N / Singer, A et al. | 2011
- 1
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Battery-supercapacitor hybrid system for high-rate pulsed load applicationsDonghwa Shin, / Younghyun Kim, / Jaeam Seo, / Naehyuck Chang, / Yanzhi Wang, / Pedram, M et al. | 2011
- 1
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Integration of orthogonal QBF solving techniquesReimer, S / Pigorsch, F / Scholl, C / Becker, B et al. | 2011
- 1
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Clock gating optimization with delay-matchingShih-Jung Hsu, / Rung-Bin Lin, et al. | 2011
- 1
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An efficient algorithm for multi-domain clock skew schedulingYanling Zhi, / Wai-Shing Luk, / Hai Zhou, / Changhao Yan, / Hengliang Zhu, / Xuan Zeng, et al. | 2011
- 1
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A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch InitiativeQiuting Huang, / Deholain, C / Enz, C / Burger, T et al. | 2011
- 1
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DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive schedulingPeng-Chih Wang, / Meng-Huan Wu, / Ren-Song Tsay, et al. | 2011
- 1
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Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variationsDa-Cheng Juan, / Garg, S / Marculescu, D et al. | 2011
- 1
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Dynamic write limited minimum operating voltage for nanoscale SRAMsNalam, S / Chandra, V / Aitken, R C / Calhoun, B H et al. | 2011
- 1
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Simulation based tuning of system specificationZaidi, Y / Grimm, C / Haase, J et al. | 2011
- 1
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Variation aware dynamic power management for chip multiprocessor architecturesGhasemazar, M / Pedram, M et al. | 2011
- 1
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Proactive recovery for BTI in high-k SRAM cellsLin Li, / Youtao Zhang, / Jun Yang, et al. | 2011
- 1
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Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate modelBo Liu, / Ying He, / Reynaert, P / Gielen, G et al. | 2011
- 1
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Smart systems at STPapa, C et al. | 2011
- 1
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Buffering implications for the design space of streaming MEMS storageKhatib, M G / Abelmann, L et al. | 2011
- 1
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An efficient Quantum-Dot Cellular Automata adderBruschi, F / Perini, F / Rana, V / Sciuto, D et al. | 2011
- 1
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Pseudo circuit model for representing uncertainty in waveformsNigam, A / Qin Tang, / Zjajo, A / Berkelaar, M / van der Meijs, N et al. | 2011
- 1
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Counterexample-guided SMT-driven optimal buffer sizingBrady, B A / Holcomb, D / Seshia, S A et al. | 2011
- 1
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A 3D reconfigurable platform for 4G telecom applicationsLafi, W / Lattard, D / Jerraya, A et al. | 2011
- 1
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Efficient parameter variation sampling for architecture simulationsFeng Lu, / Joseph, R / Trajcevski, G / Song Liu, et al. | 2011
- 1
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2011 EDAA/ACM SIGDA PhD Forum at DATE in Grenoble| 2011
- 1
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Cycle-count-accurate processor modeling for fast and accurate system-level simulationChen-Kang Lo, / Li-Chun Chen, / Meng-Huan Wu, / Ren-Song Tsay, et al. | 2011
- 1
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Realistic performance-constrained pipelining in high-level synthesisKondratyev, A / Lavagno, L / Meyer, M / Watanabe, Y et al. | 2011
- 1
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Architecture and FPGA-implementation of a high throughput K+-Best detectorHeidmann, N / Wiegand, T / Paul, S et al. | 2011
- 1
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Wireless innovations for smartphonesKauppinen, H et al. | 2011
- 1
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Power optimization in heterogenous datapathsDel Barrio, A A / Memik, S O / Molina, M C / Mendias, J M / Hermida, R et al. | 2011
- 1
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Depth-directed hardware object detectionKyrkou, C / Ttofis, C / Theocharides, T et al. | 2011
- 1
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Reliability-driven don't care assignment for logic synthesisZukoski, A / Choudhury, M R / Mohanram, K et al. | 2011
- 1
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Automated constraint-driven topology synthesis for analog circuitsMitea, O / Meissner, M / Hedrich, L / Jores, P et al. | 2011
- 1
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NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCsPorquet, J / Greiner, A / Schwarz, C et al. | 2011
- 1
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STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebraPavlenko, E / Wedler, M / Stoffel, D / Kunz, W / Dreyer, A / Seelisch, F / Greuel, G et al. | 2011
- 1
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Timing-constrained I/O buffer placement for flip-chip designsZhi-Wei Chen, / Jin-Tai Yan, et al. | 2011
- 1
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Parallelization of while loops in nested loop programs for shared-memory multiprocessor systemsGeuns, S J / Bekooij, M J G / Bijlsma, T / Corporaal, H et al. | 2011
- 1
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Minority-Game-based resource allocation for run-time reconfigurable multi-core processorsShafique, M / Bauer, L / Ahmed, W / Henkel, J et al. | 2011
- 1
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X-SENSE: Sensing in extreme environmentsBeutel, J / Buchli, B / Ferrari, F / Keller, M / Zimmerling, M / Thiele, Lothar et al. | 2011
- 1
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System-level energy-efficient scheduling for hard real-time embedded systemsLinwei Niu, et al. | 2011
- 1
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Topologically homogeneous power-performance heterogeneous multicore systemsChakraborty, K / Roy, S et al. | 2011
- 1
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Author index| 2011
- 1
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Testing of high-speed DACs using PRBS generation with “Alternate-Bit-Tapping”Singh, M / Sakare, M / Gupta, S et al. | 2011
- 1
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Virtual Manycore platforms: Moving towards 100+ processor coresLeupers, R / Eeckhout, L / Martin, G / Schirrmeister, F / Topham, N / Xiaotao Chen, et al. | 2011
- 1
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Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraintsYi-Sheng Chiu, / Chi-Sheng Shih, / Shih-Hao Hung, et al. | 2011
- 1
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Panel: What does the power industry need from the EDA industry and what is the EDA industry doing about it?Wright, P K et al. | 2011
- 1
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On the efficacy of NBTI mitigation techniquesTuck-Boon Chan, / Sartori, J / Gupta, P / Kumar, R et al. | 2011
- 1
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When to stop verification?: Statistical trade-off between expected loss and simulation costJha, S K / Langmead, C J / Mohalik, S / Ramesh, S et al. | 2011
- 1
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mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensionsAhmed, W / Shafique, M / Bauer, L / Henkel, Jörg et al. | 2011
- 1
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A confidence-driven model for error-resilient computingChia-Hsiang Chen, / Yejoong Kim, / Zhengya Zhang, / Blaauw, D / Sylvester, D / Naeimi, H / Sandhu, S et al. | 2011
- 1
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RON: An on-chip ring oscillator network for hardware Trojan detectionXuehui Zhang, / Tehranipoor, M et al. | 2011
- 1
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Dynamic thermal management in 3D multi-core architecture through run-time adaptationHameed, F / Faruque, M A A / Henkel, J et al. | 2011
- 1
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Smart devices panel session — Integrating the real world interfacesJerraya, A. / Goodacre, J. et al. | 2011
- 1
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On multiplexed signal tracing for post-silicon debugXiao Liu, / Qiang Xu, et al. | 2011
- 1
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Sensor networks on the car: State of the art and future challengesD'Orazio, L / Visintainer, F / Darin, M et al. | 2011
- 1
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A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodelsGobbato, L / Chinea, A / Grivet-Talocia, S et al. | 2011
- 1
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DynOAA — Dynamic offset adaptation algorithm for improving response times of CAN systemsZiermann, T / Teich, Jürgen / Salcic, Z et al. | 2011
- 1
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Intermediate representations for controllers in chip generatorsKelley, K / Wachs, M / Danowitz, A / Stevenson, P / Richardon, S / Horowitz, M et al. | 2011
- 1
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Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigationGielen, G / Maricau, E / De Wit, P et al. | 2011
- 1
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Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computersZhimin Chen, / Xu Guo, / Sinha, A / Schaumont, P et al. | 2011
- 1
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HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiencyMirhoseini, A / Koushanfar, F et al. | 2011
- 1
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A multi-objective decision-theoretic exploration algorithm for platform-based designBeltrame, G / Nicolescu, G et al. | 2011
- 1
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Variability-aware duty cycle scheduling in long running embedded sensing systemsWanner, L / Balani, R / Zahedi, S / Apte, C / Gupta, P / Srivastava, M et al. | 2011
- 1
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Architectures for online error detection and recovery in multicore processorsGizopoulos, D / Psarakis, M / Adve, S V / Ramachandran, P / Hari, S K S / Sorin, D / Meixner, A / Biswas, A / Vera, X et al. | 2011
- 1
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ReliNoC: A reliable network for priority-based on-chip communicationKakoee, M R / Bertacco, V / Benini, L et al. | 2011
- 1
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Re-engineering cyber-physical control applications for hybrid communication protocolsGoswami, D / Schneider, R / Chakraborty, S et al. | 2011
- 1
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An effective multi-source energy harvester for low power applicationsCarli, D / Brunelli, D / Benini, L / Ruggeri, M et al. | 2011
- 1
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Mathematical approach based on a “Design of Experiment” to simulate process variationsRémond, Eric / Nercessian, E / Bernicot, C / Mina, R et al. | 2011
- 1
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Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdownChandra, V / Aitken, R et al. | 2011
- 1
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Pruning infeasible paths for tight WCRT analysis of synchronous programsAndalam, S / Roop, P S / Girault, A et al. | 2011
- 1
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Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoringOnizawa, N / Matsumoto, A / Hanyu, T et al. | 2011
- 1
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Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testingKumar, A / Reddy, S M / Pomeranz, I / Becker, B et al. | 2011
- 1
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Compiling SyncCharts to Synchronous CTraulsen, C / Amende, T / von Hanxleden, R et al. | 2011
- 1
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3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layersYi-Chung Chen, / Hai Li, / Yiran Chen, / Pino, R E et al. | 2011
- 1
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Developing an integrated verification and debug methodologyMatsuda, A / Ishihara, T et al. | 2011
- 1
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An efficient mask optimization method based on homotopy continuation techniqueLiu, F / Xiaokang Shi, et al. | 2011
- 1
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Component-based design for the futureLee, E A / Sangiovanni-Vincentelli, A L et al. | 2011
- 1
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A high-level analytical model for application specific CMP design explorationCassidy, A / Kai Yu, / Haolang Zhou, / Andreou, A G et al. | 2011
- 1
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Loop distribution for K-loops on Reconfigurable ArchitecturesDragomir, O S / Bertels, K et al. | 2011
- 1
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Precise WCET calculation in highly variant real-time systemsMontag, P / Altmeyer, S et al. | 2011
- 1
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Energy parsimonious circuit design through probabilistic pruningLingamneni, A / Enz, C / Nagel, J.-L / Palem, K / Piguet, C et al. | 2011
- 1
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Using contract-based component specifications for virtual integration testing and architecture designDamm, W / Hungar, H / Josko, B / Peikenkamp, T / Stierand, I et al. | 2011
- 1
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E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memoriesBathen, L A D / Dutt, N D et al. | 2011
- 1
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Modeling manufacturing process variation for design and testKundu, S / Sreedhar, A et al. | 2011
- 1
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Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point linksAsadinia, M / Modarressi, M / Tavakkol, A / Sarbazi-Azad, H et al. | 2011
- 1
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Efficient RC power grid verification using node eliminationGoyal, A / Najm, F N et al. | 2011
- 1
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Biologically-inspired massively-parallel architectures — Computing beyond a million processorsFurber, S et al. | 2011
- 1
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Simplified programming of faulty sensor networks via code transformation and run-time interval computationBai, L S / Dick, R P / Dinda, P A / Chou, P H et al. | 2011
- 1
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[Copyright notice]| 2011
- 1
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Predicting bus contention effects on energy and performance in multi-processor SoCsPenolazzi, S / Sander, I / Hemani, A et al. | 2011
- 1
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A clock-gating based capture power droop reduction methodology for at-speed scan testingBo Yang, / Sanghani, A / Sarangi, S / Chunsheng Liu, et al. | 2011
- 1
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An algorithm to improve accuracy of criticality in statistical static timing analysisTsukiyama, S / Fukui, M et al. | 2011
- 1
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A low complexity stopping criterion for reducing power consumption in turbo decodersReddy, P / Clermidy, F / Baghdadi, A / Jezequel, M et al. | 2011
- 1
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Design of voltage-scalable meta-functions for approximate computingMohapatra, D / Chippa, V K / Raghunathan, A / Roy, K et al. | 2011
- 1
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Built-in generation of functional broadside testsPomeranz, I et al. | 2011
- 1
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A fault-tolerant deadlock-free adaptive routing for on chip interconnectsChaix, F / Avresky, D / Zergainoh, N-E / Nicolaidis, M et al. | 2011
- 1
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Empirical design bugs prediction for verificationQi Guo, / Tianshi Chen, / Haihua Shen, / Yunji Chen, / Yue Wu, / Weiwu Hu, et al. | 2011
- 1
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An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platformsPaterna, F / Acquaviva, A / Caprara, A / Papariello, F / Desoli, G / Benini, L et al. | 2011
- 1
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Black-box leakage power modeling for cell library and SRAM compilerChun-Kai Tseng, / Shi-Yu Huang, / Chia-Chien Weng, / Shan-Chien Fang, / Ji-Jan Chen, et al. | 2011
- 1
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Methods and tools for component-based system designSifakis, J et al. | 2011
- 1
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Eliminating speed penalty in ECC protected memoriesNicolaidis, M / Bonnoit, T / Zergainoh, N-E et al. | 2011
- 1
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Robust 6T Si tunneling transistor SRAM designXuebei Yang, / Mohanram, Kartik et al. | 2011
- 1
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High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switchesXinmu Wang, / Narasimhan, S / Krishna, A / Wolff, F G / Rajgopal, S / Te-Hao Lee, / Mehregany, M / Bhunia, S et al. | 2011
- 1
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Energy-modulated computingYakovlev, A et al. | 2011
- 1
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A unified methodology for pre-silicon verification and post-silicon validationAdir, A / Copty, S / Landa, S / Nahir, A / Shurek, G / Ziv, A / Meissner, C / Schumann, J et al. | 2011
- 1
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An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computationBarceló, S / Gili, X / Bota, Sebastià / Segura, J et al. | 2011
- 1
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Stage number optimization for switched capacitor power converters in micro-scale energy harvestingChao Lu, / Sang Phill Park, / Raghunathan, V / Roy, K et al. | 2011
- 1
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Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systemsRinaudo, S / Gangemi, G / Calimera, A / Macii, A / Poncino, M et al. | 2011
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Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networksSassone, Alessandro / Calimera, Andrea / Macii, Alberto / Macii, Enrico / Poncino, Massimo / Goldman, Rich / Melikyan, Vazgen / Babayan, Eduard / Rinaudo, Salvatore et al. | 2012
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