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Describes technologies for a 2 mum n-ch E/D MOS logic LSI fabrication process; threshold voltage control technology for enhancement type MOSFET and depletion type MOSFET, buried contact technology to connect a polysilicon layer with a diffused layer directly, load resistor formation technology for static MOSRAM, two-level metal interconnection technology, and 5 V single power supply technology. The process is useful to realize logic LSIs with high integration density. Performances for the fabricated E/D ring oscillator (FO=3) are 0.3 mW/gate in power dissipation and 0.8 ns/gate in propagation delay. The integration density for LSIs using the process is 1.5 times larger than that using the conventional process. These technologies have been applied to realize PARCOR CODEC LSI, 1 kbit associative memory and other LSIs.