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As further enhanced functionalities of mobile equipment are predicted, the development of a CMOS technology that provides low-power, high-speed, and low-noise performance has become an urgent and hot issue. For these application driven technologies, the complexity must be tackled at different levels to insure the optimisation of the area, the power consumption, the speed and the reliability. Therefore, this paper presents a review of the solutions implemented at different levels from system down to technology in order to reduce the contribution of low frequency noise. These achievements are illustrated by experimental results from literature and are inserted in the general context of system design strategies for reducing the 1/f noise contribution. In the first part, dedicated to a high-level system and circuit design, we introduce noise reduction by switching techniques and the methodology for including noise dispersion in scaled devices for the early design of analogue/RF circuits. In the second part, the 1/f noise is tackled at its origins, i.e., the choice of the gate oxide and other critical process steps.