Device technology for body biasing scheme (Englisch)
- Neue Suche nach: Imai, K.
- Neue Suche nach: Yamagata, Y.
- Neue Suche nach: Masuoka, S.
- Neue Suche nach: Kimuzuka, N.
- Neue Suche nach: Yasuda, Y.
- Neue Suche nach: Togo, M.
- Neue Suche nach: Ikeda, M.
- Neue Suche nach: Nakashiba, Y.
- Neue Suche nach: Imai, K.
- Neue Suche nach: Yamagata, Y.
- Neue Suche nach: Masuoka, S.
- Neue Suche nach: Kimuzuka, N.
- Neue Suche nach: Yasuda, Y.
- Neue Suche nach: Togo, M.
- Neue Suche nach: Ikeda, M.
- Neue Suche nach: Nakashiba, Y.
In:
ISCAS, IEEE International Symposium on Circuits and Systems, 2005
;
13-16
;
2005
-
ISBN:
- Aufsatz (Konferenz) / Print
-
Titel:Device technology for body biasing scheme
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Beteiligte:Imai, K. ( Autor:in ) / Yamagata, Y. ( Autor:in ) / Masuoka, S. ( Autor:in ) / Kimuzuka, N. ( Autor:in ) / Yasuda, Y. ( Autor:in ) / Togo, M. ( Autor:in ) / Ikeda, M. ( Autor:in ) / Nakashiba, Y. ( Autor:in )
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Erschienen in:
-
Verlag:
- Neue Suche nach: IEEE Operations Center
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Erscheinungsort:Piscataway
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Erscheinungsdatum:2005
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Format / Umfang:4 Seiten, 6 Quellen
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ISBN:
-
DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
-
Sprache:Englisch
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Schlagwörter:
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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Asymmetric halo CMOSFET to reduce static power dissipation with improved performanceBansal, A. / Roy, K. et al. | 2005
- 5
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Limits to performance spread tuning using adaptive voltage and body biasingMeijer, M. / Pessolano, F. / de Gyvez, J.P. et al. | 2005
- 9
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Adaptive circuit techniques to minimize variation impacts on microprocessor performance and powerTschanz, J. / Narendra, S. / Keshavarzi, A. / De, V. et al. | 2005
- 13
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Device technology for body biasing schemeImai, K. / Yamagata, Y. / Masuoka, S. / Kimuzuka, N. / Yasuda, Y. / Togo, M. / Ikeda, M. / Nakashiba, Y. et al. | 2005
- 17
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Optimum threshold-voltage tuning for low-power, high-performance microprocessorMiyazaki, M. / Ono, G. / Kawahara, T. et al. | 2005
- 21
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Minimizing power with flexible voltage islandsPuri, R. / Kung, D. / Stok, L. et al. | 2005
- 25
-
Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoderHatakawa, Y. / Yoshizawa, S. / Miyanaga, Y. et al. | 2005
- 29
-
A systematic framework for high throughput MAP decoder VLSI architecturesElassal, M. / Kumar, A. / Bayoumi, M. et al. | 2005
- 33
-
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- 37
-
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- 41
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A novel low-power reconfigurable FFT processorYutian Zhao, / Erdogan, A.T. / Arslan, T. et al. | 2005
- 45
-
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- 49
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- 53
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Synthesis of reconfigurable multiplier blocks: part - II algorithmDemirsoy, S.S. / Kale, I. / Dempster, A.G. et al. | 2005
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A hardware-efficient FIR architecture with input-data and tap foldingLi-Hsun Chen, / Chen, O.T.-C. et al. | 2005
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Residue number system implementations of complex heterodyne tunable filtersSoderstrand, M.A. / Cho, G.Y. / Johnson, L.G. et al. | 2005
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Low complexity decimation filter for multi-standard digital receiversTecpanecatl-Xihuitl, J.L. / Kumar, A. / Bayoumi, M.A. et al. | 2005
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Stability of a shift-variant 2-D state-space digital filterMabey, G.W. / Bose, T. / Mei Chen, et al. | 2005
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A time-to-digital-converter-based CMOS smart temperature sensorChun-Chi Chen, / Wen-Fu Lu, / Chin-Chung Tsai, / Chen, P. et al. | 2005
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High-speed sensing system for depth estimation based on depth-from-focus by using smart imagerYokota, A. / Yoshida, T. / Kashiyama, H. / Hamamoto, T. et al. | 2005
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A CMOS imager for light blobs detection and processingGonzalez, J.L. / Sadowski, D. / Kaler, K.V.I.S. / Mintchev, M.P. / Yadid-Pecht, O. et al. | 2005
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Design of electro-optical demodulating pixel in CMOS technologyDe Nisi, F. / Stoppa, D. / Scandiuzzo, M. / Gonzo, L. / Pancheri, L. / Betta, G.-F.D. et al. | 2005
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Digital measurement of human proximity to electrical power circuit by a novel amplitude-shift-keying radio-frequency receiverZeng, S. / Powers, J.R. / Jackson, L.L. / Conover, D.L. et al. | 2005
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Low-power global/rolling shutter image sensors in silicon on sapphire technologyFish, A. / Avner, E. / Yadid-Pecht, O. et al. | 2005
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Low power current mode ADC for CMOS sensor ICAgarwal, A. / Kim, Y.B. / Sonkusale, S. et al. | 2005
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A wide dynamic range CMOS active pixel sensor with frame differenceMilirud, V. / Fleshel, L. / Zhang, W. / Jullien, G. / Yadid-Pecht, O. et al. | 2005
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Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip busesGhoneima, M. / Ismail, Y. / Khellah, M. / Tschanz, J. / Ye, Y. / De, V. et al. | 2005
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Low power repeaters driving RLC interconnects with delay and bandwidth constraintsGuoqing Chen, / Friedman, E.G. et al. | 2005
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Low-leakage repeaters for NoC interconnectsMorgenshtein, A. / Cidon, I. / Kolodny, A. / Ginosar, R. et al. | 2005
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Power-aware global signaling strategiesSylvester, D. / Kaul, H. / Agarwal, K. / Rao, R.M. / Nassif, S. / Brown, R.B. et al. | 2005
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Designing optimized pipelined global interconnects: algorithms and methodology impactNookala, V. / Sapatnekar, S.S. et al. | 2005
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Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environmentSecareanu, R.M. / Banejee, S.K. / Hartin, O. / Fernandez, V. / Friedman, E.G. et al. | 2005
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Battery-aware dynamic voltage scaling in multiprocessor embedded systemYuan Cai, / Reddy, S.M. / Pomeranz, I. / Al-Hashimi, B.M. et al. | 2005
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Noise coupling in multi-voltage power distribution systems with decoupling capacitorsPopovich, M. / Friedman, E.G. et al. | 2005
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A 16-bit low-power microcontroller with monolithic MEMS-LC clockingMarsman, E.D. / Senger, R.M. / McCorquodale, M.S. / Guthaus, M.R. / Ravindran, R.A. / Brown, R.B. / Dasika, G.S. / Mahlke, S.A. et al. | 2005
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A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysisNakamura, Y. / Yoshimura, T. et al. | 2005
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An LSI system with locked in temperature insensitive state achieved by using body bias techniqueOno, G. / Miyazaki, M. / Watanabe, K. / Kawahara, T. et al. | 2005
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An energy-efficient circuit technique for single event transient noise-toleranceMing Zhang, / Shanbhag, N.R. et al. | 2005
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Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networksChi-Fu Huang, / Li-Chu Lo, / Yu-Chee Tseng, / Wen-Tsuen Chen, et al. | 2005
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Event-based imaging with active illumination in sensor networksTeixeira, T. / Andreou, A.G. / Culurciello, E. et al. | 2005
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On the construction of efficient data gathering tree in wireless sensor networksThepvilojanapong, N. / Tobe, Y. / Sezaki, K. et al. | 2005
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A RF map-based localization algorithm for indoor environmentsAlippi, C. / Mottarella, A. / Vanini, G. et al. | 2005
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A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adderBin Cao, / Chip-Hong Chang, / Srikanthan, T. et al. | 2005
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A NEW FORMULATION OF FAST DIMINISHED-ONE MULTIOPERAND MODULO 2^N+1 ADDERCao, B. / Chang, C.-H. / Srikanthan, T. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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Non-interleaving architecture for hardware implementation of modular multiplicationQiang Liu, / Dong Tong, / Xu Cheng, et al. | 2005
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A NEW DESIGN METHOD TO MODULO 2^N-1 SQUARINGCao, B. / Srikanthan, T. / Chang, C.-H. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A new design method to modulo 2/sup n/-1 squaringBin Cao, / Srikanthan, T. / Chip-Hong Chang, et al. | 2005
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Constant addition utilizing flagged prefix structuresStine, J.E. / Babb, C.R. / Dave, V.B. et al. | 2005
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Efficient VLSI implementation of N/N integer divisionKei-Yong Khoo, / Willson, A.N. et al. | 2005
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A novel design of leading zero anticipation circuit with parallel error detectionGe Zhang, / Zichu Qi, / Weiwu Hu, et al. | 2005
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High-level synthesis under I/O timing and memory constraintsCoussy, P. / Corre, G. / Bomel, P. / Senn, E. / Martin, E. et al. | 2005
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A LOW POWER SCHEDULING METHOD USING DUAL V~D~D AND DUAL V~T~HTsai, K.-L. / Chang, S.-W. / Lai, F. / Ruan, S.-J. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A low power scheduling method using dual V/sub dd/ and dual V/sub th/Kun-Lin Tsai, / Szu-Wei Chang, / Feipei Lai, / Shanq-Jang Ruan, et al. | 2005
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A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltagesLing Wang, / Yingtao Jiang, / Yu Zhang, / Ru Chen, et al. | 2005
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A heuristic approach for multiple restricted multiplicationSidahao, N. / Constantinides, G.A. / Cheung, P.Y.K. et al. | 2005
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Lower-bound estimation for multi-bitwidth schedulingJunjuan Xu, / Cong, J. / Xu Cheng, et al. | 2005
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Statistical schedule length analysis in asynchronous datapath synthesisOhashi, K. / Kaneko, M. et al. | 2005
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Comparison of two class E amplifiers for EER transmitterHeiskanen, A. / Rahkonen, T. et al. | 2005
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Steady-state behavior of class E amplifier outside designed conditionsSuetsugu, T. / Kazimierczuk, M. et al. | 2005
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Voltage-clamped class E amplifier with transmission-line transformerSuetsugu, T. / Kazimierczuk, M. et al. | 2005
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Optimum design of very low distortion class E power amplifiersSiu Chung Wong, / Tse, C.K. et al. | 2005
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Resonant DC/DC converter with class E oscillatorHase, H. / Sekiya, H. / Jianming Lu, / Yahagi, T. et al. | 2005
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Planar inductors with interleaved conductors for integrated power applicationsSalles, A. / Estibals, B. / Bourrier, D. / Alonso, C. et al. | 2005
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A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensorsRankov, A. / Rodriguez-Villegas, E. / Lee, M.J. et al. | 2005
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On-chip active power rectifiers for biomedical applicationsLehmann, T. / Moghe, Y. et al. | 2005
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A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applicationsHwang-Cherng Chow, / Bo-Wei Chen, / Hsiao-Chen Chen, / Wu-Shiung Feng, et al. | 2005
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A 0.9-V 67-/spl mu/W analog front-end using adaptive-SNR technique for digital hearing aidSunyoung Kim, / Jae-Youl Lee, / Seong-Jun Song, / Namjun Cho, / Hoi-Jun Yoo, et al. | 2005
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A 0.9-V 67-muW ANALOG FRONT-END USING ADAPTIVE-SNR TECHNIQUE FOR DIGITAL HEARING AIDKim, S. / Lee, J.-Y. / Song, S.-J. / Cho, N. / Yoo, H.-J. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A BiCMOS ENG amplifier with high SIR outputTriantis, I.F. / Demosthenous, A. et al. | 2005
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10-channel very low noise ENG amplifier system using CMOS technologyRieger, R. / Pal, D. / Taylor, J. / Clarke, C. / Langlois, P. / Donaldson, N. et al. | 2005
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Minimum augmentation to bi-connect specified vertices of a graph with upper bounds on vertex-degreeMashima, T. / Fukuoka, T. / Taoka, S. / Watanabe, T. et al. | 2005
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A modeling method of a rule based control system with hierarchical Petri netSakamoto, M. / Miyamoto, T. / Kumagai, S. et al. | 2005
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Minimal time reachability problem of some subclasses of timed Petri netsOhta, A. / Tsuji, K. / Hisamura, T. et al. | 2005
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The node voltage equations and structural conditions of observability for RLC networks over F(z)Kai-Sheng Lu, / Guo-Zhang Gao, et al. | 2005
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Graph-theoretic approach to the design of four-switch DC-DC convertersOgata, M. / Nishi, T. et al. | 2005
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Simplified algorithm to determine break point realys & relay coordination based on network topology [for realys read relays]Mks, S. et al. | 2005
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SIMPLIFIED ALGORITHM TO DETERMINE BREAK POINT REALYS & RELAY COORDINATION BASED ON NETWORK TOPOLOGYMks, S. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A low-distortion 1.2 V DAC+filter for transmitters in wireless applicationsGhittori, N. / Vigna, A. / Malcovati, P. / Baschirotto, A. / D'Amico, S. et al. | 2005
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Adjustable gamma correction circuit for TFT LCDPo-Ming Lee, / Hung-Yi Chen, et al. | 2005
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A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC testHanjun Jiang, / Olleta, B. / Degang Chen, / Geiger, R.L. et al. | 2005
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A start-up calibration method for generic current-steering D/A converters with optimal area solutionRadulov, G.I. / Quinn, P.J. / Hegt, J.A. / van Roermund, A.H.M. et al. | 2005
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Pipeline ADC linearity testing with dramatically reduced data capture timeZhongjun Yu, / Degang Chen, / Geiger, R. / Papantonopoulos, Y. et al. | 2005
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On-chip built-in self-test of video-rate ADCs using Gaussian noiseEvans, G. / Goes, J. / Paulino, N. et al. | 2005
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A 0.18muM CMOS LOW-NOISE ELLIPTIC LOW-PASS CONTINUOUS-TIME FILTERFernandez-Bootello, J. F. / Delgado-Restituto, M. / Rodriguez-Vazquez, A. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A 0.18 /spl mu/m CMOS low-noise elliptic low-pass continuous-time filterFernandez-Bootello, J.F. / Delgado-Restituto, M. / Rodriguez-Vazquez, A. et al. | 2005
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Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum componentsShu-Hui Tu, / Ross, J.N. et al. | 2005
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Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networksJurisic, D. / Mijat, N. / Moschytz, G.S. et al. | 2005
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A widely tunable Gm-C filter using tail current offset in two differential pairsTanaka, T. / Sungwoo Cha, / Shimizu, S. / Ida, T. / Ishihara, H. / Matsuoka, T. / Taniguchi, K. / Sugimori, A. / Hihara, H. et al. | 2005
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A comparison approach of lowpass type wave active filter using unified circuit blockHirano, S. / Sato, A. / Kitamura, T. et al. | 2005
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Single amplifier bi-quadratic filter topologies in transimpedance configurationChandra, G. / Tadeparthy, P. / Easwaran, P. et al. | 2005
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Quantum circuit design of discrete Hartley transform using recursive decomposition formulaChien-Cheng Tseng, / Tsung-Ming Hwang, et al. | 2005
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QUANTUM CIRCUIT DESIGN OF 8x8 DISCRETE COSINE TRANSFORM USING ITS FAST COMPUTATION FLOW GRAPHTseng, C.-C. / Hwang, T.-M. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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Quantum circuit design of 8/spl times/8 discrete cosine transform using its fast computation flow graphChien-Cheng Tseng, / Tsung-Ming Hwang, et al. | 2005
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Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrixHanna, M.T. / Seif, N.P.A. / Ahmed, W.A.E.M. et al. | 2005
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An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structureBouguezel, S. / Ahmad, M.O. / Swamy, M.N.S. et al. | 2005
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Design of wavelet filters based on digital complex allpass filtersFernandez-Vazquez, A. / Jovanovic-Dolecek, G. et al. | 2005
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Block time-recursive discrete Gabor transform implemented by unified parallel lattice structuresLiang, T. / Kwan, H.K. et al. | 2005
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Rate determination based on perceptual loudnessAtti, V. / Spanias, A. et al. | 2005
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A mixed analog-digital hybrid for speech enhancement purposesSallberg, B. / Akesson, H. / Dahl, M. / Claesson, I. et al. | 2005
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Adaptive beamformer for hands-free communication system in noisy environmentsHai Quang Dam, / Nordholm, S. / Hai Huyen Dam, / Siow Yong Low, et al. | 2005
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Audio classification and scene recognition and for hearing aidsRavindran, S. / Anderson, D.V. et al. | 2005
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A VERSATILE SPEECH ENHANCMENT SYSTEM BASED ON PERCEPTUAL WAVELET DENOISINGShao, Y. / Chang, C.-H. / Institute of Electrical and Electronics Engineers / IEEE Circuits and Systems Society et al. | 2005
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A versatile speech enhancement system based on perceptual wavelet denoisingYu Shao, / Chip-Hong Chang, et al. | 2005
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Improved voice activity detection via contextual information and noise suppressionSangwan, A. / Zhu, W.P. / Ahmad, M.O. et al. | 2005
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Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chainsFujisaki, H. / Keller, G. et al. | 2005
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Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systemsJi Yao, / Lawrance, A.J. et al. | 2005
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Cryptanalysis of a multistage encryption systemChengqing, L. / Xinxiao Li, / Shujun Li, / Guanrong Chen, et al. | 2005