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The size of metal-oxide-semiconductor field effect transistors has been drastically miniaturized to achieve higher performance according to the scaling law. 0.1 mu m complementary metal-oxide-semiconductor (CMOS) technology is no longer at the frontier of device research; it is being optimized as a real device. The scaling law has been partly modified but the overall direction of device technology is still following that scenario. This article will first review some key messages that have been learned from 0.1 mu m CMOS development in our laboratories. In the sub-0.1 mu m era, there will be a strong demand for new device physics and technologies, including new materials, for a new electronics paradigm. As an example of the new devices, silicon single electron tunneling devices will be discussed here in terms of their graceful assimilation into the current silicon ultralarge scale integration world