Whole-Chip ESD Protection for CMOS VLSI/ULSI with Multiple Power PINs (Englisch)
- Neue Suche nach: Ker, M.-D.
- Neue Suche nach: Wu, C.-Y.
- Neue Suche nach: Cheng, T.
- Neue Suche nach: Tsai, H.-J.
- Neue Suche nach: IEEE Electron Devices Society
- Neue Suche nach: IEEE Reliability Society
- Neue Suche nach: Ker, M.-D.
- Neue Suche nach: Wu, C.-Y.
- Neue Suche nach: Cheng, T.
- Neue Suche nach: Tsai, H.-J.
- Neue Suche nach: IEEE Electron Devices Society
- Neue Suche nach: IEEE Reliability Society
In:
International integrated reliability workshop
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124-128
;
1994
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:Whole-Chip ESD Protection for CMOS VLSI/ULSI with Multiple Power PINs
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Beteiligte:Ker, M.-D. ( Autor:in ) / Wu, C.-Y. ( Autor:in ) / Cheng, T. ( Autor:in ) / Tsai, H.-J. ( Autor:in ) / IEEE Electron Devices Society / IEEE Reliability Society
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Kongress:International integrated reliability workshop ; 1994 ; Lake Tahoe; CA
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE Reliability Society
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Erscheinungsort:[New York] , IEEE Electron Devices Society
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Erscheinungsdatum:01.01.1994
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Format / Umfang:5 pages
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Anmerkungen:IEEE cat no 94TH0654-4
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
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Inhaltsverzeichnis Konferenzband
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Whole-Chip ESD Protection for CMOS VLSI/ULSI with Multiple Power PINsKer, M.-D. / Wu, C.-Y. / Cheng, T. / Tsai, H.-J. / IEEE Electron Devices Society / IEEE Reliability Society et al. | 1994
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- i
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Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)| 1994