Optimizing Designs Containing Black Boxes (Englisch)
- Neue Suche nach: Liu, T.-H.
- Neue Suche nach: Sajid, K.
- Neue Suche nach: Aziz, A.
- Neue Suche nach: Singhal, V.
- Neue Suche nach: Liu, T.-H.
- Neue Suche nach: Sajid, K.
- Neue Suche nach: Aziz, A.
- Neue Suche nach: Singhal, V.
In:
Design automation conference
34
;
113-116
;
1997
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ISBN:
-
ISSN:
- Aufsatz (Konferenz) / Print
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Titel:Optimizing Designs Containing Black Boxes
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Beteiligte:
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Kongress:34th, Design automation conference ; 1997 ; Anaheim; CA
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Erschienen in:Design automation conference , 34 ; 113-116DESIGN AUTOMATION CONFERENCE , 34 ; 113-116
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.1997
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Format / Umfang:4 pages
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Anmerkungen:Described as proceedings. IEEE cat no 97CH36101 and 97CB36101
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ISBN:
-
ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 2
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An Improved Algorithm For Minimum-area RetimingMaheshwari, N. / Sapatnekar, S.S. et al. | 1997
- 8
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Efficient Latch Optimization Using Exclusive SetsSentovich, E.M. / Toma, H. / Berry, G. et al. | 1997
- 12
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Sequence Compaction For Probabilistic Analysis Of Finite-state MachinesMarculescu, D. / Marculescu, R. / Pedram, M. et al. | 1997
- 16
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Synthesis Of Speed-independent Circuits From STG-unfolding SegmentSemenov, A. / Yakovlev, A. / Pastor, E. / Pena, M.A. / Cortadella, J. et al. | 1997
- 22
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Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency ControlBenini, L. / Macii, E. / Poncino, M. et al. | 1997
- 22
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Telescopic Units: Increasing The Average Throughput Pipelined Designs By Adaptive Latency ControlBenini, L. / Macii, E. / Poncino, M. et al. | 1997
- 28
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Zeros And Passivity Of Arnoldi-reduced-order Models For Interconnect NetworksElfadel, I.M. / Ling, D.D. et al. | 1997
- 34
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Preservation Of Passivity During RLC Network Reduction Via Split Congruence TransformationsKerns, K.J. / Yang, A.T. et al. | 1997
- 40
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Lumped Interconnect Models Via Gaussian QuadratureNabors, K. / Tze-Ting Fang, / Hung-Wen Chang, / Kundert, K.S. / White, J.K. et al. | 1997
- 46
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Calculating worst-case gate delays due to dominant capacitance couplingDartu, F. / Pileggi, L.T. et al. | 1997
- 52
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Schedule Validation For Embedded Reactive Real-time SystemsBalarin, F. / Sangiovanni-Vincentelli, A. et al. | 1997
- 58
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Incorporating Imprecise Computation Into System-level Design Of Application-specific Heterogeneous MultiprocessorsTirat-Gefen, Y.G. / Silva, D.C. / Parker, A.C. et al. | 1997
- 64
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Data Memory Minimisation For Synchronous Data Flow Graphs Emulated On DSP-FPGA TargetsAde, M. / Lauwereins, R. / Peperstraete, J.A. et al. | 1997
- 70
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An Efficient Implementation Of Reactivity For Modeling Hardware In The Scenic Design EnvironmentLiao, S. / Tjiang, S. / Gupta, R. et al. | 1997
- 76
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Embedded Tutorial: Tools and Methodologies for Low Power DesignFrenkil, J. et al. | 1997
- 76
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Tools And Methodologies For Low Power DesignFrenkil, J. et al. | 1997
- 82
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Panel: Low-Power Design Tools - Where Is the Impact?Rabaey, J. M. / Collins, N. / Bell, B. / Frenkil, J. et al. | 1997
- 83
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A C-based RTL Design Verification Methodology For Complex MicroprocessorJoon-Seo Yim, / Yoon-Ho Hwang, / Chang-Jae Park, / Hoon Choi, / Woo-Seung Yang, / Hun-Seung Oh, / In-Cheol Park, / Chong-Min Kyung, et al. | 1997
- 89
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Hierarchical Random Simulation Approach For The Verification Of S/390 Cmos MultiprocessorsWalter, J. / Leenstra, J. / Dottling, G. / Leppla, B. / Munster, H. / Kark, K. / Wile, B. et al. | 1997
- 95
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Efficient Testing Of Clock Regenerator Circuits In Scan DesignsRaina, R. / Bailey, R. / Njinda, C. / Molyneaux, R. / Beh, C. et al. | 1997
- 101
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A Real-time Rtl Engineering-change Method Supporting On-line Debugging For Logic-emulation ApplicationsWen-Jong Fang, / Wu, A.C.-H. / Ti-Yen Yen, et al. | 1997
- 107
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A Graph-based Synthesis Algorithm For AND/XOR NetworksYibin Ye, / Roy, K. et al. | 1997
- 113
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Optimizing Designs Containing Black BoxesTai-Hung Liu, / Sajid, K. / Aziz, A. / Singhal, V. et al. | 1997
- 117
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Solving Covering Problems Using LPR-based Lower BoundsLiao, S. / Devadas, S. et al. | 1997
- 121
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Exact Coloring Of Real-life Graphs Is EasyCoudert, O. et al. | 1997
- 127
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Hierarchical 2-D Field Solution For Capacitance Extraction For VLSI Interconnect ModelingDengi, E.A. / Rohrer, R.A. et al. | 1997
- 133
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Bounds For BEM Capacitance ExtractionBeattie, M.W. / Pileggi, L.T. et al. | 1997
- 137
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SPIE: Sparse Partial Inductance ExtractionZhijiang He, / Celik, M. / Pileggi, L. et al. | 1997
- 141
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A Fast Method Of Moments Solver For Efficient Parameter Extraction Of MCMsKapur, S. / Jinsong Zhao, et al. | 1997
- 147
-
Embedded Tutorial: Static Timing Analysis of Embedded SoftwareMalik, S. / Martonosi, M. / Li, Y.-T. S. et al. | 1997
- 147
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Static Timing Analysis Of Embedded SoftwareMalik, S. / Martonosi, M. / Yau-Tsun Steven Li, et al. | 1997
- 153
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A Task-level Hierarchical Memory Model For System Synthesis Of MultiprocessorsYanbing Li, / Wolf, W. et al. | 1997
- 157
-
Predicting Timing Behavior In Architectural Design Exploration Of Real-time Embedded SystemsSambandam, R.S. / Xiaobo Hu, et al. | 1997
- 161
-
Formal Verification of a Superscalar Execution UnitNelson, K.L. / Jain, A. / Bryant, R.E. et al. | 1997
- 167
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Formal Verification Of Content Addressable Memories Using Symbolic Trajectory EvaluationPandey, M. / Raimi, R. / Bryant, R.E. / Abadir, M.S. et al. | 1997
- 173
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Formal Verification Of FIRE: A Case StudyJae-Young Jang, / Qadeer, S. / Kaufmann, M. / Pixley, C. et al. | 1997
- 178
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Interface-based DesignRowson, J.A. / Sangiovanni-Vincentelli, A. et al. | 1997
- 184
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An Integrated Design Environment For Performance And Dependability AnalysisKlenke, R.H. / Meyassed, M. / Aylor, J.H. / Johnson, B.W. / Rae, R. / Ghosh, A. et al. | 1997
- 190
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A Dynamic Design Estimation And Exploration EnvironmentBentz, O. / Rabaey, J.M. / Lidsky, D. et al. | 1997
- 196
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Remembrance Of Things Past: Locality And Memory In BDDsManne, S. / Grunwald, D. / Somenzi, F. et al. | 1997
- 202
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Linear Sifting Of Decision DiagramsMeinel, C. / Somenzi, F. / Theobald, T. et al. | 1997
- 208
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Safe BDD Minimization Using Don't CaresYoupyo Hong, / Beerel, P.A. / Burch, J.R. / McMillan, K.L. et al. | 1997
- 214
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Timing Optimization For Multi-source Nets: Characterization And Optimal Repeater InsertionLillis, J. / Chung-Kuan Cheng, et al. | 1997
- 220
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Exact Required Time Analysis Via False Path DetectionKttkimoto, Y. / Brayton, R.K. et al. | 1997
- 226
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Symbolic Timing Verification Of Timing Diagrams Using Presburger FormulasAmon, T. / Borriello, G. / Taokuan Hu, / Jiwen Liu, et al. | 1997
- 232
-
Embedded Tutorial: Code Generation for Core ProcessorsGupta, R. / De Micheli, G. / Marwedel, P. et al. | 1997
- 232
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Code Generation For Core ProcessorsMarwedel, P. et al. | 1997
- 238
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Panel: Physical Design And Synthesis: Merge Or DiePedram, M. et al. | 1997
- 240
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Interface Timing Verification Drives System Design Ajay J. DagaDaga, A.J. / Suaris, P.R. et al. | 1997
- 240
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Interface Timing Verification Drives System DesignDaga, A. J. / Suaris, P. R. et al. | 1997
- 246
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Memory-CPU Size Optimization For Embedded System DesignsShackleford, B. / Yasuda, M. / Okushi, E. / Koizumi, H. / Tomiyama, H. / Yasuura, H. et al. | 1997
- 252
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Methodology For Behavioral Synthesis-based Algorithm-level Design Space Exploration: DCT Case StudyPotkonjak, M. / Kyosun Kim, / Karri, R. et al. | 1997
- 258
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Embedded Tutorial: Formal Verification in a Commercial SettingKurshan, R. P. et al. | 1997
- 258
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Formal Verification In A Commercial SettingKurshan, R.P. et al. | 1997
- 263
-
Equivalence Checking Using Cuts And HeapsKuehlmann, A. / Krohm, F. et al. | 1997
- 269
-
Efficient Methods For Simulating Highly Nonlinear Multi-rate CircuitsRoychowdhury, J. et al. | 1997
- 275
-
Rapid Frequency-domain Analog Fault Simulation Under Parameter TolerancesTian, M.W. / Shi, C.-J.R. et al. | 1997
- 281
-
SWITTEST: Automatic Switch-level Fault Simulation And Test Evaluation Of Switched-capacitor SystemsMir, S. / Rueda, A. / Olbrich, T. / Peralias, E. / Huertas, J.L. et al. | 1997
- 287
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Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP ArchitecturesSudarsanam, A. / Liao, S. / Devadas, S. et al. | 1997
- 287
-
Analysis And Evaluation of Address Arithmetic Capabilities in Custom DSP ArchtecturesSudarsanam, A. / Liao, S. / Devadas, S. et al. | 1997
- 293
-
System Level Fixed-point Design Based On An Interpolative ApproachWillems, M. / Bursgens, V. / Keding, H. / Grotker, T. / Meyr, H. et al. | 1997
- 299
-
ISDL: An Instruction Set Description Language For RetargetabilityHadjiyiannis, G. / Hanono, S. / Devadas, S. et al. | 1997
- 303
-
Generation Of Software Tools From Processor Descriptions For Hardware/software CodesignHartoog, M.R. / Rowson, J.A. / Reddy, P.D. / Desai, S. / Dunlop, D.D. / Harcourt, E.A. / Khullar, N. et al. | 1997
- 307
-
Education For The Deep Submicronage: Business As Usual?De Man, H. et al. | 1997
- 313
-
INFOPAD - An Experiment in System-Level Design and IntegrationBrodersen, R. W. et al. | 1997
- 315
-
Very Rapid Prototyping Of Wearable Computers: A Case Study Of Custom Versus Off-the-shelf Design MethodologiesSmailagic, A. / Siewiorek, D.P. / Martin, R. / Stivoric, J. et al. | 1997
- 321
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CAD At The Design-manufacturing InterfaceHeineken, H.T. / Khare, J. / Maly, W. / Nag, P.K. / Ouyang, C. / Pleskacz, W.A. et al. | 1997
- 327
-
CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell LibrariesGuruswamy, M. / Maziasz, R.L. / Dulitz, D. / Raman, S. / Chiluvuri, V. / Fernandez, A. / Jones, L.G. et al. | 1997
- 333
-
Developing A Concurrent Methodology For Standard-cell Library GenerationBaltus, D.G. / Varga, T. / Armstrong, R.C. / Duh, J. / Matheson, T.G. et al. | 1997
- 337
-
A Fast And Accurate Technique To Optimize Characterization Tables For Logic SynthesisCroix, J.F. / Wong, D.F. et al. | 1997
- 341
-
Limited Exception Modeling And Its Use In Presynthesis OptimizationJian Li, / Gupta, R.K. et al. | 1997
- 347
-
Potential-driven Statistical Ordering Of TransformationsInki Hong, / Kirovski, D. / Potkonjak, M. et al. | 1997
- 353
-
Synthesis Of Application Specific Programmable ProcessorsKyosun Kim, / Karri, R. / Potkonjak, M. et al. | 1997
- 359
-
Symbolic Evaluation Of Performance Models For Tradeoff VisualizationWalrath, J. / Vemuri, R. et al. | 1997
- 365
-
Power Macromodeling For High Level Power EstimationGupta, S. / Najm, F.N. et al. | 1997
- 371
-
Statistical Estimation Of The Cumulative Distribution Function For Power Dissipation In VLSI CircuitsChih-Shun Ding, / Qing Wu, / Cheng-Ta Hsieh, / Pedram, M. et al. | 1997
- 377
-
Statistical Estimation Of Average Power Dissipation In Sequential CircuitsLi-Pen Yuan, / Chin-Chi Teng, / Sung-Mo Kang, et al. | 1997
- 383
-
Vector Generation For Maximum Instantaneous Current Through Supply Lines For CMOS CircuitsKrstic, A. / Kwang-Ting Cheng, et al. | 1997
- 389
-
Fast Hardware/software Co-simulation For Virtual Prototyping And Trade-off AnalysisPasserone, C. / Lavagno, L. / Chiodo, M. / Sangiovanni-Vincentelli, A. et al. | 1997
- 395
-
Dynamic Communication Models in Embedded System Co-SimulationHines, K. / Borriello, G. et al. | 1997
- 401
-
Panel: Challenges in Worldwide IP Reuse with Embedded Tutorial: Applying VSIA Standards to System on Chip DesignGlover, R. / Inoue, T. / Teets, J. / Fairnbairn, D. et al. | 1997
- 403
-
Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic NetworksPant, P. / Vivek De, / Chatterjee, A. et al. | 1997
- 409
-
Transistor Sizing Issues And Tool For Multi-threshold Cmos TechnologyKao, J. / Chandrakasan, A. / Antoniadis, D. et al. | 1997
- 415
-
Architectural Exploration Using Verilog-based Power Estimation: A Case Study Of The IdctXanthopoulos, T. / Yaoi, Y. / Chandrakasan, A. et al. | 1997
- 421
-
A Power Estimation Framework For Designing Low Power Portable Video ApplicationsChi-Ying Tsui, / Kai-Keung Chan Qing Wu, / Chih-Shun Ding, / Pedram, M. et al. | 1997
- 425
-
An Investigation of Power Delay Trade-Offs on PowerPC CircuitsWang, Q. / Vrudhula, S. B. K. / Ganguly, S. et al. | 1997
- 425
-
An Investigation Of Power Delay Trade-offs On PowerpcQi Wang, / Vrudhula, S.B.K. / Ganguly, S. et al. | 1997
- 429
-
Power Management Techniques For Control-flow Intensive DesignsRaghunathan, A. / Dey, S. / Jha, N.K. / Wakabayashi, K. et al. | 1997
- 435
-
Low Energy Memory And Register Allocation Using Network FlowGebotys, C.H. et al. | 1997
- 441
-
Power-conscious High Level Synthesis Using Loop FoldingDaehong Kim, / Kiyoung Choi, et al. | 1997
- 446
-
Embedded Tutorial: The Future of Custom Cell Generation in Physical SynthesisLefebvre, M. / Marple, D. / Sechen, C. et al. | 1997
- 446
-
The Future Of Custom Cell Generation in Physical SynthesisLefebvre, M. / Marple, D. et al. | 1997
- 452
-
Clip: An Optimizing Layout Generator For Two-dimensional Cmos CellsGupta, A. / Hayes, J.P. et al. | 1997
- 456
-
An Efficient Transistor Folding Algorithm For Row-based Cmos Layout DesignJaewon Kim, / Kang, S.M. et al. | 1997
- 460
-
Technology Retargeting For Ic LayoutLakes, J. et al. | 1997
- 466
-
A Test Synthesis Approach To Reducing Ballast Dft OverheadChang, D. / Mike Tien-Chien Lee, / Marek-Sadowska, M. / Aikyo, T. / Kwang-Ting Cheng, et al. | 1997
- 472
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Starbist Scan Autocorrelated Random Pattern GenerationTsai, K.H. / Hellebrand, S. / Rajski, J. / Marek-Sadowska, M. et al. | 1997
- 478
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A Hybrid Algorithm For Test Point Selection For Scan-based BistHuan-Chih Tsai, / Kwang-Ting Cheng, / Chih-Jen Lin, / Bhawmik, S. et al. | 1997
- 484
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Panel: Hardware/Software Co-VerificationSmith, G. / Courtoy, M. / Kenefick, M. / Bailey, B. et al. | 1997
- 486
-
Design And Synthesis Of Array Structured Telecommunication Processing ApplicationsMeyer, W. / Seawright, A. / Tada, F. et al. | 1997
- 492
-
Rassp Virtual Prototyping Of Dsp SystemsHein, C. / Pridgen, J. / Kline, W. et al. | 1997
- 498
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A Parallel/serial Trade-off Methodology For Look-up Table Based DecodersSchneider, C. et al. | 1997
- 504
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High-level Power Modeling, Estimation, And OptimizationMacii, E. / Pedram, M. / Somenzi, F. et al. | 1997
- 504
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High-level power modeling, estimation, and optimisationMacii, E. / Pedram, M. / Somenzi, F. et al. | 1997
- 504
-
Embedded Tutorial: High-Level Power Modeling, Estimation, and OptimizationPedram, M. / De Micheli, G. / Macii, E. / Somenzi, F. et al. | 1997
- 512
-
A Network Flow Approach For Hierarchical Tree PartitioningMing-Ter Kuo, / Chung-Kuan Cheng, et al. | 1997
- 518
-
Multi-way Fpga Partitioning By Fully Exploiting Design HierarchyWen-Jong Fang, / Wu, A.C.-H. et al. | 1997
- 522
-
A Hierarchy-driven Fpga Partitioning methodKrupnova, H. / Abbara, A. / Saucier, G. et al. | 1997
- 526
-
Multilevel Hypergraph Partitioning: Application In Vlsi DomainKarypis, G. / Aggarwal, R. / Kumar, V. / Shekhar, S. et al. | 1997
- 530
-
Multilevel Circuit PartitioningAlpert, C.J. / Jen-Hsin Huang, / Kahng, A.B. et al. | 1997
- 534
-
Hierarchical Test Generation And Design For Testability Of ASPPs and ASIPsGhosh, L. / Raghunathan, A. / Jha, N.K. et al. | 1997
- 540
-
Frequency-domain Compatibility In Digital Filter BistGoodby, L. / Orailoglu, A. et al. | 1997
- 546
-
A Scheme For Integrated Controller-datapath Fault TestingNourani, M. / Carletta, J. / Papachristou, C. et al. | 1997
- 552
-
Panel: The Next Generation HDLSchulz, S. E. / Goering, R. / Collins, N. / Berry, G. et al. | 1997
- 553
-
Executable Workflows: A Paradigm For Collaborative Design On The InternetLavana, H. / Khetawat, A. / Brglez, F. / Kozminski, K. et al. | 1997
- 559
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Electronic Component Information Exchange (ECIX)Cottrell, D.R. et al. | 1997
- 564
-
Modeling Design Tasks And Tools - The Link Between Product And Flow Model -Schurmann, B. / Altmeyer, J. et al. | 1997
- 570
-
Hierarchical Sequence Compaction For Power EstimationMarculescu, R. / Marculescu, D. / Pedram, M. et al. | 1997
- 576
-
Profile-driven Program Synthesis For Evaluation Of System Power DissipationCheng-Ta Hsieh, / Pedram, M. et al. | 1997
- 582
-
Analytical Estimation Of Transition Activity From Word-level Signal StatisticsRamprasad, S. / Shanbhag, N.R. / Hajj, I.N. et al. | 1997
- 588
-
Wire Segmenting For Improved Buffer InsertionAlpert, C. / Devgan, A. et al. | 1997
- 594
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More Practical Bounded-skew Clock RoutingKahng, A.B. / Tsao, C.-W.A. et al. | 1997
- 600
-
An Efficient Approach To Multi-layer Layer Assignment With Application To Via MinimizationChin-Chih Chang, / Cong, J. et al. | 1997
- 604
-
Optimal Wire-sizing Function With Fringing Capacitance ConsiderationChung-Ping Chen, / Wong, D.F. et al. | 1997
- 608
-
Fault Simulation Under The Multiple Observation Time Approach Using Backward ImplicationsPomeranz, I. / Reddy, S.M. et al. | 1997
- 614
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Atpg For Heat Dissipation Minimization During Scan TestingSeongmoon Wang, / Gupta, S.K. et al. | 1997
- 620
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Automatic Generation Of Synchronous Test Patterns For Asynchronous CircuitsRoig, O. / Cortadella, J. / Peiia, M.A. / Pastor, E. et al. | 1997
- 626
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Panel: The Road Ahead in CPLD & FPGA Design MethodologyRohleder, R. / Birkner, J. / Faria, D. / Golson, S. et al. | 1997
- 627
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Analysis And Justification Of A Practical 2 L/2-d Capacitance Extraction MethodologyCong, J. / Lei Het, / Kahng, A.B. / Noice, D. / Shirali, N. / Yen, S.H.-C. et al. | 1997
- 627
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Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction MethodologyCong, J. / He, L. / Kahng, A. B. / Noice, D. et al. | 1997
- 633
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Accurate And Efficient Macromodel Of Submicron Digital Standard CellsForzan, C. / Franzini, B. / Guardiani, C. et al. | 1997
- 638
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Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip DesignChen, H.H. / Ling, D.D. et al. | 1997
- 644
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Fpga Synthesis With Retiming And Pipelining For Clock Period Minimization Of Sequential CircuitsCong, J. / Chang Wu, et al. | 1997
- 650
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Technology-dependent Transformations For Low-power SynthesisPanda, R. / Najm, F.N. et al. | 1997
- 656
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Low Power Fpga Design - A Re-engineering ApproachChau-Shen Chen, / TingTing Hwang, / Liu, C.L. et al. | 1997
- 662
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Post-layout Logic Restructuring For Performance OptimizationYi-Min Jiang, / Krstic, A. / Kwang-Ting Cheng, / Marek-Sadowska, M. et al. | 1997
- 666
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Layout Driven Re-synthesis For Low Power Consumption LsisMurofushi, M. / Ishioka, T. / Murakata, M. / Mitsuhashi, T. et al. | 1997
- 670
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Embedded Tutorial: Overview of Microelectromechanical Systems and Design ProcessesTang, W. C. et al. | 1997
- 670
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Overview Of Microelectromechanical Systems And Design ProcessesTang, W.C. et al. | 1997
- 674
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Cad And Foundries For MicrosystemsKaraml, J.M. / Courtoisl, B. / Boutaminel, H. / Drake, P. / Poppe, A. / Szekely, V. / Rencz, M. / Hofmann, K. / Glesner, M. et al. | 1997
- 680
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Structured Design Of Microelectromechanical SystemsMukherjee, T. / Fedder, G.K. et al. | 1997
- 686
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Algorithms For Coupled Domain Mems SimulationAluru, N. / White, J. et al. | 1997
- 691
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A Hardware/Software Partitioner Using a Dynamically Determined GranularityHenkel, J. / Ernst, R. et al. | 1997
- 691
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A Hardware/software Partitioned Using A Dynamically Determined GranularityHenkel, J. / Ernst, R. et al. | 1997
- 697
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System-level Synthesis Of Low-power Hard Real-time SystemsKirovski, D. / Potkonjak, M. et al. | 1997
- 703
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Cosyn: Hardware-software Co-synthesis Of Embedded SystemsDave, B.P. / Lakshminarayana, G. / Jha, N.K. et al. | 1997
- 709
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Data-flow Assisted Behavioral Partitioning For Embedded SystemsAgrawal, S. / Gupta, R.K. et al. | 1997
- 713
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Hardware/software Partitioning And PipeliningBakshi, S. / Gajski, D.D. et al. | 1997
- 717
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Chip Parasitic Extraction And Signal Integrity VerificationDai, W.W.-M. et al. | 1997
- 717
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Embedded Tutorial: Chip Parasitic Extraction and Signal Integrity VerificationDai, W. W.-M. et al. | 1997
- 720
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Panel: Noise and Signal Integrity in Deep Submicron DesignGuthrie, W. E. / Pedram, M. / Chadha, R. / Cong, J. et al. | 1997
- 722
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Designing High Performance Cmos Microprocessors Using Full Custom TechniquesGrundmann, W.J. / Dobberpuhl, D. / Allmon, R.L. / Rethman, N.L. et al. | 1997
- 728
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Disjunctive Partitioning And Partial Iterative Squaring: An Effective Approach For Symbolic Traversal Of Large CircuitsCabodi, G. / Camurati, P. / Lavagno, L. / Quer, S. et al. | 1997
- 734
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An Efficient Assertion Checker For Combinational PropertiesHasteert, G. / Mathur, A. / Banerjee, P. et al. | 1997
- 740
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Toward Formalizing A Validation Methodology Using Simulation CoverageGupta, A. / Malik, S. / Ashar, P. et al. | 1997
- 746
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Algorithms for Large-Scale Flat PlacementVygen, J. et al. | 1997
- 746
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Algorithm For Large-scale Flat PlacementVygen, J. et al. | 1997
- 752
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Quadratic Placement RevisitedAlpert, C.J. / Chan, T. / Huang, D.J.-H. / Markov, I. / Yan, K. et al. | 1997
- 758
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Unification Of Budgeting And PlacementSarrafzadeh, M. / Knol, D. / Tellez, G. et al. | 1997
- 762
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