Temperature Dependence of Avalanche Multiplication in Spiked Electric Fields (Englisch)
- Neue Suche nach: van den Berg, M. R.
- Neue Suche nach: Nanver, L. K.
- Neue Suche nach: Slotboom, J. W.
- Neue Suche nach: IEEE
- Neue Suche nach: van den Berg, M. R.
- Neue Suche nach: Nanver, L. K.
- Neue Suche nach: Slotboom, J. W.
- Neue Suche nach: IEEE
In:
International electron devices meeting
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79-82
;
2000
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:Temperature Dependence of Avalanche Multiplication in Spiked Electric Fields
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Beteiligte:
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Kongress:International electron devices meeting ; 2000 ; San Francisco, CA
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.2000
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Format / Umfang:4 pages
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Anmerkungen:IEEE cat no 00CH37138 and 00CB37138
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)| 2000
- 1_5
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Author index| 2000
- 3
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Microsystems for the automotive industryMarek, J. / Illing, M. et al. | 2000
- 9
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III-V nitride-based LEDs and lasers: Current status and future opportunitiesNakamura, S. et al. | 2000
- 12
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Prospects for quantum computingDiVincenzo, D.P. et al. | 2000
- 19
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Band diagram and carrier conduction mechanism in ZrO/sub 2//Zr-silicate/Si MIS structure fabricated by pulsed-laser-ablation depositionYamaguchi, T. / Satake, H. / Fukushima, N. / Toriumi, A. et al. | 2000
- 19
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Band Diagram and Carrier Conduction Mechanism in ZrO~2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation DepositionYamaguchi, T. / Satake, H. / Fukushima, N. / Toriumi, A. / IEEE et al. | 2000
- 23
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Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applicationsManchanda, L. / Green, M.L. / van Dover, R.B. / Morris, M.D. / Kerber, A. / Hu, Y. / Han, J.-P. / Silverman, P.J. / Sorsch, T.W. / Weber, G. et al. | 2000
- 27
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MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO~2 and Zr Silicate Gate DielectricsLee, C. H. / Luan, H. F. / Bai, W. P. / Lee, S. J. / Jeon, T. S. / Senzaki, Y. / Roberts, D. / Kwong, D. L. / IEEE et al. | 2000
- 27
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MOS characteristics of ultra thin rapid thermal CVD ZrO/sub 2/ and Zr silicate gate dielectricsLee, C.H. / Luan, H.F. / Bai, W.P. / Lee, S.J. / Jeon, T.S. / Senzaki, Y. / Roberts, D. / Kwong, D.L. et al. | 2000
- 31
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High Quality Untra Thin CVD HfO~2 Gate Stack with Poly-Si Gate ElectrodeLee, S. J. / Luan, H. F. / Bai, W. P. / Lee, C. H. / Jeon, T. S. / Senzaki, Y. / Roberts, D. / Kwong, D. L. / IEEE et al. | 2000
- 31
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High quality ultra thin CVD HfO/sub 2/ gate stack with poly-Si gate electrodeLee, S.J. / Luan, H.F. / Bai, W.P. / Lee, C.H. / Jeon, T.S. / Senzaki, Y. / Roberts, D. / Kwong, D.L. et al. | 2000
- 35
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MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectricsKang, L. / Onishi, K. / Jeon, Y. / Byoung Hun Lee, / Kang, C. / Wen-Jie Qi, / Nieh, R. / Gopalan, S. / Choi, R. / Lee, J.C. et al. | 2000
- 35
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MOSFET Devices with Polysilicon on Single-Layer HfO~2 High-K DielectricsKang, L. / Onishi, K. / Jeon, Y. / Lee, B. H. / Kang, C. / Qi, W.-J. / Nieh, R. / Gopalan, S. / Choi, R. / Lee, J. C. et al. | 2000
- 39
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Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 /spl Aring/-12 /spl Aring/)Byoung Hun Lee, / Choi, R. / Kang, L. / Gopalan, S. / Nieh, R. / Onishi, K. / Jeon, Y. / Wen-Jie Qi, / Kang, C. / Lee, J.C. et al. | 2000
- 39
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Characteristics of TaN Gate MOSFET with Ultrathin Hafnium Oxide (8Angstrom-12Angstrom)Lee, B. H. / Choi, R. / Kang, L. / Gopalan, S. / Nieh, R. / Onishi, K. / Jeon, Y. / Qi, W.-J. / Kang, C. S. / Lee, J. C. et al. | 2000
- 45
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30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delaysChau, R. / Kavalieros, J. / Roberds, B. / Schenker, R. / Lionberger, D. / Barlage, D. / Doyle, B. / Arghavani, R. / Murthy, A. / Dewey, G. et al. | 2000
- 49
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45-nm gate length CMOS technology and beyond using steep haloWakabayashi, H. / Ueki, M. / Narihiro, M. / Fukai, T. / Ikezawa, N. / Matsuda, T. / Yoshida, K. / Takeuchi, K. / Ochiai, Y. / Mogami, T. et al. | 2000
- 53
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SALVO process for sub-50 nm low-V/sub T/ replacement gate CMOS with KrF lithographyChang, C.-P. / Vuang, H.-H. / Baker, M.R. / Pai, C.S. / Klemens, F.P. / Miner, J.F. / Mansfield, W.M. / Kleiman, R.N. / Kornbllit, A. / Baumann, F.H. et al. | 2000
- 53
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SALVO Process for Sub-50 nm Low-V~T Replacement Gate CMOS with KrF LithographyChang, C.-P. / Vuong, H.-H. / Baker, M. R. / Pai, C. S. / Klemens, R. P. / Miner, J. F. / Mansfield, W. / Kleiman, R. / Kornblit, A. / Baumann, F. et al. | 2000
- 57
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Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regimeKedzierski, J. / Xuan, P. / Anderson, E.H. / Bokor, J. / Tsu-Jae King, / Chenming Hu, et al. | 2000
- 61
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50-nm vertical sidewall transistors with high channel doping concentrationsSchulz, T. / Rosner, W. / Risch, L. / Langmann, U. et al. | 2000
- 65
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50 nm Vertical Replacement-Gate (VRG) pMOSFETsSang-Hyun Oh, / Hergenrother, J.M. / Nigam, T. / Monroe, D. / Klemens, F.P. / Kornblit, A. / Mansfield, W.M. / Baker, M.R. / Barr, D.L. / Baumann, F.H. et al. | 2000
- 71
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Vertical power-MOSFETs with local channel dopingFink, C. / Schulze, J. / Eisele, I. / Hansch, W. / Werner, W. / Kanert, W. et al. | 2000
- 75
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SOA improvement by a double RESURF LDMOS technique in a power IC technologyParthasarathy, V. / Khemka, V. / Zhu, R. / Bose, A. et al. | 2000
- 79
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Temperature dependence of avalanche multiplication in spiked electric fieldsvan den Berg, M.R. / Nanver, L.K. / Slotboom, J.W. et al. | 2000
- 83
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Electrical-thermal coupling mechanism on operating limit of LDMOS transistorChung, Y.S. / Baird, B. et al. | 2000
- 87
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Reduction of metal-semiconductor contact resistance by embedded nanocrystalsNarayanan, V. / Liu, Z. / Shen, Y.-M.N. / Kim, M. / Kan, E.C. et al. | 2000
- 93
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Simulation of Si-SiO~2 Defect Generation in CMOS Chips: from Atomistic Structure to Chip Failure Rates (Invited)Hess, K. / Haggag, A. / McMahon, W. / Fischer, B. / Cheng, K. / Lee, J. / Lyding, J. / IEEE et al. | 2000
- 93
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Simulation of Si-SiO/sub 2/ defect generation in CMOS chips: from atomistic structure to chip failure ratesHess, K. / Haggag, A. / McMahon, W. / Fischer, B. / Cheng, K. / Lee, J. / Lyding, J. et al. | 2000
- 97
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Impact ionization and photon emission in MOS capacitors and FETsPalestri, P. / Pavesi, M. / Rigolli, P. / Selmi, L. / Dalla Serra, A. / Abramo, A. / Widdershoven, F. / Sangiorgi, E. et al. | 2000
- 101
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An accurate, experimentally verified electron minority carrier mobility model for Si and SiGeJungemann, C. / Heinemann, B. / Tittelbach-Helmrich, K. / Meinerzhagen, B. et al. | 2000
- 105
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Enhanced secondary electron injection in novel SiGe flash memory devicesKencke, D.L. / Xin Wang, / Ouyang, Q. / Mudanai, S. / Tasch, A. / Banerjee, S.K. et al. | 2000
- 109
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Efficiency and stochastic error of Monte Carlo device simulationsJungemann, C. / Meinerzhagen, B. et al. | 2000
- 113
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Ensemble Monte Carlo/molecular dynamics simulation of gate remote charge effects in small geometry MOSFETsKawashima, I. / Kamakura, Y. / Taniguchi, K. et al. | 2000
- 119
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Optimizing the Electromigration Performance of Copper Interconnects (Invited)Besser, P. / Marathe, A. / Zhao, L. / Herrick, M. / Capasso, C. / Kawasaki, H. / IEEE et al. | 2000
- 119
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Optimizing the electromigration performance of copper interconnectsBesser, P. / Marathe, A. / Zhao, L. / Herrick, M. / Capasso, C. / Kawasaki, H. et al. | 2000
- 123
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Improvement of thermal stability of via resistance in dual damascene copper interconnectionOshima, T. / Tamaru, T. / Ohmori, K. / Aoki, H. / Ashihara, H. / Saito, T. / Yamaguchi, H. / Miyauchi, M. / Torii, K. / Murata, J. et al. | 2000
- 127
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ESD protection scheme using CMOS compatible vertical bipolar transistor for 130 nm CMOS generationOkushima, M. / Noguchi, K. / Sawahata, K. / Suzuki, H. / Kuroki, S. / Koyama, S. / Ando, K. / Ikezawa, N. et al. | 2000
- 131
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Reliability issues for silicon-on-insulatorBolam, R. / Shahidi, G. / Assaderaghi, F. / Khare, M. / Mocuta, A. / Hook, T. / Wu, E. / Leobandung, E. / Voldman, S. / Badami, D. et al. | 2000
- 131
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Reliability Issues for Silicon-on-Insulator (Invited)Bolam, R. / Shahidi, G. / Assaderaghi, F. / Khare, M. / Mocuta, A. / Hook, T. / Wu, E. / Leobandung, E. / Voldman, S. / Badami, D. et al. | 2000
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Hot carrier reliability for 0.13 /spl mu/m CMOS technology with dual gate oxide thicknessLin, C. / Biesemans, S. / Han, L.K. / Houlihan, K. / Schiml, T. / Schruefer, K. / Wann, C. / Chen, J. / Mahnkopf, R. et al. | 2000
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Hot Carrier Reliability for 0.13mum CMOS Technology with Dual Gate Oxide ThicknessLin, C. / Biesmann, S. / Han, L. K. / Houlihan, K. / Schiml, T. / Schruefer, K. / Wann, C. / Chen, J. / Mahnkopf, R. / IEEE et al. | 2000
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Valence-band tunneling enhanced hot carrier degradation in ultrathin oxide nMOSFETsTsai, C.W. / Gu, S.H. / Chiang, L.P. / Wang, T. / Liu, Y.C. / Huang, L.S. / Wang, M.C. / Hsia, L.C. et al. | 2000
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COM2 SiGe modular BiCMOS technology for digital, mixed-signal, and RF applicationsCarroll, M. / Ivanov, T. / Kuehne, S. / Chu, J. / King, C. / Frei, M. / Mastrapasqua, M. / Johnson, R. / Ng, K. / Moinian, S. et al. | 2000
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A 73GHz f~T 0.18mum RF-SiGe BiCMOS Technology Considering Thermal Budget Trade-off and with Reduced Boron-Spike Effect on HBT CharacteristicsHashimoto, T. / Sato, F. / Aoyama, T. / Suzuki, H. / Yoshida, H. / Fujii, H. / Yamazaki, T. / IEEE et al. | 2000
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A 73 GHz f/sub T/ 0.18 /spl mu/m RF-SiGe BiCMOS technology considering thermal budget trade-off and with reduced boron-spike effect on HBT characteristicsHashimoto, T. / Sato, F. / Aoyama, T. / Suzuki, H. / Yoshida, H. / Fujii, H. / Yamazaki, T. et al. | 2000
- 153
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Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologiesZurcher, P. / Alluri, P. / Chu, P. / Duvallet, A. / Happ, C. / Henderson, R. / Mendonca, J. / Kim, M. / Petras, M. / Raymond, M. et al. | 2000
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Integration of Thin Film MIM Capacitors and Resistors into Copper Metalization Based RF-CMOS and Bi-CMOS TechnologiesZurcher, P. / Alluri, P. / Chu, P. / Duvallet, A. / Happ, C. / Henderson, R. / Mendonca, J. / Kim, M. / Petras, M. / Raymond, M. et al. | 2000
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A High Reliability Metal Insulator Metal Capacitor for 0.18 mum Copper TechnologyArmacost, M. / Augustin, A. / Felsner, P. / Feng, Y. / Friese, G. / Heidenreich, J. / Hueckel, G. / Prigge, O. / Stein, K. / IEEE et al. | 2000
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A high reliability metal insulator metal capacitor for 0.18 /spl mu/m copper technologyArmacost, M. / Augustin, A. / Felsner, P. / Feng, Y. / Friese, G. / Heidenreich, J. / Hueckel, G. / Prigge, O. / Stein, K. et al. | 2000
- 161
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Three dimensional CMOS integrated circuits on large grain polysilicon filmsChan, V.W.C. / Chan, P.C.H. / Chan, M. et al. | 2000
- 165
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Three-dimensional shared memory fabricated using wafer stacking technologyLee, K.W. / Nakamura, T. / Ono, T. / Yamada, Y. / Mizukusa, T. / Hashimoto, H. / Park, K.T. / Kurino, H. / Koyanagi, M. et al. | 2000
- 169
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Novel Silicon Epitaxy for Advanced MOSFET Devices (Invited)Neudeck, G. / Su, T.-C. / Denton, J. / IEEE et al. | 2000
- 169
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Novel silicon epitaxy for advanced MOSFET devicesNeudeck, G.W. / Tai-Chi Su, / Denton, J.P. et al. | 2000
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InP HEMT Amplifier Development for G-band (140-220 GHz) Applications (Invited)Lai, R. / Barsky, M. / Grundbacher, R. / Liu, P. H. / Chin, T. P. / Nishimoto, M. / Elmajarian, R. / Rodriguez, R. / Tran, L. / Gutierrez, A. et al. | 2000
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InP HEMT amplifier development for G-band (140-220 GHz) applicationsLai, R. / Barsky, M. / Grundbacher, R. / Liu, P.H. / Chin, T.P. / Nishimoto, M. / Elmajarian, R. / Rodriguez, R. / Tran, L. / Gutierrez, A. et al. | 2000
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Abrupt junction InP/GaAsSb/InP double heterojunction bipolar transistors with F/sub T/ as high as 250 GHz and BV/sub CEO/>6 VDvorak, M.W. / Pitts, O.J. / Watkins, S.P. / Bolognesi, C.R. et al. | 2000
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Abrupt Junction InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with F~T as High as 250 GHz and BV~C~E~O>6VDvorak, M. / Pitts, O. / Watkins, S. / Bolognesi, C. / IEEE et al. | 2000
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Metamorphic HFETs on GaAs with InP-subchannels for device performance improvementsGassler, C. / Ziegler, V. / Wolk, C. / Deufel, R. / Berlec, F.-J. / Kab, N. / Kohn, E. et al. | 2000
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Simulation of InAlAs/InGaAs high electron mobility transistors with a single set of physical parametersQuay, R. / Palankovski, V. / Chertouk, M. / Leuther, A. / Selberherr, S. et al. | 2000
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Reliability study of parasitic source and drain resistances of InP-based HEMTsSuemitsu, T. / Fukai, Y.K. / Sugiyama, H. / Watanabe, K. / Yokoyama, H. et al. | 2000
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Low temperature poly-Si TFT-electrophoretic displays (TFT-EPDs) with four level gray scaleInoue, S. / Sadao, K. / Ozawa, T. / Kobashi, Y. / Kawai, H. / Kitagawa, T. / Shimoda, T. et al. | 2000
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High density, low parasitic direct integration by fluidic self assembly (FSA)Smith, J.S. et al. | 2000
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High Density, Low Parasitic Direct Integration by Fluidic Self Assembly (FSA) (Invited)Smith, J. / IEEE et al. | 2000
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A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structureOhgata, K. / Mishima, Y. / Sasaki, N. et al. | 2000
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Selective single-crystalline-silicon growth at the pre-defined active regions of TFTs on a glass by a scanning CW laser irradiationHara, A. / Takeuchi, F. / Sasaki, N. et al. | 2000
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A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealingJae-Hong Jeon, / Min-Cheol Lee, / Kee-Chan Park, / Sang-Hoon Jung, / Min-Koo Han, et al. | 2000
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Reliability of low temperature poly-Si TFT employing counter-doped lateral body terminalYoo, J.S. / Kim, C.H. / Lee, M.C. / Han, M.K. / Kim, H.J. et al. | 2000
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80 nm Poly-Silicon Gated n-FETs with Ultra-Thin Al~2O~3 Gate Dielectric for ULSI ApplicationsBuchanan, D. / Gusev, E. / Cartier, E. / Okorn-Schmidt, H. / Rim, K. / Gribelyuk, M. / Mocuta, A. / Ajmera, A. / Copel, M. / Guha, S. et al. | 2000
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80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applicationsBuchanan, D.A. / Gusev, E.P. / Cartier, E. / Okorn-Schmidt, H. / Rim, K. / Gribelyuk, M.A. / Mocuta, A. / Ajmera, A. / Copel, M. / Guha, S. et al. | 2000
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Extending gate dielectric scaling limit by NO oxynitride: design and process issues for sub-100 nm technologyFujiwara, M. / Takayanagi, M. / Shimizu, T. / Toyoshima, Y. et al. | 2000
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Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOSFung, S.K.H. / Zamdmer, N. / Oldiges, P.J. / Sleight, J. / Mocuta, A. / Sherony, M. / Lo, S.-H. / Joshi, R. / Chuang, C.T. / Yang, I. et al. | 2000
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Controlling Floating-Body Effects for 0.13mum and 0.10mum SOI CMOSFung, S. K. H. / Zamdmer, N. / Oldiges, P. / Sleight, J. / Mocuta, A. / Sherony, M. / Lo, S.-H. / Joshi, R. / Chuang, C. T. / Yang, I. et al. | 2000
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CMOS device scaling beyond 100 nmSong, S. / Yi, J.H. / Kim, W.S. / Lee, J.S. / Fujihara, K. / Kang, H.K. / Moon, J.T. / Lee, M.Y. et al. | 2000
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CMOS Device Scaling Beyond 100nm (Invited)Song, S. / Yi, J. H. / Kim, W. S. / Lee, J. S. / Fujihara, K. / Kang, H. K. / Moon, J. T. / Lee, M. Y. / IEEE et al. | 2000
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80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN processSayama, H. / Nishida, Y. / Oda, H. / Tsuchimoto, J. / Umeda, H. / Teramoto, A. / Eikyu, K. / Inoue, Y. / Inuishi, M. et al. | 2000
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Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth techniqueHokazono, A. / Ohuchi, K. / Miyano, K. / Mizushima, I. / Tsunashima, Y. / Toyoshima, Y. et al. | 2000
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Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor designIto, S. / Namba, H. / Yamaguchi, K. / Hirata, T. / Ando, K. / Koyama, S. / Kuroki, S. / Ikezawa, N. / Suzuki, T. / Saitoh, T. et al. | 2000
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Current and future low-k dielectrics for Cu interconnectsKikkawa, T. et al. | 2000
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Current and Future Low-k Dielectrics for Cu Interconnects (Invited)Kikkawa, T. / IEEE et al. | 2000
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Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic filmKinoshita, K. / Tada, M. / Usami, T. / Hiroi, M. / Tonegawa, T. / Shiba, K. / Onodera, T. / Tagami, M. / Saitoh, S. / Hayashi, Y. et al. | 2000
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Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnectsTing-Yen Chiang, / Banerjee, K. / Saraswat, K.C. et al. | 2000
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A high reliability copper dual-damascene interconnection with direct-contact via structureUeno, K. / Suzuki, M. / Matsumoto, A. / Motoyama, K. / Tonegawa, T. / Ito, N. / Arita, K. / Tsuchiya, Y. / Wake, T. / Kubo, A. et al. | 2000
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V~t~h Fluctuation Induced by Statistical Variation of Pocket Dopant ProfileTanaka, T. / Usuki, T. / Futatsugi, T. / Momiyama, Y. / Sugii, T. / IEEE et al. | 2000
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Role of long-range and short-range Coulomb potentials in threshold characteristics under discrete dopants in sub-0.1 /spl mu/m Si-MOSFETsSano, N. / Matsuzawa, K. / Mukai, M. / Nakayama, N. et al. | 2000
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Role of Long-Range and Short-Range Coulomb Potentials in Threshold Characteristics under Discrete Dopants in Sub-0.1 mum Si-MOSFETsSano, N. / Matsuzawa, K. / Mukai, M. / Nakayama, N. / IEEE et al. | 2000
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Random telegraph signal amplitudes in sub 100 nm (decanano) MOSFETs: a 3D 'Atomistic' simulation studyAsenov, A. / Balasubramaniam, R. / Brown, A.R. / Davies, J.H. / Saini, S. et al. | 2000
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Random Telegraph Signal Amplitudes in Sub 100 nm (Decaneno) MOSFETs: A 3D `Atomistic' Simulation StudyAsenov, A. / Balasubramaniam, R. / Brown, A. / Davies, J. / Saini, S. / IEEE et al. | 2000
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A full-band Monte Carlo model for silicon nanoscale devices with a quantum mechanical correction of the potentialTsuchiya, H. / Fischer, B. / Hess, K. et al. | 2000
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Quantum effects in MOSFETs: use of an effective potential in 3D Monte Carlo simulation of ultra-short channel devicesFerry, D.K. / Akis, R. / Vasileska, D. et al. | 2000
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Quantum effects along the channel of ultra-scaled Si-based MOSFETs?Wanqiang Chen, / Qiqing Ouyang, / Register, L.F. / Banerjee, S.K. et al. | 2000
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Single-electron pass-transistor logic: operation of its elemental circuitOno, Y. / Takahashi, Y. et al. | 2000
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A Single-Electron Shut-Off Transistor for Scalable Sub-0.1-mum MemoryOsabe, T. / Ishii, T. / Mine, T. / Murai, F. / Yano, K. / IEEE et al. | 2000
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A single-electron shut-off transistor for a scalable sub-0.1 /spl mu/m memoryOsabe, T. / Ishii, T. / Mine, T. / Murai, F. / Yano, K. et al. | 2000
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Engineering variations: towards practical single-electron (few-electron) memoryIshii, T. / Osabe, T. / Mine, T. / Murai, F. / Yano, K. et al. | 2000
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Characteristics of p-channel Si nano-crystal memoryKwangseok Han, / Ilgweon Kim, / Shungcheol Shin, et al. | 2000
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Non-volatile Si quantum memory with self-aligned doubly-stacked dotsOhba, R. / Sugiyama, N. / Uchida, K. / Koga, J. / Toriumi, A. et al. | 2000
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A novel FET-type ferroelectric memory with excellent data retention characteristicsSung-Min Yoon, / Ishiwara, H. et al. | 2000
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Substrate enhanced degradation of CMOS devicesDriussi, F. / Esseni, D. / Selmi, L. / Piazza, F. et al. | 2000
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Degradation of ultra-thin gate oxides accompanied by hole direct tunneling: can we keep long-term reliability of p-MOSFETs?Deguchi, K. / Uno, S. / Ishida, A. / Hirose, T. / Kamakura, Y. / Taniguchi, K. et al. | 2000
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Experimental and Numerical Analysis of the Quantum YieldIelmini, D. / Spinelli, A. / Lacaita, A. / DiMaria, D. / Ghidini, G. / IEEE et al. | 2000
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Experimental and numerical analysis of the quantum yield [MOSFETs]Ielmini, D. / Spinelli, A.S. / Lacaita, A.L. / DiMaria, D.J. / Ghidini, G. et al. | 2000
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Anomalous low temperature charge leakage mechanism in ULSI flash memoriesLam, C. / Sunaga, T. / Igarashi, Y. / Ichinose, M. / Kitamura, K. / Willets, C. / Johnson, J. / Mittl, S. / White, F. / Tang, H. et al. | 2000
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Deuterium effect on interface states and SILC generation in CHE stress conditions: A comparative studyEsseni, D. / Bude, J.D. / Selmi, L. et al. | 2000
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Highly reliable gate oxide under Fowler-Nordheim electron injection by deuterium pyrogenic oxidation and deuterated poly-Si depositionMitani, Y. / Satake, H. / Itoh, H. / Toriumi, A. et al. | 2000
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An Orthogonal 6F^2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAMRadens, C. / Kudelka, S. / Nesbit, L. / Malik, R. / Dyer, T. / Dubuc, C. / Joseph, T. / Seitz, M. / Clevenger, L. / Arnold, N. et al. | 2000
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An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAMRadens, C.J. / Kudelka, S. / Nesbit, L. / Malik, R. / Dyer, T. / Dubuc, C. / Joseph, T. / Seitz, M. / Clevenger, L. / Arnold, N. et al. | 2000
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Highly Manufacturable 4Gb DRAM Using 0.11mum DRAM TechnologyJeong, H. S. / Yang, W. S. / Hwang, Y. S. / Cho, C. H. / Park, S. / Ahn, S. J. / Chun, Y. S. / Shin, S. H. / Song, S. H. / Lee, J. Y. et al. | 2000
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Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technologyJeong, H.S. / Yang, W.S. / Hwang, Y.S. / Cho, C.H. / Park, S. / Ahn, S.J. / Chun, Y.S. / Shin, S.H. / Song, S.H. / Lee, J.Y. et al. | 2000
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Diagonal Layout & Surface Strap Trench (DST) cellKajiyama, T. / Aochi, H. / Asao, Y. / Morikado, M. / Koyama, H. / Sugimae, K. / Ishibashi, S. / Hosotani, K. / Kito, M. / Sato, A. et al. | 2000
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Diagonal layout and surface strap trench (DST) cell [embedded DRAMs]Kajiyama, T. / Aochi, H. / Asao, Y. / Morikado, M. / Koyama, H. / Sugimae, K. / Ishibashi, S. / Hosotani, K. / Kito, M. / Sato, A. et al. | 2000
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A Novel Bit-Line Process using Poly-Si Masked Dual-Damascene (PMDD) for 0.13mum DRAMs and BeyondMiyashita, T. / Nitta, H. / Nomura, H. / Nakajima, K. / Sakata, A. / Katata, T. / Mizutani, T. / Minakata, H. / Tanaka, M. / Tomita, H. et al. | 2000
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A novel bit-line process using poly-Si masked dual-damascene (PMDD) for 0.13 /spl mu/m DRAMs and beyondMiyashita, T. / Nitta, H. / Nomura, H. / Nakajima, K. / Sakata, A. / Mizutani, T. / Minakata, H. / Tanaka, M. / Tomita, H. / Kurahashi, T. et al. | 2000
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A Fully Working 0.14mum DRAM Technology with Polymetal (W/WNx/Poly-Si) GateJung, J.-W. / Lee, S.-W. / Sung, Y.-G. / Lee, B.-H. / Choi, J.-H. / Lee, B.-J. / Park, R.-H. / Han, S.-B. / IEEE et al. | 2000
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A fully working 0.14 /spl mu/m DRAM technology with polymetal (W/WN/sub x//poly-Si) gateJong-Wan Jung, / Seok-Woo Lee, / Yong-Gyu Sung, / Byung-Hak Lee, / Jun-Ho Choi, / Bong-Jae Lee, / Rae-Hak Park, / Sang-Beom Han, et al. | 2000
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Novel capacitor technology for high density stand-alone and embedded DRAMsYeong Kwan Kim, / Seung Hwan Lee, / Sung Je Choi, / Hong Bae Park, / Young Dong Seo, / Kwang Hyun Chin, / Dongchan Kim, / Jae Soon Lim, / Wan Don Kim, / Kab Jin Nam, et al. | 2000
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A 50-W AlGaN/GaN HEMT amplifierWu, Y.-F. / Chavarkar, P.M. / Moore, M. / Parikh, P. / Keller, B.P. / Mishra, U.K. et al. | 2000
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Novel high drain breakdown voltage AlGaN/GaN HFETs using selective thermal oxidation processMasato, H. / Ikeda, Y. / Matsuno, T. / Inoue, K. / Nishii, K. et al. | 2000
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Characteristics of AlGaN/GaN HEMT devices with SiN passivationJong-Soo Lee, / Vescan, A. / Wieszt, A. / Dietrich, R. / Leier, H. / Young-Se Kwon, et al. | 2000
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Microwave performance of AlGaN/GaN metal insulator semiconductor field effect transistorsChumbes, E.M. / Smart, J.A. / Prunty, T. / Shealy, J.R. et al. | 2000
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Diagnosis of trapping phenomena in GaN MESFETsMeneghesso, G. / Chini, A. / Zanoni, E. / Manfredi, M. / Pavesi, M. / Boudart, B. / Gaquiere, C. et al. | 2000
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A low-distortion 230 W GaAs power FP-HFET operated at 22 V for cellular base stationMatsunaga, K. / Ishikura, K. / Takenaka, I. / Contrata, W. / Wakejima, A. / Ota, K. / Kanamori, M. / Kuzuhara, M. et al. | 2000
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Mechanically temperature-compensated flexural-mode micromechanical resonatorsWan-Thai Hsu, / Clark, J.R. / Nguyen, C.T.-C. et al. | 2000
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Development of a wide tuning range MEMS tunable capacitor for wireless communication systemsJun Zou, / Chang Liu, / Schutt-Aine, J. / Jinghong Chen, / Sung-Mo Kang, et al. | 2000
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An active microelectronic transducer for enabling label-free miniaturized chemical sensorsPerkins, F.K. / Fertig, S.J. / Brown, K.A. / McCarthy, D. / Tender, L.M. / Peckerar, M.C. et al. | 2000
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Organic-based transducer for low-cost charge detection in aqueous mediaBartic, C. / Campitelli, A. / Baert, K. / Suls, J. / Borghs, S. et al. | 2000
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CMOS-Only Sensors and Manipulators for Micro-organism (Invited)Medoro, G. / Manaresi, N. / Tartagni, M. / Guerrieri, R. / IEEE et al. | 2000
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CMOS-only sensors and manipulators for microorganismsMedoro, G. / Manaresi, N. / Tartagni, M. / Guerrieri, R. et al. | 2000
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Fingerprint imager based on a-Si:H active-matrix photo-diode arraysLan, J. / Cole, A. / VanZandt, J. / Dickinson, A. / van de Ven, F. / Bird, N. / Badano, A. / Kanicki, J. et al. | 2000
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Low operation voltage high integrated field emitter arrays by transfer metal mold technique using ultra precision machining and super microelectroplating technologyNakamoto, M. / Fukuda, K. / Inoue, A. / Takahashi, F. / Honda, S. et al. | 2000
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Ultra shallow junction profilingVandervorst, W. / Clarysse, T. / Duhayon, N. / Eyben, P. / Hantschel, T. / Xu, M. / Janssens, T. / de Witte, H. / Conard, T. / Deleu, J. et al. | 2000
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Ultra Shallow Junction Profiling (Invited)Vandervorst, W. / Clarysse, T. / Duhayon, N. / Eyben, P. / Hantschel, T. / Xu, M. / Janssens, T. / De Witte, H. / Conrad, T. / Deleu, J. et al. | 2000
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Low thermal budget elevated source/drain technology utilizing novel solid phase epitaxy and selective vapor phase etchingMiyano, K. / Mizushima, I. / Hokazono, A. / Ohuchi, K. / Tsunashima, Y. et al. | 2000
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Low temperature (800/spl deg/C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOSGannavaram, S. / Pesovic, N. / Ozturk, C. et al. | 2000
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Low Temperature (Gannavaram, S. / Pesovic, N. / Ozturk, M. C. / IEEE et al. | 2000
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Laser thermal annealed SSR well prior to epi-channel growth (LASPE) for 70 nm nFETSJung-Ho Lee, / Jeongyoub Lee, / Somit Talwar, / Yun Wang, / Daehee Weon, / Seungho Hahn, / Changyong Kang, / Taeeun Hong, / Younggwan Kim, / Haewang Lee, et al. | 2000
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Highly reliable poly-SiGe/amorphous-Si gate CMOSUejima, K. / Yamamoto, T. / Mogami, T. et al. | 2000
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A 140 GHz ft and 60 GHz fmax DTMOS integrated with high-performance SOI logic technologyMomiyama, Y. / Hirose, T. / Kurata, H. / Goto, K. / Watanabe, Y. / Sugii, T. et al. | 2000
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CMOS device optimization for system-on-a-chip applicationsImai, K. / Yamaguchi, K. / Kudo, T. / Kimizuka, N. / Onishi, H. / Ono, A. / Nakahara, Y. / Goto, Y. / Noda, K. / Masuoka, S. et al. | 2000
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CMOS Device Optimization for System-On-a-Chip Applications (Invited)Imai, K. / Yamaguchi, K. / Kudo, T. / Kimizuka, N. / Onishi, H. / Ono, A. / Nakahara, Y. / Goto, Y. / Noda, K. / Masuoka, S. et al. | 2000
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A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology nodeMorifuji, E. / Oishi, A. / Miyashita, K. / Aota, S. / Nishigori, M. / Ootani, H. / Nakayama, T. / Miyamoto, K. / Matsuoka, F. / Noguchi, T. et al. | 2000
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An 1.5 V High Performance Mixed Signal Integration with Indium Channel for 130 nm Technology NodeMorifuji, E. / Ohishi, A. / Miyashita, K. / Aota, S. / Nishigori, M. / Ootani, H. / Nakayama, T. / Miyamoto, K. / Matsuoka, F. / Noguchi, T. et al. | 2000
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Impact of process scaling on 1/f noise in advanced CMOS technologiesKnitel, M.J. / Woerlee, P.H. / Scholten, A.J. / Zegers-Van Duijnhoven, A. et al. | 2000
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Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technologyHirano, Y. / Matsumoto, T. / Maeda, S. / Iwamatsu, T. / Kunikiyo, T. / Nii, K. / Yamamoto, K. / Yamaguchi, Y. / Ipposhi, T. / Maegawa, S. et al. | 2000
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Impact of 0.10mum SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break through the Scaling Crisis of Silicon TechnologyHirano, Y. / Matsumoto, T. / Maeda, S. / Iwamatsu, T. / Kunikiyo, T. / Nii, K. / Yamamoto, K. / Yamaguchi, Y. / Ipposhi, T. / Maegawa, S. et al. | 2000
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Latchup immunity and well profile design by a deep carbon-doped layerHeinemann, B. / Barth, R. / Bolze, D. / Ehwald, K.-E. / Knoll, D. / Kruger, D. / Kurps, R. / Rucker, H. / Schley, P. / Tillack, B. et al. | 2000
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A high aspect-ratio silicon substrate-via technology and applications: through-wafer interconnects for power and ground and Faraday cages for SOC isolationWu, J.H. / Del Alamo, J.A. / Jenkins, K.A. et al. | 2000
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A micromachining post-process module for RF silicon technologyPham, N.P. / Ng, K.T. / Bartek, M. / Sarro, P.M. / Rejaei, B. / Burghartz, J.N. et al. | 2000
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On-chip wireless interconnection with integrated antennasKihong Kim, / Hyun Yoon, / O, K.K. et al. | 2000
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A high-Q tunable micromechanical capacitor with movable dielectric for RF applicationsJun-Bo Yoon, / Nguyen, C.T.-C. et al. | 2000
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High-Q VHF micromechanical contour-mode disk resonatorsClark, J.R. / Wan-Thai Hsu, / Nguyen, C.T.-C. et al. | 2000
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Modelling of dishing for metal chemical mechanical polishingNguyen, V.H. / Van Der Velden, P. / Daamen, R. / Van Kranenburg, H. / Woerlee, P.H. et al. | 2000
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Recent advances in feature scale simulationKersch, A. / Schulze Icking-Konert, G. et al. | 2000
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Recent Advances in Feature Scale Simulation (Invited)Kersch, A. / Icking-Konert, G. S. / IEEE et al. | 2000
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A physical model for implanted nitrogen diffusion and its effect on oxide growthAdam, L.S. / Law, M.E. / Dokumaci, O. / Hegde, S. et al. | 2000
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A new model for {311} defects based on in situ measurementsLaw, M.E. / Jones, K.S. et al. | 2000
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A New Model for {311} Defects Base on In-Situ MeasurementsLaw, M. / Jones, K. / IEEE et al. | 2000
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Boron diffusion and activation in the presence of other speciesHong-Jyh Li, / Kohli, P. / Ganguly, S. / Kirichenko, T.A. / Zeitzoff, P. / Torres, K. / Banerjee, S. et al. | 2000
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Investigation of a Model for the Segregation and Pile-up of Boron at the SiO~2/Si Interface during the Formation of Ultra-Shallow p^+ JunctionsShima, A. / Jinbo, T. / Ushio, J. / Oh, J.-H. / Ono, K. / Oshima, M. / Natsuaki, N. / IEEE et al. | 2000
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Investigation of a model for the segregation and pile-up of boron at the SiO/sub 2//Si interface during the formation of ultrashallow p/sup +/ junctionsShima, A. / Jinbo, T. / Ushio, J. / Oh, J.-H. / Ono, K. / Oshima, M. / Natsuaki, N. et al. | 2000
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Modeling of arsenic transient enhanced diffusion and background boron segregation in low-energy As/sup +/ implanted SiRyangsu Kim, / Aoki, T. / Hirose, T. / Furuta, Y. / Hayashi, S. / Shano, T. / Taniguchi, K. et al. | 2000
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Modeling of Arsenic Transient Enhanced Diffusion and Background Boron Segregation in Low-Energy As^+ Implanted SiKim, R. / Aoki, T. / Hirose, T. / Furuta, Y. / Hayashi, S. / Shano, T. / Taniguchi, K. / IEEE et al. | 2000
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The statistical distribution of percolation resistance as a probe into the mechanics of ultra-thin oxide breakdownAlam, M.A. / Weir, B.E. / Silverman, P.J. / Ma, Y. / Hwang, D. et al. | 2000
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Post Soft Breakdown Condition in SiO~2 Gate OxidesSune, J. / Miranda, E. / IEEE et al. | 2000
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Post soft breakdown conduction in SiO/sub 2/ gate oxidesSune, J. / Miranda, E. et al. | 2000
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Substrate hole current origin after oxide breakdownRasras, M. / De Wolf, I. / Groeseneken, G. / Degraeve, R. / Maes, H.E. et al. | 2000
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Voltage-dependent voltage-acceleration of oxide breakdown for ultra-thin oxidesWu, E.Y. / Aitken, J. / Nowak, E. / Vayshenker, A. / Varekamp, P. / Hueckel, G. / McKenna, J. / Harmon, D. / Han, L.-K. / Montrose, C. et al. | 2000
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Extending the Reliability Scaling Limit of SiO2 through Plasma NitridationNicollian, P. / Baldwin, G. / Eason, K. / Grider, D. / Hattangady, S. / Hu, J. C. / Hunter, W. / Rodder, M. / Rotondaro, A. / IEEE et al. | 2000
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Extending the reliability scaling limit of SiO/sub 2/ through plasma nitridationNicollian, P.E. / Baldwin, G.C. / Eason, K.N. / Grider, D.T. / Hattangady, S.V. / Hu, J.C. / Hunter, W.R. / Rodder, M. / Rotondaro, A.L.P. et al. | 2000
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Resolving the Non-uniqueness of the Activation Energy Associated with TDDB for SiO~2 Thin FilmsShanware, A. / Khamankar, R. / McPherson, J. / IEEE et al. | 2000
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Resolving the non-uniqueness of the activation energy associated with TDDB for SiO/sub 2/ thin filmsShanware, A. / Khamankar, R.B. / McPherson, W. et al. | 2000
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Impact of MOSFET oxide breakdown on digital circuit operation and reliabilityKaczer, B. / Degraeve, R. / Groeseneken, G. / Rasras, M. / Kubicek, S. / Vandamme, E. / Badenes, G. et al. | 2000
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A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip coresTakao, Y. / Kudo, H. / Mitani, J. / Kotani, Y. / Yamaguchi, S. / Yoshie, K. / Kawano, M. / Nagano, T. / Yamamura, I. / Uematsu, M. et al. | 2000
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A 0.11mum CMOS Technology with Copper and Very-low-k Interconnects for High-Performance System-On-a Chip CoresTakao, Y. / Kudo, H. / Mitani, J. / Kotani, Y. / Yamaguchi, S. / Yoshie, K. / Kawano, M. / Nagano, T. / Yamamura, I. / Uematsu, M. et al. | 2000
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A 0.13mum CMOS Technology with 193nm Lithography and Cu/Low-k for High Performance ApplicationsYoung, K. K. / Wu, S. Y. / Wu, C. C. / Wang, C. H. / Lin, C. T. / Cheng, J. Y. / Chiang, M. / Chen, S. H. / Lo, T. C. / Chen, Y. S. et al. | 2000
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A 0.13 /spl mu/m CMOS technology with 193 nm lithography and Cu/low-k for high performance applicationsYoung, K.K. / Wu, S.Y. / Wu, C.C. / Wang, C.H. / Lin, C.T. / Cheng, J.Y. / Chiang, M. / Chen, S.H. / Lo, T.C. / Chen, Y.S. et al. | 2000
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A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnectsTyagi, S. / Alavi, M. / Bigwood, R. / Bramblett, T. / Brandenburg, J. / Chen, W. / Crew, B. / Hussein, M. / Jacob, P. / Kenyon, C. et al. | 2000
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A Versatile 0.13 mum CMOS Platform Technology Supporting High Performance and Low Power ApplicationsPerera, A. / Smith, B. / Cave, N. / Sureddin, M. / Chheda, S. / Singh, R. / Islam, R. / Chang, J. / Song, S.-C. / Sultan, A. et al. | 2000
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A versatile 0.13 /spl mu/m CMOS platform technology supporting high performance and low power applicationsPerera, A.H. / Smith, B. / Cave, N. / Sureddin, M. / Chheda, S. / Islam, R. / Chang, J. / Song, S.-C. / Sultan, A. / Crown, S. et al. | 2000
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A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applicationsOotsuka, F. / Wakahara, S. / Ichinose, K. / Honzawa, A. / Wada, S. / Sato, H. / Ando, T. / Ohta, H. / Watanabe, K. / Onai, T. et al. | 2000
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A 2.05 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.15 nm generation single gate CMOS technologyJang, J.H. / Kim, H.S. / Baek, H.C. / Na, J.J. / Lee, K.H. / Seo, D.S. / Kim, K.J. / Kim, K.T. / Shin, Y.S. / Hwang, C.G. et al. | 2000
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A 2.05 mum^2 Full CMOS Ultra-Low Power SRAM Cell with 0.15mum Generation Single Gate CMOS TechnologyJang, J. H. / Kim, H. S. / Baek, H. C. / Na, J. J. / Lee, K. H. / Seo, D. S. / Kim, K. J. / Kim, K. T. / Shin, Y. S. / Hwang, C. G. et al. | 2000
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GaAs Schottky wrap-gate binary-decision-diagram devices for realization of novel single electron logic architectureKasai, S. / Amemiya, Y. / Hasegawa, H. et al. | 2000
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Femtosecond all-optical devices for tera-bit/sec optical networksWada, O. et al. | 2000
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Femtosecond All-Optical Devices for Tera-bit/sec Optical Networks (Invited)Wada, O. / IEEE et al. | 2000
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Spot-Size-Converted 1.3mum Directly-Modulated Fabry-Perot and Distributed Feedback Lasers Suitable for Passive Alignment and 2.5 Gb/s Operation at 85CKlotzkin, D. / Sheridan-Eng, J. / Mazzatesta, A. / Ford, G. / Laquindinum, J. / Chien, M. / Park, M. / Michel, E. / Kunkel, R. / Roycroft, S. et al. | 2000
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Spot-size-converted 1.3 /spl mu/m directly-modulated Fabry-Perot and distributed feedback lasers suitable for passive alignment and 2.5 gb/s operation at 85/spl deg/CKlotzkin, D. / Sheridan-Eng, J. / Mazzatesta, A. / Ford, G. / Laquindinum, J. / Chien, M. / Park, M. / Michel, E. / Kinkel, R. / Roycroft, S. et al. | 2000
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High Temperature Operated (∼250 K) Photovoltaic-Photoconductive (PV-PC) Mixed-mode InAs/GaAs Quantum Dot Infrared PhotodetectorTang, S.-F. / Lin, S.-Y. / Lee, S.-C. / Kuan, C. H. / Cherng, Y.-T. / IEEE et al. | 2000
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High temperature operated (/spl sim/250 K) photovoltaic-photoconductive (PV-PC) mixed-mode InAs/GaAs quantum dot infrared photodetectorShiang-Feng Tang, / Shih-Yen Lin, / Si-Chen Lee, / Chieh Hsiung Kuan, / Ya-Tung Cherng, et al. | 2000
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Room-temperature memory operation of AlGaAs/GaAs high electron mobility transistors with InAs quantum dots embedded in the channelJae-Eung Oh, / Jong-Wook Kim, et al. | 2000
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Improved external coupling efficiency in organic light-emitting devices on high-index substratesLu, M.-H. / Madigan, C.F. / Sturm, J.C. et al. | 2000
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Application of metal-induced unilaterally crystallized polycrystalline silicon thin-film transistor technology to active-matrix organic light-emitting diode displaysZhiguo Meng, / Haiying Chen, / Chengfeng Qiu, / Liduo Wang, / Kwok, H.S. / Man Wong, et al. | 2000
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High performance light emitting polymers for colour displaysHeeks, K. / Towns, C. / Burroughes, J. / Cina, S. / Gunner, A. et al. | 2000
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High Performance Light Emitting Polymers for Colour Displays (Invited)Heeks, K. / Towns, C. / Burroughes, J. / Cina, S. / Gunner, A. / IEEE et al. | 2000
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Fast organic circuits on flexible polymeric substratesSheraw, C.D. / Nichols, J.A. / Gundlach, D.J. / Huang, J.R. / Kuo, C.C. / Klauk, H. / Jackson, T.N. / Kane, M.G. / Campi, J. / Cuomo, F.P. et al. | 2000
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All-polymer thin film transistors fabricated by high-resolution ink-jet printingKawase, T. / Sirringhaus, H. / Friend, R.H. / Shimoda, T. et al. | 2000
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Fabrication and characterization of cathodoluminescent devices made using porous silicon as a cold-cathode field emitterElqaq, D.H. / Hasan, M.-A. et al. | 2000
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Impact of recoiled-oxygen-free processing on 1.5 nm SiON gate-dielectric in sub-100 nm CMOS technologyTogo, M. / Mogami, T. et al. | 2000
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Molybdenum Metal Gate MOS Technology for Post-SiO~2 Gate DielectricsLu, Q. / Lin, R. / Ranade, P. / Yeo, Y. C. / Meng, X. / Takeuchi, H. / King, T.-J. / Hu, C. / Luan, H. / Lee, S. et al. | 2000
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Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectricsQiang Lu, / Lin, R. / Ranade, P. / Yee Chia Yeo, / Xiaofan Meng, / Takeuchi, H. / Tsu-Jae King, / Chenming Hu, / Hongfa Luan, / Songjoo Lee, et al. | 2000
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Effect of Polysilicon Gate on the Flatband Voltage Shift and Mobility Degradation for ALD-Al~2O~3 Gate DielectricLee, J. H. / Koh, K. / Lee, N. I. / Cho, M. H. / Kim, Y. K. / Jeon, J. S. / Cho, K. H. / Shin, H. S. / Kim, M. H. / Fujihara, K. et al. | 2000
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Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectricLee, J.H. / Koh, K. / Lee, N.I. / Cho, M.H. / Ki, Y.K. / Jeon, J.S. / Cho, K.H. / Shin, H.S. / Kim, M.H. / Fujihara, K. et al. | 2000
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Conformable Formation of High Quality Ultra-Thin Amorphous Ta~2O~5 Gate Dielectrics Utilizing Water Assisted Deposition (WAD) for Sub 50 nm Damascene Metal Gate MOSFETsInumiya, S. / Morozumi, Y. / Yagishita, A. / Saito, T. / Gao, D. / Choi, D. / Hasebe, K. / Suguro, K. / Tsunashima, Y. / Arikado, T. et al. | 2000
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Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETsInumiya, S. / Morozumi, Y. / Yagishita, A. / Saito, T. / Gao, D. / Choi, D. / Hasebe, K. / Suguro, K. / Tsunashima, Y. / Arikado, T. et al. | 2000
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High-k gate dielectrics with ultra-low leakage current based on praseodymium oxideOsten, H.J. / Liu, J.P. / Gaworzewski, P. / Bugiel, E. / Zaumseil, P. et al. | 2000
- 659
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A Notched Metal Gate MOSFET for sub-0.1 mum OperationPidin, S. / Mushiga, M. / Shido, H. / Yamamoto, T. / Sambonsugi, Y. / Tamura, Y. / Sugii, T. / IEEE et al. | 2000
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A notched metal gate MOSFET for sub-0.1 /spl mu/m operationPidin, S. / Mushiga, M. / Shido, H. / Yamamoto, T. / Sambonsugi, Y. / Tamura, Y. / Sugii, T. et al. | 2000
- 663
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Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristicsYagishita, A. / Saito, T. / Inumiya, S. / Matsuo, K. / Tsunashima, Y. / Suguro, K. / Arikado, T. et al. | 2000
- 667
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A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETsBae, G.J. / Choe, T.H. / Kim, S.S. / Rhee, H.S. / Lee, K.W. / Lee, N.I. / Kim, K.D. / Park, Y.K. / Kang, H.S. / Kim, Y.W. et al. | 2000
- 671
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Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETsEsseni, D. / Mastrapasqua, M. / Celler, G.K. / Baumann, F.H. / Fiegna, C. / Selmi, L. / Sangiorgi, E. et al. | 2000
- 675
-
Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETsAnil, K.G. / Mahapatra, S. / Eisele, I. et al. | 2000
- 679
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Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETsYang, K.N. / Huang, H.T. / Chen, M.J. / Lin, Y.M. / Yu, M.C. / Jang, S.M. / Yu, C.H. / Liang, M.S. et al. | 2000
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A novel, aerosol-nanocrystal floating-gate device for non-volatile memory applicationsDe Blauwe, J. / Ostraat, M. / Green, M.L. / Weber, G. / Sorsch, T. / Kerber, A. / Klemens, F. / Cirelli, R. / Ferry, E. / Grazul, J.L. et al. | 2000
- 689
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Sensitivity improvement in progressive-scan FT-CCDs for digital still camera applicationsVan Kuijk, H.C. / Bosiers, J.T. / Kleimann, A.C. / Le Cam, L. / Maas, J.P. / Peek, H.L. / Peschel, C.R. et al. | 2000
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Sensitivity Improvements in Progressive-Scan FT-CCDs for Digital Still Camera Applicationsvan Kuijk, H. / Bosiers, J. / Kleimann, A. / Le Cam, L. / Maas, J. / Peek, H. / Peschel, C. / IEEE et al. | 2000
- 693
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A novel lateral overflow drain technology for high quantum efficiency CCD imagersAdachi, S. / Simada, H. / Gotoh, H. / Mizobuchi, K. et al. | 2000
- 697
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Monolithic 3.3 V CCD/SOI-CMOS imager technologySuntharalingam, V. / Burke, B. / Cooper, M. / Yost, D. / Gouker, P. / Anthony, M. / Whittingham, H. / Sage, J. / Burns, J. / Rabe, S. et al. | 2000
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High sensitivity and no-cross-talk pixel technology for embedded CMOS image sensorFurumiya, M. / Ohkubo, H. / Muramatsu, Y. / Kurosawa, S. / Nakashiba, Y. et al. | 2000
- 705
-
High performance 0.25-um CMOS color imager technology with non-silicide source/drain pixelShou-Gwo Wuu, / Dun-Nian Yaung, / Chien-Hsien Tseng, / Ho-Ching Chien, / Wang, C.S. / Yean-Kuen Hsiao, / Chin-Kung Chang, / Chang, B.J. et al. | 2000
- 705
-
High Performance 0.25-mum CMOS Color Imager Technology with Non-silicide Source/Drain PixelWuu, S.-G. / Yaung, D.-N. / Tseng, C.-H. / Chien, H.-C. / Wang, C. S. / Fang, Y.-K. / Wang, C.-C. / Sodini, C. / Hsiao, Y.-K. / Chang, C.-K. et al. | 2000
- 709
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Ultraviolet avalanche photodiode in CMOS technologyPauchard, A. / Rochas, A. / Randjelovic, Z. / Besse, P.A. / Popovic, R.S. et al. | 2000
- 715
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The ballistic nanotransistor: a simulation studyZhibin Ren, / Venugopal, R. / Datta, S. / Lundstrom, M. / Jovanovic, D. / Fossum, J. et al. | 2000
- 719
-
Gate length scaling and threshold voltage control of double-gate MOSFETsChang, L. / Tang, S. / Tsu-Jae King, / Bokor, J. / Chenming Hu, et al. | 2000
- 723
-
Advanced model and analysis for series resistance in sub-100 nm CMOS including poly depletion and overlap doping gradient effectSeong Dong Kim, / Cheol-Min Park, / Woo, J.C.S. et al. | 2000
- 727
-
Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICsSungjun Im, / Banerjee, K. et al. | 2000
- 731
-
RLC Signal Integrity Analysis of High-Speed Global InterconnectHuang, X. / Cao, Y. / Sylvester, D. / Lin, S. / King, T.-J. / Hu, C. / IEEE et al. | 2000
- 731
-
RLC signal integrity analysis of high-speed global interconnects [CMOS]Xuejue Huang, / Yu Cao, / Sylvester, D. / Shen Lin, / King, T.-J. / Chenming Hu, et al. | 2000
- 737
-
Device and technology requirements for next generation communications systemsLarson, L.E. et al. | 2000
- 737
-
Device and Technology Requirements for Next Generation Communications Systems (Invited)Larson, L. E. / IEEE et al. | 2000
- 741
-
A 0.2-/spl mu/m 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applicationsWashio, K. / Ohue, E. / Shimamoto, H. / Oda, K. / Hayami, R. / Kiyota, Y. / Tanabe, M. / Kondo, M. / Hashimoto, T. / Harada, T. et al. | 2000
- 741
-
A 0.2-mum 180-GHz-f~m~a~x 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HBT/CMOS Technology for Microwave and High-Speed Digital ApplicationsWashio, K. / Ohue, E. / Shimamoto, H. / Oda, K. / Hayami, R. / Kiyota, Y. / Tanabe, M. / Kondo, M. / Hashimoto, T. / Harada, T. et al. | 2000
- 745
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SiGe bipolar technology for mixed digital and analogue RF applicationsBbck, J. / Meister, T.F. / Knapp, H. / Zoschg, D. / Schafer, H. / Aufinger, K. / Wurzer, M. / Boguth, S. / Franosch, M. / Stengl, R. et al. | 2000
- 749
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Novel epitaxial p-Si/n-Si/sub 1-y/C/sub y//p-Si heterojunction bipolar transistorsSingh, D.V. / Hoyt, J.L. / Gibbons, J.F. et al. | 2000
- 749
-
Novel Epitaxial p-Si/n-Si~1~-~yCy/p-Si Heterojunction Bipolar TransistorsSingh, D. / Hoyt, J. / Gibbons, J. / IEEE et al. | 2000
- 753
-
Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germaniumYee-Chia Yeo, / Qiang Lu, / Tsu-Jae King, / Chenming Hu, / Kawashima, T. / Oishi, M. / Mashiro, S. / Sakai, J. et al. | 2000
- 757
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High Performance Digital-Analog Mixed Device on a Si Substrate with Resistivity Beyond 1 kOmega cmOhguro, T. / Ishikawa, T. / Kimura, T. / Samata, S. / Kawasaki, A. / Nagano, T. / Yoshitomi, T. / Toyoshima, T. / IEEE et al. | 2000
- 757
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High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cmOhguro, T. / Ishikawa, T. / Kimura, T. / Samata, S. / Kawasaki, A. / Nagano, T. / Yoshitomi, T. / Toyoshima, T. et al. | 2000
- 763
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Advanced flash memory technology and trends for file storage applicationAritome, S. et al. | 2000
- 763
-
Advanced Flash Memory Technology and Trends for File Storage Application (Invited)Aritome, S. / IEEE et al. | 2000
- 767
-
A 0.15 /spl mu/m NAND flash technology with 0.11 /spl mu/m/sup 2/ cell size for 1 Gbit flash memoryJung-Dal Choi, / Joon-Hee Lee, / Won-Hong Lee, / Kwang-Shik Shin, / Yong-Sik Yim, / Jae-Duk Lee, / Yoo-Cheol Shin, / Sung-Nam Chang, / Kyu-Charn Park, / Jong-Woo Park, et al. | 2000
- 767
-
A 0.15mum NAND Flash Technology with 0.11 mum^2 Cell Size for 1 Gbit Flash MemoryChoi, J. D. / Lee, J. H. / Lee, W. H. / Shin, K.-S. / Yim, Y.-S. / Lee, J.-D. / Shin, Y.-C. / Chang, S.-N. / Park, K.-C. / Park, J.-W. et al. | 2000
- 771
-
A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memoriesGoda, A. / Moriyama, W. / Hazama, H. / Iizuka, H. / Shimizu, K. / Aritome, S. / Shirota, R. et al. | 2000
- 775
-
High-Density (4.4F^2) NAND Flash Technology Using Super-Shallow Channel Profile (SSCP) EngineeringArai, F. / Arai, N. / Satoh, S. / Yaegashi, T. / Kamiya, E. / Matsunaga, Y. / Takeuchi, Y. / Kamata, H. / Shimizu, A. / Ohtani, N. et al. | 2000
- 775
-
High-density (4.4F/sup 2/) NAND flash technology using Super-Shallow Channel Profile (SSCP) engineeringArai, F. / Arai, N. / Satoh, S. / Yaegashi, T. / Kamiya, E. / Matsunaga, Y. / Takeuchi, Y. / Kamata, H. / Shimizu, A. / Ohtami, N. et al. | 2000
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A novel Uniform-Channel-Program Erase (UCPE) flash EEPROM using an isolated P-well structureLi, C.-N.B. / Farenc, D. / Singh, R. / Yater, J. / Liu, S. / Chia-Lin Chang, / Bagchi, S. / Chen, K. / Ingersoll, P. / Kuo-Tung Chang, et al. | 2000
- 783
-
64 Kbit CMVP FeRAM macro with reliable retention/imprint characteristicsKobayashi, S. / Amanuma, K. / Mori, H. / Kasai, N. / Maejima, Y. / Seike, A. / Tanabe, N. / Tatsumi, T. / Yamada, J. / Miwa, T. et al. | 2000
- 789
-
Conformal CVD-ruthenium process for MIM capacitor in giga-bit DRAMsSeok-Jun Won, / Wan-Don Kim, / Cha-Young Yoo, / Sung-Tae Kim, / Young-Wook Park, / Joo-Tae Moon, / Moon-Yong Lee, et al. | 2000
- 793
-
Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMsFukuzumi, Y. / Suzuki, T. / Sato, A. / Ishibashi, Y. / Hatada, A. / Nakamura, K. / Tsunoda, K. / Fukuda, M. / Lin, J. / Nakabayashi, M. et al. | 2000
- 793
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Liner-Supported Cylinder (LSC) Technology to Realize Ru/Ta~2O~5/Ru Capacitor for Future DRAMsFukuzumi, Y. / Suzuki, T. / Sato, A. / Ishibashi, Y. / Hatada, A. / Nakamura, K. / Tsunoda, K. / Fukuda, M. / Lin, J. / Nakabayashi, M. et al. | 2000
- 797
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Low thermal-budget fabrication of sputtered-PZT capacitor on multilevel interconnects for embedded FeRAMInoue, N. / Nakura, T. / Hayashi, Y. et al. | 2000
- 801
-
A novel Ir/IrO/sub 2//Pt-PZT-Pt/IrO/sub 2//Ir capacitor for a highly reliable mega-scale FRAMDongjin Jung, / Hyunho Kim, / Yoonjong Song, / Nakwon Jang, / Bonjae Koo, / Sungyung Lee, / Soonoh Park, / Yungwook Park, / Kinam Kim, et al. | 2000
- 801
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A Novel Ir/IrO~2/Pt-PZT-Pt/IrO~2/Ir Capacitor for A Highly Reliable Mega-Scale FRAMJung, D. J. / Kim, H. H. / Song, Y. J. / Jang, N. W. / Koo, B. J. / Lee, S. Y. / Park, S. O. / Park, Y. W. / Kim, K. / IEEE et al. | 2000
- 807
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RF-distortion in deep-submicron CMOS technologiesvan Langevelde, R. / Tiemeijer, L.F. / Havens, R.J. / Knitel, M.J. / Ores, R.F.M. / Woerlee, P.H. / Klaassen, D.B.M. et al. | 2000
- 811
-
The equivalence of van der Ziel and BSIM4 models in modeling the induced gate noise of MOSFETsJung-Suk Goo, / Liu, W. / Chang-Hoon Choi, / Green, K.R. / Zhiping Yu, / Lee, T.H. / Dutton, R.W. et al. | 2000
- 815
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BSIM4 gate leakage model including source-drain partitionCao, K.M. / Lee, W.-C. / Liu, W. / Jin, X. / Su, P. / Fung, S.K.H. / An, J.X. / Yu, B. / Hu, C. et al. | 2000
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The construction and evaluation of behavioral models for microwave devices based on time-domain large-signal measurementsSchreurs, D. / Wood, J. / Tufillaro, N. / Usikov, D. / Barford, L. / Root, D.E. et al. | 2000
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A new analytical delay and noise model for on-chip RLC interconnectYu Cao, / Xuejue Huang, / Sylvester, D. / Chang, N. / Chenming Hu, et al. | 2000
- 829
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Phase shift lithography in the manufacture of sub-120 nm low-voltage DSP circuitsKizilyalli, I.C. / Watson, G.P. / Kohler, R.A. / Nalamasu, O. / Harriott, L.R. et al. | 2000
- 829
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Phase Shift Lithography in the Manufacture of sub-120 nm Low-Voltage DSP Circuits (Invited)Kizilyalli, I. / Watson, G. / Kohler, R. / Nalamasu, O. / Harriott, L. / IEEE et al. | 2000
- 833
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Throughput enhancement strategy of maskless electron beam direct writing for logic deviceInanami, R. / Magoshi, S. / Kousai, S. / Hmada, M. / Takayanagi, T. / Sugihara, K. / Okumura, K. / Kuroda, T. et al. | 2000
- 837
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Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention timeSaino, K. / Horiba, S. / Uchiyama, S. / Takaishi, Y. / Takenaka, M. / Uchida, T. / Takada, Y. / Koyama, K. / Miyake, H. / Hu, C. et al. | 2000
- 841
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Yield management methodology for SoC vertical yield rampMiyamoto, K. / Inoue, K. / Tamura, I. / Kondo, N. / Inoto, H. / Ito, I. / Kasahara, K. / Oshikiri, Y. et al. | 2000
- 845
-
New yield models for DSM manufacturingFei, Y. / Simon, P. / Maly, W. et al. | 2000
- 851
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Cu Single Damascene Interconnects with Plasma-Polymerized Organic Polymers (k=2.6) for High-Speed, 0.1mum CMOS DevicesTagami, M. / Fukai, T. / Hiroi, M. / Kawahara, J. / Shiba, K. / Tada, M. / Onodera, T. / Saito, S. / Kinoshita, K. / Ogura, T. et al. | 2000
- 851
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Cu single damascene interconnects with plasma-polymerized organic polymers (k=2.6) for high-speed, 0.1 /spl mu/m CMOS devicesTagami, M. / Fukai, T. / Hiroi, M. / Kawahara, J. / Shiba, K. / Tada, M. / Onodera, T. / Saito, S. / Kinoshita, K. / Ogura, T. et al. | 2000
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Undoped-emitter InP/InGaAs HBTs for high-speed and low-power applicationsIda, M. / Kurishima, K. / Nakajima, H. / Watanabe, N. / Yamahata, S. et al. | 2000
- 857
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A novel implantless MOS thin-film transistor with simple processing, excellent performance and ambipolar operation capabilityLin, H.C. / Lin, C.Y. / Yeh, K.L. / Huang, R.G. / Wang, M.F. / Yu, C.M. / Huang, T.Y. / Sze, S.M. et al. | 2000
- 860
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Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodesQi Xiang, / Joong Jeon, / Sachdey, P. / Bin Yu, / Saraswat, K.C. / Ming-Ren Lin, et al. | 2000
- 863
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Room-temperature operation of multifunctional single-electron transistor logicUchida, K. / Koga, J. / Ohba, R. / Toriumi, A. et al. | 2000
- 866
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Silicon single-electron CCDFujiwara, A. / Takahashi, Y. et al. | 2000
- 869
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Stencil mask ion implantation technology for high performance MOSFETsShibata, T. / Suguro, K. / Sugihara, K. / Mizuno, H. / Yagishita, A. / Saito, T. / Okumura, K. / Nishihashi, T. / Gotou, T. / Tsunoda, M. et al. | 2000