1.55-mum reflection-type optical waveguide switch based on thermo-optic effect [5117-70] (Englisch)
- Neue Suche nach: Cantore, F. L.
- Neue Suche nach: Corte, F. G. D.
- Neue Suche nach: SPIE
- Neue Suche nach: Cantore, F. L.
- Neue Suche nach: Corte, F. G. D.
- Neue Suche nach: Lopez, J. F.
- Neue Suche nach: Montiel-Nelson, J. A.
- Neue Suche nach: Pavlidis, D.
- Neue Suche nach: SPIE
In:
VLSI circuits and systems
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589-597
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2003
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Print
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Titel:1.55-mum reflection-type optical waveguide switch based on thermo-optic effect [5117-70]
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Beteiligte:Cantore, F. L. ( Autor:in ) / Corte, F. G. D. ( Autor:in ) / Lopez, J. F. / Montiel-Nelson, J. A. / Pavlidis, D. / SPIE
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Kongress:Conference, VLSI circuits and systems ; 2003 ; Maspalomas, Spain
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Erschienen in:VLSI circuits and systems ; 589-597PROCEEDINGS- SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING ; 5117 ; 589-597
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Verlag:
- Neue Suche nach: SPIE
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Erscheinungsdatum:01.01.2003
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Format / Umfang:9 pages
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Anmerkungen:Held as part of the Symposium on Microtechnologies for the New Millenium
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
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Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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IC technology trends for wireless local area networks (Invited Paper) [5117-73]Weste, N. / SPIE et al. | 2003
- 1
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IC technology trends for wireless local area networksWeste, Neil et al. | 2003
- 13
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VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing [5117-01]Stechele, W. / SPIE et al. | 2003
- 13
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VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processingStechele, Walter et al. | 2003
- 23
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FPGA implementation of Santos-Victor optical flow algorithm for real-time image processing: a useful attempt [5117-02]Arribas, P. C. / Macia, F. M. H. / SPIE et al. | 2003
- 23
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FPGA implementation of Santos-Victor optical flow algorithm for real-time image processing: an useful attemptCobos Arribas, Pedro / Monasterio Huelin Macia, Felix et al. | 2003
- 33
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Integer cosine transform chip design for image compressionRuiz, Gustavo A. / Michell, Juan A. / Buron, Angel M. / Solana, Jose M. / Manzano, Miguel A. / Diaz, J. et al. | 2003
- 33
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Integer cosine transform chip design for image compression [5117-03]Ruiz, G. A. / Michell, J. A. / Buron, A. M. / Solana, J. M. / Manzano, M. A. / Diaz, J. / SPIE et al. | 2003
- 42
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Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoderCallico, Gustavo M. / Peset Llopis, Rafael / Nunez, Antonio / Sethuraman, Ramanathan et al. | 2003
- 42
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Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoder [5117-04]Callico, G. M. / Llopis, R. P. / Nunez, A. / Sethuraman, R. / SPIE et al. | 2003
- 53
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State of the art in CMOS threshold logic VLSI gate implementations and applications (Invited Paper) [5117-06]Celinski, P. / Cotofana, S. D. / Lopez, J. F. / Al-Sarawi, S. F. / Abbott, D. / SPIE et al. | 2003
- 53
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State of the art in CMOS threshold logic VLSI gate implementations and systemsCelinski, Peter / Cotofana, Sorin D. / Lopez, Jose F. / Al-Sarawi, Said F. / Abbott, Derek et al. | 2003
- 65
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New efficient offset voltage cancellation techniques using digital trimmingAl-Sarawi, Said F. et al. | 2003
- 65
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New efficient offset voltage cancellation techniques using digital trimming [5117-07]Al-Sarawi, S. F. / SPIE et al. | 2003
- 77
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Novel 1.25Gb/s CMOS burst mode optical receiver with automatically gain controllable preamplifier and high sensitive peak detector without external reset signalSeo, Ja-Won / Han, Seop / Le, Quan / Lee, Sang-Gug / Lee, Man-Seop / Yoo, Tae-Whan et al. | 2003
- 77
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Novel 1.25-Gb/s CMOS burst mode optical receiver with automatic gain controllable preamplifier and a highly sensitive peak detector without external reset signal [5117-08]Seo, J.-W. / Han, S. / Le, Q. / Lee, S.-G. / Lee, M.-S. / Yoo, T.-W. / SPIE et al. | 2003
- 86
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Scheduling components for multigigabit network SoCs [5117-10]Orphanoudakis, T. / Komaros, G. / Papaefstathiou, I. / Leligou, H.-C. / Perissakis, S. / Zervos, N. / SPIE et al. | 2003
- 86
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Scheduling components for multigigabit network SoCsOrphanoudakis, Theofanis / Kornaros, George / Papaefstathiou, Ioannis / Leligou, Helen-Catherine / Perissakis, Stylianos / Zervos, Nicholas et al. | 2003
- 98
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CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using a low-voltage power line [5117-11]Escalera, S. / Dominguez-Matas, C. M. / Garcia-Gonzalez, J. M. / Guerra, O. / Rodriguez-Vazquez, A. / SPIE et al. | 2003
- 98
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CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power lineEscalera, Sara / Dominguez-Matas, Carlos M. / Garcia-Gonzalez, Jose M. / Guerra, Oscar / Rodriguez-Vazquez, Angel et al. | 2003
- 106
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High-speed clock recovery unit based on a phase aligner [5117-12]Tejera, E. / Esper-Chain, R. / Tobajas, F. / De Armas, V. / Sarmiento, R. / SPIE et al. | 2003
- 106
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High-speed clock recovery unit based on a phase alignerTejera, Efrain / Esper-Chain, Roberto / Tobajas, Felix / De Armas, Valentin / Sarmiento, Roberto et al. | 2003
- 116
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Practical high-level methodology case study: implementation of an ATM over SDH transceiver from the system specification [5117-13]Arteaga, R. / Tobajas, F. / Esper-Chain, R. / De Armas, V. / Sarmiento, R. / SPIE et al. | 2003
- 116
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Practical high-level methodology case study: implementation of an ATM over SDH transceiver from the system specificationArteaga, Ruben / Tobajas, Felix / Esper-Chain, Roberto / De Armas, Valentin / Sarmiento, Roberto et al. | 2003
- 126
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High-bandwidth low-latency global interconnect (Invited Paper) [5117-14]Svensson, C. M. / Caputa, P. / SPIE et al. | 2003
- 126
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High-bandwidth low-latency global interconnectSvensson, Christer M. / Caputa, Peter et al. | 2003
- 135
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Leakage control for deep-submicron circuitsRoy, Kaushik / Mahmoodi-Meimand, Hamid / Mukhopadhyay, Saibal et al. | 2003
- 135
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Leakage control for deep-submicron circuits [5117-15]Roy, K. / Mahmoodi-Meimand, H. / Mukhopadhyay, S. / SPIE et al. | 2003
- 147
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Scaling down photonic waveguide devices on the SOI platformCheben, Pavel / Xu, Dan-Xia / Janz, Siegfried / Delage, Andre et al. | 2003
- 147
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Scaling down photonic waveguide devices on the SOI platform [5117-16]Cheben, P. / Xu, D.-X. / Janz, S. / Delage, A. / SPIE et al. | 2003
- 157
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Theoretical analysis on characteristics and efficiency of CdS/CdTe heterojunction solar cell [5117-17]Guo, J. / Kong, C. / Wang, W. / SPIE et al. | 2003
- 157
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Theoretical analysis on characteristics and efficiency of CdS/CdTe heterojunction solar cellGuo, Jiang / Kong, Chunyang / Wang, Wanlu et al. | 2003
- 165
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Signaling in the heterogeneous architecture multiprocessor paradigmNunez, Antonio / Reyes, Victor / Bautista, Tomas et al. | 2003
- 165
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Signaling in the heterogeneous architecture multiprocessor paradigm (Invited Paper) [5117-18]Nunez, A. / Reyes, V. / Bautista, T. / SPIE et al. | 2003
- 175
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High-performance VLSI architecture for video processingNavarro, Hector / Montiel-Nelson, Juan A. / Sosa, Javier / Garcia, Jose C. / Sarmiento, Roberto / Nooshabadi, Saeid et al. | 2003
- 187
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System-level verification methodology for advanced switch fabricsSosa, Javier / Montiel-Nelson, Juan A. / Navarro, Hector / Shahdadpuri, Mahendra V. / Sarmiento, Roberto et al. | 2003
- 187
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System-level verification methodology for advanced switch fabrics [5117-21]Sosa, J. / Montiel-Nelson, J. A. / Navarro, H. / Shahdadpuri, M. V. / Sarmiento, R. / SPIE et al. | 2003
- 199
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Models and algorithm for the calculation of the impulse response on IR-wireless indoor channelsRodriguez, Silvestre / Perez-Jimenez, Rafael / Lopez-Hernandez, Francisco J. / Gonzalez, Oswaldo B. / Mendoza, Beatriz R. et al. | 2003
- 199
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Models and algorithm for the calculation of the impulse response on IR-wireless indoor channels [5117-22]Rodriguez, S. / Perez-Jimenez, R. / Lopez-Hernandez, F. J. / Gonzalez, O. B. / Mendoza, B. R. / SPIE et al. | 2003
- 209
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VESTA: a system-level verification environment based on C++Shahdadpuri, Mahendra V. / Sosa, Javier / Navarro, Héctor / Montiel-Nelson, Juan A. / Sarmiento, Roberto et al. | 2003
- 209
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VESTA: a system-level verification environment based on C++ [5117-23]Shahdadpuri, M. V. / Sosa, J. / Navarro, H. / Montiel-Nelson, J. A. / Sarmiento, R. / SPIE et al. | 2003
- 220
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MHDL CAD tool with fault circuit handlingEspinosa Flores-Verdad, Guillermo / Altamirano Robles, Leopoldo / Osorio Roque, Leticia et al. | 2003
- 220
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MHDL CAD tool with fault circuit handling [5117-24]Flores-Verdad, G. E. / Robles, L. A. / Roque, L. O. / SPIE et al. | 2003
- 228
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Switch-based interconnect architecture for future systems on chip [5117-25]Pande, P. P. / Grecu, C. S. / Ivanov, A. / Saleh, R. A. / SPIE et al. | 2003
- 228
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Switch-based interconnect architecture for future systems on chipPande, Partha P. / Grecu, Cristian S. / Ivanov, Andre / Saleh, Resve A. et al. | 2003
- 238
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CMOS receiver circuits for high-speed data transmission according to LVDS standard [5117-26]Hirsch, S. / Pfleiderer, H.-J. / SPIE et al. | 2003
- 238
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CMOS receiver circuits for high-speed data transmission according to LVDS-standardHirsch, Stefan / Pfleiderer, Hans-Jorg et al. | 2003
- 245
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System-level optimization of baseband filters for communication applicationsDelgado-Restituto, Manuel / Fernandez-Bootello, Juan F. / Rodriguez-Vazquez, Angel et al. | 2003
- 245
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System-level optimization of baseband filters for communication applications [5117-27]Fernandez-Bootello, J. F. / Delgado-Restituto, M. / Rodriguez-Vazquez, A. / SPIE et al. | 2003
- 257
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Analog filter circuits testing using voltage and current measurements [5117-28]Al-Qutayri, M. A. / SPIE et al. | 2003
- 257
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Analogue filter circuits testing using voltage and current measurementsAl-Qutayri, Mahmoud A. et al. | 2003
- 267
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Iterative current mode per pixel ADC for 3D SoftChip implementation in CMOSLachowicz, Stefan W. / Rassau, Alexander / Lee, Seung-Minh / Eshraghian, Kamran / Lee, Mike M. et al. | 2003
- 267
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Iterative current mode per pixel ADC for 3D SoftChip implementation in CMOS [5117-29]Lachowicz, S. W. / Rassau, A. / Lee, S.-M. / Eshraghian, K. / Lee, M. M.-O. / SPIE et al. | 2003
- 274
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Novel low-voltage low-power Gb/s transimpedance amplifier architectureGuckenberger, Drew / Kornegay, Kevin et al. | 2003
- 274
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Novel low-voltage low-power Gb/s transimpedance amplifier architecture [5117-30]Guckenberger, D. / Kornegay, K. / SPIE et al. | 2003
- 286
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Σ-Δ modulator for a programmable gain, low-power, high-linearity automotive sensor interfacede la Rosa, Jose M. / Medeiro, Fernando / Perez-Verdu, Belen / del Rio, Rocio / Rodriguez-Vazquez, Angel et al. | 2003
- 286
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SigmaDelta modulator for a programmable-gain low-power high-linearity automotive sensor interface [5117-31]de la Rosa, J. M. / Medeiro, F. / Perez-Verdu, B. / del Rio, R. / Rodriguez-Vazquez, A. / SPIE et al. | 2003
- 298
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LP-LV high-performance monolithic DTMF receiver with on-chip test facilitiesVazquez, Diego / Huertas, Gloria / Avedillo, Maria J. / Quintana, Jose M. / Rueda, Adoracion / Huertas, Jose L. et al. | 2003
- 298
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LP-LV high-performance monolithic DTMF receiver with on-chip test facilities [5117-32]Vazquez, D. / Huertas, G. / Avedillo, M. J. / Quintana, J. M. / Rueda, A. / Huertas, J. L. / SPIE et al. | 2003
- 310
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Flexible coprocessor architectures for ambient intelligent applications in the mobile communication and automotive domain [5117-33]Gehrke, W. / Jachalsky, J. / Wahle, M. / Kruijtzer, W. / Alba, C. / Sethuraman, R. / SPIE et al. | 2003
- 310
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Flexible coprocessor architectures for ambient intelligent applications in the mobile communication and automotive domainGehrke, Winfried / Jachalsky, Joern / Wahle, Martin / Kruijtzer, Wido / Alba, Carlos / Sethuraman, Ramanathan et al. | 2003
- 321
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Lifting folded pipelined discrete wavelet packet transform architecturePaya, Guillermo / Peiro, Marcos M. / Ballester, J. Francisco / Herrero, Vicente / Mora, Francisco et al. | 2003
- 321
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Lifting folded pipelined discrete wavelet packet transform architecture [5117-34]Paya, G. / Peiro, M. M. / Ballester, J. F. / Herrero, V. / Mora, F. / SPIE et al. | 2003
- 329
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Some experiences using system-on-chip buses [5117-36]Carballo, P. P. / Santos, P. / Marrero, M. / Nunez, A. / SPIE et al. | 2003
- 329
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Some experiences using system-on-chip busesCarballo, Pedro P. / Santos, Pablo / Marrero, Margarita / Nunez, Antonio et al. | 2003
- 341
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Performance optimization of the MPEG-2 to MPEG-4 video transcoderKalva, Hari / Vetro, Anthony / Sun, Huifang et al. | 2003
- 341
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Performance optimization of an MPEG-2 to MPEG-4 video transcoder (Invited Paper) [5117-37]Kalva, H. / Vetro, A. / Sun, H. / SPIE et al. | 2003
- 351
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New lifting folded pipelined discrete wavelet transform architecture [5117-38]Paya, G. / Peiro, M. M. / Ballester, J. F. / Herrero, V. / Colom, R. / SPIE et al. | 2003
- 351
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New lifting folded pipelined discrete wavelet transform architecturePaya, Guillermo / Peiro, Marcos M. / Ballester, J. Francisco / Herrero, Vicente / Colom, Ricardo et al. | 2003
- 361
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0.25-μm technology arithmetic codec for mobile multimedia communicatorsAlvarez, Alberto / Lopez, Sebastian / Lopez, Jose F. / Sarmiento, Roberto et al. | 2003
- 361
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0.25-mum technology arithmetic codec for mobile multimedia communicators [5117-39]Alvarez, A. / Lopez, S. / Lopez, J. F. / Sarmiento, R. / SPIE et al. | 2003
- 370
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New distributed arithmetic discrete wavelet packet transform architecturePaya, Guillermo / Peiro, Marcos M. / Ballester, J. Francisco / Gadea, Rafael / Colom, Ricardo et al. | 2003
- 370
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New distributed arithmetic discrete wavelet packet transform architecture [5117-40]Paya, G. / Peiro, M. M. / Ballester, J. F. / Gadea, R. / Colom, R. / SPIE et al. | 2003
- 379
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Mixed-signal early vision chip with embedded-image and programming memories and digital I/O [5117-41]Linan-Cembrano, G. / Rodriguez-Vazquez, A. / Dominguez-Castro, R. / Espejo, S. / SPIE et al. | 2003
- 379
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Mixed-signal early vision chip with embedded image and programming memories and digital I/OLinan-Cembrano, Gustavo / Rodriguez-Vazquez, Angel / Dominguez-Castro, Rafael / Espejo, Servando et al. | 2003
- 389
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Approaching nanoscale integrationDraxelmayr, Dieter et al. | 2003
- 389
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Approaching nanoscale integration (Keynote Paper, Invited Paper) [5117-42]Draxelmayr, D. / SPIE et al. | 2003
- 401
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Holographic study of microsystems during space missions in the 21st centuryPetrov, Valery D. et al. | 2003
- 401
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Holographic study of microsystems during space missions in the 21st century (Invited Paper) [5117-43]Petrov, V. D. / SPIE et al. | 2003
- 416
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Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFICAragones, Xavier / Mateo, Diego / Boric-Lubecke, Olga et al. | 2003
- 416
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Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC [5117-44]Aragones, X. / Mateo, D. / Boric-Lubecke, O. / SPIE et al. | 2003
- 428
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Low-cost VLSI-compatible resonant-cavity-enhanced p-i-n in muc-Si operating at VCSEL wavelengths around 850 nm [5117-45]De Stefano, L. / Moretti, L. / Rendina, I. / Summonte, C. / SPIE et al. | 2003
- 428
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Low-cost VLSI-compatible resonant-cavity-enhanced p-i-n in micron-Si operating at the VCSEL wavelengths around 850 nmDe Stefano, Luca / Moretti, Luigi / Rendina, Ivo / Summonte, Caterina et al. | 2003
- 434
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Macromodel for exact computation of propagation delay time in GaAs and CMOS technologiesGarcia, Jose C. / Montiel-Nelson, Juan A. / Sosa, Javier / Navarro, Hector / Sarmiento, Roberto et al. | 2003
- 434
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Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies [5117-46]Garcia, J. C. / Montiel-Nelson, J. A. / Sosa, J. / Navarro, H. / Sarmiento, R. / SPIE et al. | 2003
- 445
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Simulation of void formation in interconnect linesSheikholeslami, Alireza / Heitzinger, Clemens / Puchner, Helmut / Badrieh, Fuad / Selberherr, Siegfried et al. | 2003
- 445
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Simulation of void formation in interconnect lines [5117-47]Sheikholeslami, A. / Heitzinger, C. / Puchner, H. / Badrieh, F. / Selberherr, S. / SPIE et al. | 2003
- 453
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Timing and power model for CMOS inverters [5117-48]Geissler, R. / Pfleiderer, H.-J. / SPIE et al. | 2003
- 453
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Timing and power model for CMOS invertersGeibler, Richard / Pfleiderer, Hans-Jorg et al. | 2003
- 461
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Empirical model of the metal losses in integrated inductorsdel Pino, F. Javier / Garcia, Javier / Gonzalez, Benito / Sendra, Jose R. / Hernandez, Antonio / Garcia-Alonso, Andres / Nunez, Antonio et al. | 2003
- 461
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Empirical model of the metal losses in integrated inductors [5117-50]del Pino, F. J. / Garcia, J. / Gonzalez, B. / Sendra, J. R. / Hernandez, A. / Garcia-Alonso, A. / Nunez, A. / SPIE et al. | 2003
- 470
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On-chip training for cellular neural networks using iterative annealing [5117-52]Feiden, D. / Tetzlaff, R. / SPIE et al. | 2003
- 470
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On-chip training for cellular neural networks using iterative annealingFeiden, Dirk / Tetzlaff, Ronald et al. | 2003
- 478
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Optimal design of a leak-proof SRAM cell using MCDM method [5117-53]Wang, Q. / Kang, S.-M. / SPIE et al. | 2003
- 478
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Optimal design of leak-proof SRAM cell using MCDM methodWang, Qi / Kang, Sung-Mo et al. | 2003
- 485
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Evolutionary design and FPGA implementation of digital filters [5117-54]Azzini, A. / Bettoni, M. / Liberali, V. / Rossi, R. / Tettamanzi, A. / SPIE et al. | 2003
- 485
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Evolutionary design and FPGA implementation of digital filtersAzzini, Antonia / Bettoni, Matteo / Liberali, Valentino / Rossi, Roberto / Tettamanzi, Andrea et al. | 2003
- 497
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Hierarchical test pattern composition to testing a foveal imager ASIC [5117-58]Gonzalez, M. / Salinas, J. R. / Coslado, F. J. / Camacho, P. / Sandoval, F. / SPIE et al. | 2003
- 497
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Hierarchical test pattern composition to testing a foveal imager ASICGonzalez, Martin / Salinas, Jose R. / Coslado, Francisco J. / Camacho, Pelegrin / Sandoval, Francisco et al. | 2003
- 506
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Experimental characterization of a synchronous frequency-hopping spread-spectrum transceiver for wireless optical communicationsPerez Suarez, Santiago T. / Rabadan, Jose A. / Delgado, Francisco A. / Velazquez, Jose R. / Perez Jimenez, Rafael et al. | 2003
- 506
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Experimental characterization of a synchronous frequency-hopping spread-spectrum transceiver for wireless optical communications [5117-59]Perez, S. T. / Rabadan, J. A. / Delgado, F. A. / Velazquez, J. R. / Jimenez, R. P. / SPIE et al. | 2003
- 515
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Analysis of current-mode flip-flops in CMOS technologiesJimenez, Raul / Parra, Pilar / Sanmartin, Pedro M. / Acosta, Antonio J. et al. | 2003
- 515
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Analysis of current-mode flip-flops in CMOS technologies [5117-60]Jimenez, R. / Parra, P. / Sanmartin, P. M. / Acosta, A. J. / SPIE et al. | 2003
- 527
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Temperature in HFETs when operating in DC [5117-62]Gonzalez, B. / Hernandez, A. / Garcia, J. / del Pino, F. J. / Sendra, J. R. / Nunez, A. / SPIE et al. | 2003
- 527
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Temperature in HFETs when operating in DCGonzalez, Benito / Hernandez, Antonio / Garcia, Javier / del Pino, F. J. / Nunez, Antonio / Sendra, Jose R. et al. | 2003
- 538
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Laser-induced structure defects and their use for (Cd,Hg)Te epitaxial layers and CdTe crystals properties modificationKotlyarchuk, Bohdan K. / Zaginey, Apollinariy O. / Syvenkyy, Yuriy E. et al. | 2003
- 538
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Laser-induced structure defects and their use for modification of the properties of (Cd,Hg)Te epitaxial layers and CdTe crystals [5117-63]Kotlyarchuk, B. K. / Zaginey, A. O. / Syvenkyy, Y. E. / SPIE et al. | 2003
- 547
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Design and simulation of an a-Si:H/GaAs HBT with improved DC and high-frequency characteristicsPezzimenti, Fortunato / Della Corte, Francesco G. et al. | 2003
- 547
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Design and simulation of an a-Si:H/GaAs HBT with improved DC and high-frequency characteristics [5117-65]Pezzimenti, F. / Corte, F. G. D. / SPIE et al. | 2003
- 557
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Diffusion barrier layer fabrication by plasma immersion ion implantation [5117-66]Kumar, M. / Rajkumar / Kumar, D. / George, P. J. / Paul, A. K. / SPIE et al. | 2003
- 557
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Diffusion barrier layer fabrication by plasma immersion ion implantationKumar, Mukesh / Rajkumar, - / Kumar, Dinesh / George, P. J. / Paul, A. K. et al. | 2003
- 564
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Switching-noise reduction in clock distribution in mixed-mode VLSI circuitsParra, Pilar / Acosta, Antonio J. / Valencia, Manuel et al. | 2003
- 564
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Switching-noise reduction in clock distribution in mixed-mode VLSI circuits [5117-67]Parra, P. / Acosta, A. J. / Valencia, M. / SPIE et al. | 2003
- 574
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Integrated optical scheme for residue-based logic operationsGhosh, Partha et al. | 2003
- 574
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Integrated optical scheme for residue-based logic operations [5117-68]Ghosh, P. / SPIE et al. | 2003
- 581
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Digital optical switch based on amorphous silicon waveguideSirleto, Luigi / Iodice, Mario / Della Corte, Francesco G. / Rendina, Ivo et al. | 2003
- 581
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Digital optical switch based on amorphous silicon waveguide [5117-69]Sirleto, L. / Iodice, M. / Corte, F. G. D. / Rendina, I. / SPIE et al. | 2003
- 589
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1.55-µm reflection-type optical waveguide switch based on thermo-optic effectCantore, Francesca L. / Della Corte, Francesco G. et al. | 2003
- 589
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1.55-mum reflection-type optical waveguide switch based on thermo-optic effect [5117-70]Cantore, F. L. / Corte, F. G. D. / SPIE et al. | 2003
- 598
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Comparison of CMOS and BiCMOS optical receiver SoCsZimmermann, Horst / Swoboda, Robert / Schneider, Kerstin / Knorr, Johannes et al. | 2003
- 598
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Comparison of CMOS and BiCMOS optical receiver SoCs [5117-71]Zimmermann, H. / Swoboda, R. / Schneider, K. / Knorr, J. / SPIE et al. | 2003
- 610
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Method of generating trustworthy performance estimations for soft IPs [5117-72]Marrero, M. / Carballo, P. P. / Nunez, A. / SPIE et al. | 2003
- 610
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Method of generating trustworthy performance estimations for soft-IPsMarrero, Margarita / Carballo, Pedro P. / Nunez, Antonio et al. | 2003
- 618
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Turbo decoder core design for system development [5117-35]Chen, X. / Yao, Q. / Liu, P. / SPIE et al. | 2003
- 618
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Turbo decoder core design for system developmentChen, Xiaoyi / Yao, Qingdong / Liu, Peng et al. | 2003