Trends in systematic nonparticle yield loss mechanisms and the implication for IC design [5040-41] (Englisch)
- Neue Suche nach: Berglund, C. N.
- Neue Suche nach: SPIE
- Neue Suche nach: Berglund, C. N.
- Neue Suche nach: Starikov, A.
- Neue Suche nach: SPIE
In:
Design and process integration for microelecronic manufacturing
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395-403
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2003
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Print
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Titel:Trends in systematic nonparticle yield loss mechanisms and the implication for IC design [5040-41]
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Beteiligte:
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Kongress:Conference; 2nd, Design and process integration for microelecronic manufacturing ; 2003 ; Santa Clara, CA
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Erschienen in:PROCEEDINGS- SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING ; 5042 ; 395-403
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Verlag:
- Neue Suche nach: SPIE
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Erscheinungsdatum:01.01.2003
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Format / Umfang:9 pages
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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Layout optimization at the pinnacle of optical lithography (Invited Paper) [5042-01]Liebmann, L. W. / Northrop, G. A. / Culp, J. / Sigal, L. / Barish, A. / Fonseca, C. A. / SPIE et al. | 2003
- 1
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Layout optimization at the pinnacle of optical lithographyLiebmann, Lars W. / Northrop, Greg A. / Culp, James / Sigal, Leon / Barish, Arnold / Fonseca, Carlos A. et al. | 2003
- 15
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Dense-only phase-shift template lithography [5042-02]Fritze, M. / Tyrrell, B. / Mallen, R. D. / Wheeler, B. / Rhyins, P. D. / Martin, P. M. / SPIE et al. | 2003
- 15
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Dense only phase-shift template lithographyFritze, Michael / Tyrrell, Brian / Mallen, Renee D. / Wheeler, Bruce / Rhyins, Peter D. / Martin, Patrick M. et al. | 2003
- 30
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Assessing technology options for 65-nm logic circuitsPramanik, Dipankar / Cote, Michel L. / Beaudette, Kevin / Axelrad, Valery et al. | 2003
- 30
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Assessing technology options for 65-nm logic circuits [5042-03]Pramanik, D. / Cote, M. L. / Beaudette, K. / Axelrad, V. / SPIE et al. | 2003
- 42
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Generalization of the photo process window and its application to OPC test pattern designEisenmann, Hans / Peter, Kai / Strojwas, Andrzej J. et al. | 2003
- 42
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Generalization of the photo process window and its application to OPC test pattern design [5042-05]Eisenmann, H. / Peter, K. / Strojwas, A. J. / SPIE et al. | 2003
- 51
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Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETsPack, Robert C. / Axelrad, Valery / Shibkov, Andrei / Boksha, Victor V. / Huckabay, Judy A. / Salik, Rachid / Staud, Wolfgang / Wang, Ruoping / Grobman, Warren D. et al. | 2003
- 51
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Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs [5042-35]Pack, R. C. / Axelrad, V. / Shibkov, A. / Boksha, V. V. / Huckabay, J. A. / Salik, R. / Staud, W. / Wang, R. / Grobman, W. D. / SPIE et al. | 2003
- 63
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Technology CAD for integrated circuit fabrication technology development and technology transfer [5042-06]Saha, S. / SPIE et al. | 2003
- 63
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Technology CAD for integrated circuit fabrication technology development and technology transferSaha, Samar et al. | 2003
- 75
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Performance-impact limited-area fill synthesisChen, Yu / Gupta, Puneet / Kahng, Andrew B. et al. | 2003
- 75
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Performance-impact limited-area fill synthesis [5042-07]Chen, Y. / Gupta, P. / Kahng, A. B. / SPIE et al. | 2003
- 87
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Simulation-based data processing using repeated pattern identificationZhang, Youping et al. | 2003
- 87
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Simulation-based data processing using repeated pattern identification [5042-08]Zhang, Y. / SPIE et al. | 2003
- 99
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Model-assisted placement of subresolution assist features: experimental resultsBrist, Travis E. / Torres, Juan A. et al. | 2003
- 99
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Model-assisted placement of subresolution assist features: experimental results [5042-09]Brist, T. E. / Torres, J. A. / SPIE et al. | 2003
- 107
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OPC on real-world circuitry [5042-10]O Brien, S. C. / Aton, T. / Mason, M. E. / Vickery, C. / Randall, J. N. / SPIE et al. | 2003
- 107
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OPC on real-world circuitryO'Brien, Sean C. / Aton, Tom / Mason, Mark E. / Vickery, Carl / Randall, John N. et al. | 2003
- 116
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OPC methods to improve image slope and process windowCobb, Nicolas B. / Granik, Yuri et al. | 2003
- 116
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OPC methods to improve image slope and process window [5042-41]Cobb, N. B. / Granik, Y. / SPIE et al. | 2003
- 126
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Lithography-driven layout of logic cells for 65-nm node [5042-13]Pramanik, D. / Cote, M. L. / SPIE et al. | 2003
- 126
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Lithography-driven layout of logic cells for 65-nm nodePramanik, Dipankar / Cote, Michel L. et al. | 2003
- 135
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Improved manufacturability by OPC based on defocus data [5042-14]Thiele, J. / Anke, I. / Haffner, H. / Semmler, A. / SPIE et al. | 2003
- 135
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Improved manufacturability by OPC based on defocus dataThiele, Jorg / Anke, Ines / Haffner, Henning / Semmler, Armin et al. | 2003
- 144
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LithoScope: an advanced physical modeling system for mask layout data verificationQian, Qi-De et al. | 2003
- 144
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LithoScope: an advanced physical modeling system for mask data verification [5042-15]Qian, Q.-D. / SPIE et al. | 2003
- 153
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Effective multicutline QUASAR illumination optimization for SRAM and logicBrist, Travis E. / Bailey, George E. et al. | 2003
- 153
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Effective multicutline QUASAR illumination optimization for SRAM and logic [5042-37]Brist, T. E. / Bailey, G. E. / SPIE et al. | 2003
- 160
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Investigation of product design weaknesses using model-based OPC sensitivity analysis [5042-17]Postnikov, S. V. / Lucas, K. / Garza, C. M. / Wimmer, K. / LaCour, P. / Word, J. C. / SPIE et al. | 2003
- 160
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Investigation of product design weaknesses using model-based OPC sensitivity analysisPostnikov, Sergei V. / Lucas, Kevin / Garza, Cesar M. / Wimmer, Karl / LaCour, Patrick / Word, James C. et al. | 2003
- 172
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Device characteristics of sub-20-nm silicon nanotransistorsSaha, Samar et al. | 2003
- 172
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Device characteristics of sub-20-nm silicon nanotransistors [5042-18]Saha, S. / SPIE et al. | 2003
- 180
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NBTI improvement for pMOS by Cl-contained 1^s^t oxidation in 20A/65A dual-nitrided gate oxide of 0.13-mum CMOS technology [5042-19]Hao, C.-C. / Chi, M.-H. / Chen, C.-C. / Lin, H.-J. / Lin, Y.-F. / Hsieh, C. H. / Lee, C. H. / Chang, K. H. / Wu, H. T. / Shen, C.-H. et al. | 2003
- 180
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NBTI improvement for pMOS by Cl-contained 1stoxidation in 20A/65A dual-nitrided gate oxide of 0.13-μm CMOS technologyHao, Ching-Chen / Chi, Min-Hwa / Chen, Chao-Chi / Lin, Hung-Jen / Lin, Yu-Fang / Hsieh, C. H. / Lee, Chih-Hsiung / Chang, Kuang-Hui / Wu, H. T. / Shen, Chin-Heng et al. | 2003
- 188
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Library-based process test vehicle design framework [5042-20]Doong, K. Y.-Y. / Hung, L.-J. / Ho, S. / Lin, S. C. / Young, K. L. / SPIE et al. | 2003
- 188
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Library-based process test vehicle design frameworkDoong, Kelvin Y. / Hung, L.-J. / Ho, Susan / Lin, S. C. / Young, K. L. et al. | 2003
- 197
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Design-to-process integration: optimizing 130-nm X architecture manufacturing [5042-21]Dean, R. / Malhotra, V. K. / King, N. / Sanie, M. / MacDonald, S. S. / Jordan, J. D. / Hirukawa, S. / SPIE et al. | 2003
- 197
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Design-to-process integration: optimizing 130-nm X architecture manufacturingDean, Robert / Malhotra, Vinod K. / King, Nahid / Sanie, Michael / MacDonald, Susan S. / Jordan, James D. / Hirukawa, Shigeru et al. | 2003
- 205
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Using the CODE technique to print complex two-dimensional structures in a 90-nm ground rule processManakli, Serdar / Trouiller, Yorick / Toublan, Olivier / Schiavone, Patrick / Rody, Yves F. / Goirand, Pierre Jerome et al. | 2003
- 205
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Using the CODE technique to print complex two-dimensional structures in a 90-nm ground rule process [5042-22]Manakli, S. / Trouiller, Y. / Toublan, O. / Schiavone, P. / Rody, Y. F. / Goirand, P. J. / SPIE et al. | 2003
- 214
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New stream format: progress report on containing data size explosion [5042-24]LaCour, P. / Reich, A. J. / Nakagawa, K. H. / Schulze, S. F. / Grodd, L. / SPIE et al. | 2003
- 214
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New stream format: progress report on containing data size explosionLaCour, Patrick / Reich, Alfred J. / Nakagawa, Kent H. / Schulze, Steffen F. / Grodd, Laurence et al. | 2003
- 222
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Optimization of the data preparation for variable-shape beam mask writing machinesSchulze, Steffen F. / LaCour, Patrick et al. | 2003
- 222
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Optimization of the data preparation for variable-shaped beam mask writing machines [5042-25]Schulze, S. F. / LaCour, P. / SPIE et al. | 2003
- 233
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Compression algorithms for dummy-fill VLSI layout dataEllis, Robert B. / Kahng, Andrew B. / Zheng, Yuhong et al. | 2003
- 233
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Compression algorithms for dummy-fill VLSI layout data [5042-26]Ellis, R. B. / Kahng, A. B. / Zheng, Y. / SPIE et al. | 2003
- 246
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Characterization and modeling of intradie variation and its applications to design for manufacturability [5042-11]Saxena, S. / Guardiani, C. / Quarantelli, M. / Dragone, N. / Minehane, S. / McNamara, P. / Babcock, J. A. / SPIE et al. | 2003
- 246
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Characterization and modeling of intradie variation and its applications to design for manufacturabilitySaxena, Sharad / Guardiani, Carlo / Quarantelli, Michele / Dragone, Nicola / Minehane, Sean / McNamara, Patrick / Babcock, Jeff A. et al. | 2003
- 251
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Applications of image diagnostics to metrology quality assurance and process control [5042-39]Allgair, J. A. / Boksha, V. V. / Bunday, B. D. / Diebold, A. C. / Cole, D. C. / Davidson, M. P. / Hutcheson, J. D. / Gurnell, A. W. / Joy, D. C. / McIntosh, J. M. et al. | 2003
- 251
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Applications of image diagnostics to metrology quality assurance and process controlAllgair, John A. / Boksha, Victor V. / Bunday, Benjamin D. / Diebold, Alain C. / Cole, Daniel C. / Davidson, Mark P. / Hutcheson, Jerry D. / Gurnell, Andrew W. / Joy, David C. / McIntosh, John M. et al. | 2003
- 278
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Creation and verification of phase-compliance SoC IP for the fabless COT designersMalhotra, Vinod K. / King, Nahid / Leung, Raymond / Zia, Zain / Jeeawoody, Shakeel et al. | 2003
- 278
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Creation and verification of phase-compliant SoC hard IP for the fabless COT designers [5042-29]Malhotra, V. K. / King, N. / Leung, R. / Zia, Z. / Jeawoody, S. / SPIE et al. | 2003
- 286
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Statistical data assessment for optimization of the data preparation and manufacturing [5042-30]Schulze, S. F. / LaCour, P. / SPIE et al. | 2003
- 286
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Statistical data assessment for optimization of data preparation and manufacturingSchulze, Steffen F. / LaCour, Patrick et al. | 2003
- 293
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Lithographic tradeoffs between different assist feature OPC design strategiesWord, James C. / Zhu, Siuhua et al. | 2003
- 293
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Lithographic tradeoffs between different assist feature OPC design strategies [5042-31]Word, J. C. / Zhu, S. / SPIE et al. | 2003
- 305
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Resolution enhancement technology requirements for 65-nm node [5042-32]Kroyan, A. / Liu, H. / SPIE et al. | 2003
- 305
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Resolution enhancement technology requirements for 65-nm nodeKroyan, Armen / Liu, Hua-Yu et al. | 2003
- 314
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PsmLint: bringing AltPSM benefits to the IC design stageGhosh, Pradiptya / Kang, Chung-Shin / Sanie, Michael / Huckabay, Judy A. et al. | 2003
- 314
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PsmLint: bringing AltPSM benefits to the IC design stage [5042-33]Ghosh, P. / Kang, C. / Sanie, M. / Huckabay, J. A. / SPIE et al. | 2003
- 326
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Optimizing manufacturability for the 65-nm process nodePramanik, Dipankar / Cote, Michel L. et al. | 2003
- 326
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Optimizing manufacturability for the 65-nm process node [5042-34]Pramanik, D. / Cote, M. L. / SPIE et al. | 2003
- 334
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Optimized cobalt silicide formation through etch process improvementsTucker, David S. / Yang, Richard / Maines, Heather et al. | 2003
- 334
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Optimized cobalt silicide formation through etch process improvements [5042-36]Tucker, D. S. / Yang, R. / Maines, H. / SPIE et al. | 2003
- 341
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Modification of existing chip layout for yield and reliability improvement by computer-aided design tools [5042-38]Li, M.-J. / Maturi, S. / Dixit, P. / SPIE et al. | 2003
- 341
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Modification of existing chip layout for yield and reliability improvement by computer-aided design toolsLi, Mu-Jing / Maturi, Suryanarayana / Dixit, Pankaj et al. | 2003
- 346
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Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-mum CMOS technology [5042-28]Lee, T.-K. / Wang, Y.-C. / Chi, M.-H. / Lu, C. Y. / Hsieh, C. H. / Liu, R. G. / Liao, H. J. / Yang, S. S. / Chang, C.-H. / SPIE et al. | 2003
- 353
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Process, design, and optical proximity correction requirements for the 65-nm device generation [5040-37]Lucas, K. / Montgomery, P. / Litt, L. C. / Conley, W. / Postnikov, S. V. / Wu, W. / Yuan, C.-M. / Olivares, M. / Strozewski, K. / Carter, R. L. et al. | 2003
- 365
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Optical rule checking for proximity-corrected mask shapes [5040-38]Mukherjee, M. / Baum, Z. / Nickel, J. / Dunham, T. G. / SPIE et al. | 2003
- 376
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Failure prediction across process window for robust OPC [5040-39]Shang, S. D. / Granik, Y. / Cobb, N. B. / Maurer, W. / Cui, Y. / Liebmann, L. W. / Oberschmidt, J. M. / Singh, R. N. / Vampatella, B. R. / SPIE et al. | 2003
- 386
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A methodology to calculate line-end correction feature performance as a function of reticle cost [5040-40]Melvin, L. S. / Shiely, J. P. / Rieger, M. L. / Painter, B. / SPIE et al. | 2003
- 395
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Trends in systematic nonparticle yield loss mechanisms and the implication for IC design [5040-41]Berglund, C. N. / SPIE et al. | 2003
- 404
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Impact of inter-mask CD error on OPC accuracy in resolution of 90 nm and below [5040-96]Ozawa, K. / Sato, S. / Ohnuma, H. / SPIE et al. | 2003
- 450
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Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-μm CMOS technologyLee, Tzy-Kuang / Wang, Yao-Ching / Chi, Min-hwa / Lu, C. Y. / Hsieh, C. H. / Liu, R. G. / Liao, H. J. / Yang, S. S. / Chang, Chih-Hao et al. | 2003