15.1 - 3:25 p.m. New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical Capacitor (Englisch)
- Neue Suche nach: Nagel, N.
- Neue Suche nach: Bruchhaus, R.
- Neue Suche nach: Hornik, K.
- Neue Suche nach: Egger, U.
- Neue Suche nach: Zhuang, H.
- Neue Suche nach: Joachim, H.-O.
- Neue Suche nach: Roehr, T.
- Neue Suche nach: Beitel, G.
- Neue Suche nach: Ozaki, T.
- Neue Suche nach: Kunishima, I.
- Neue Suche nach: IEEE
- Neue Suche nach: Nagel, N.
- Neue Suche nach: Bruchhaus, R.
- Neue Suche nach: Hornik, K.
- Neue Suche nach: Egger, U.
- Neue Suche nach: Zhuang, H.
- Neue Suche nach: Joachim, H.-O.
- Neue Suche nach: Roehr, T.
- Neue Suche nach: Beitel, G.
- Neue Suche nach: Ozaki, T.
- Neue Suche nach: Kunishima, I.
- Neue Suche nach: IEEE
In:
VLSI technology
2004
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146-147
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2004
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:15.1 - 3:25 p.m. New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical Capacitor
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Beteiligte:Nagel, N. ( Autor:in ) / Bruchhaus, R. ( Autor:in ) / Hornik, K. ( Autor:in ) / Egger, U. ( Autor:in ) / Zhuang, H. ( Autor:in ) / Joachim, H.-O. ( Autor:in ) / Roehr, T. ( Autor:in ) / Beitel, G. ( Autor:in ) / Ozaki, T. ( Autor:in ) / Kunishima, I. ( Autor:in )
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Kongress:digest of technical papers.; Symposium, VLSI technology ; 2004 ; Honolulu, HI
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Erschienen in:VLSI technology , 2004 ; 146-147SYMPOSIUM ON VLSI TECHNOLOGY , 2004 ; 146-147
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Verlag:
- Neue Suche nach: IEEE,
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Erscheinungsdatum:01.01.2004
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Format / Umfang:2 pages
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Anmerkungen:IEEE cat no 04CH37526
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Front Inside Cover [blank]| 2004
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Back Inside Cover [blank]| 2004
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SESSION 1 - Plenary Session| 2004
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Challenges and opportunities in the broadband connected worldSamueli, H. et al. | 2004
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1.1 - 8:30 a.m. Challenges and Opportunities in the Broadband Connected WorldSamueli, H. / IEEE et al. | 2004
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1.2 - 9:15 a.m Device Challenges and OpportunitiesHu, C. / IEEE et al. | 2004
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Device challenges and opportunitiesChenming Hu, et al. | 2004
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Breaker page| 2004
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SESSION 2 - Advanced CMOS Technology| 2004
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2.1 - 10:20 a.m. 45nm Node Planar-SOI Technology with 0.296mum^2 6T-SRAM CellYang, F.-L. / Huang, C.-C. / Chung, T.-X. / Chen, H.-Y. / Chang, C.-Y. / Chen, H.-W. / Lee, D.-H. / Liu, S.-D. / Chen, K.-H. / IEEE et al. | 2004
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45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cellFu-Liang Yang, / Cheng-Chuan Huang, / Chien-Chao Huang, / Tang-Xuan Chung, / Hou-Yu Chen, / Chang-Yun Chang, / Hung-Wei Chen, / Di-Hong Lee, / Sheng-Da Liu, / Kuang-Hsin Chen, et al. | 2004
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Low cost 65nm CMOS platform for Low Power & General Purpose applicationsArnaud, F. / Duriez, B. / Tavel, B. / Pain, L. / Todeschini, J. / Jurdit, M. / Laplanche, Y. / Boeuf, F. / Salvetti, F. / Lenoble, D. et al. | 2004
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2.3 - 11:10 a.m. 15nm CMOS Platform Technology (CMOS6) with High Density Embedded MemoriesIwai, M. / Oishi, A. / Sanuki, T. / Takegawa, Y. / Komoda, T. / Morimasa, Y. / Ishimaru, K. / Takayanagi, M. / Eguchi, K. / Matsushita, D. et al. | 2004
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45nm CMOS platform technology (CMOS6) with high density embedded memoriesIwai, M. / Oishi, A. / Sanuki, T. / Takegawa, Y. / Komoda, T. / Morimasa, Y. / Ishimaru, K. / Takayanagi, M. / Eguchi, K. / Matsushita, D. et al. | 2004
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2.4 - 11:35 a.m. Transistor Optimization for Leakage Power Management in a 65nm CMOS Technology for Wireless and Mobile ApplicationsZhao, S. / Chatterjee, A. / Tang, S. / Yoon, J. / Crank, S. / Bu, H. / Houston, T. / Sadra, K. / Jain, A. / Wang, Y. et al. | 2004
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Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applicationsZhao, S. / Chatterjee, A. / Tang, S. / Yoon, J. / Crank, S. / Bu, H. / Houston, T. / Sadra, K. / Jain, A. / Wang, Y. et al. | 2004
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SESSION 3 - Emerging Memory Technologies I| 2004
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Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applicationsPellizzer, F. / Pirovano, A. / Ottogalli, F. / Magistretti, M. / Scaravaggi, M. / Zuliani, P. / Tosi, M. / Benvenuti, A. / Besana, P. / Cadeo, S. et al. | 2004
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3.1 - 10:20 a.m. Novel muTrench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory ApplicationsPellizzer, F. / Pirovano, A. / Ottogalli, F. / Magistretti, M. / Scaravaggi, M. / Zuliani, P. / Tosi, M. / Benvenuti, A. / Besana, P. / Cadeo, S. et al. | 2004
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Full integration and cell characteristics for 64Mb nonvolatile PRAMLee, S.H. / Hwang, Y.N. / Lee, S.Y. / Ryoo, K.C. / Ahn, S.J. / Koo, H.C. / Jeong, C.W. / Kim, Y.-T. / Koh, G.H. / Jeong, G.T. et al. | 2004
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3.2 - 10:45 a.m. Full Integration and Cell Characteristics for 64Mb Nonvolatile PRAMLee, S. H. / Hwang, Y. N. / Lee, S. Y. / Ryoo, K. C. / Ahn, S. J. / Koo, H. C. / Jeong, C. W. / Kim, Y.-T. / Koh, G. H. / Jeong, G. T. et al. | 2004
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3.3 - 11:10 a.m. A Study for 0.18um High-Density MRAMMotoyoshi, M. / Yamamura, I. / Ohtsuka, W. / Shouji, M. / Yamagishi, H. / Nakamura, M. / Yamada, H. / Tai, K. / Kikutani, T. / Sagara, T. et al. | 2004
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A study for 0.18 /spl mu/m high-density MRAMMotoyoshi, M. / Yamamura, I. / Ohtsuka, W. / Shouji, M. / Yamagishi, H. / Nakamura, M. / Yamada, H. / Tai, K. / Kikutani, T. / Sagara, T. et al. | 2004
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MRAM with novel shaped cell using synthetic anti-ferromagnetic free layerHa, Y.K. / Lee, J.E. / Kim, H.-J. / Bae, J.S. / Oh, S.C. / Nam, K.T. / Park, S.O. / Lee, N.I. / Kang, H.K. / Chung, U.-I. et al. | 2004
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3.4 - 11:35 a.m. MRAM with Novel Shaped Cell Using Synthetic Anti-Ferromagnetic Free LayerHa, Y. K. / Lee, J. E. / Kim, H.-J. / Bae, J. S. / Oh, S. C. / Nam, K. T. / Park, S. O. / Lee, N. I. / Kang, H. K. / Chung, U.-I. et al. | 2004
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SESSION 4 - DRAM I| 2004
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4.1 - 1:30 p.m. A 78nm 6F^2 DRAM Technology for Multigigabit DensitiesFishburn, F. / Busch, B. / Dale, J. / Hwang, D. / Lane, R. / McDaniel, T. / Southwick, S. / Turi, R. / Wang, H. / Tran, L. et al. | 2004
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A 78nm 6F/sup 2/ DRAM technology for multigigabit densitiesFishburn, F. / Busch, B. / Dale, J. / Hwang, D. / Lane, R. / McDaniel, T. / Southwick, S. / Turi, R. / Wang, H. / Tran, L. et al. | 2004
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4.2 - 1:55 p.m. 80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated Cell Array Transistor (PiCAT)Yeo, K. H. / Oh, C. W. / Kim, S.-M. / Kim, M.-S. / Lee, C.-S. / Lee, S.-Y. / Li, M. / Cho, H.-J. / Yoon, E.-J. / Kim, S.-H. et al. | 2004
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80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)Kyoung Hwan Yeo, / Chang Woo Oh, / Sung-Min Kim, / Min-Sang Kim, / Chang-Sub Lee, / Sung-Young Lee, / Ming Li, / Hye-Jin Cho, / Eun-Jung Yoon, / Sung-Hwan Kim, et al. | 2004
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4.3 - 2:20 p.m. Integrated Device and Process Technology for Sub-70nm Low Power DRAMCho, C. / Song, S. / Kim, S. / Jang, S. / Lee, S. / Kim, H. / Park, J. / Bae, J. / Ahn, Y. / Kim, Y. et al. | 2004
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Integrated device and process technology for sub-70nm low power DRAMChanghyun Cho, / Sangho Song, / Sangho Kim, / Sungho Jang, / Seongsam Lee, / Hyungtak Kim, / Junwoong Park, / Junshik Bae, / Yongsuk Ahn, / Yungi Kim, et al. | 2004
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Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyondPark, J.M. / Hwang, Y.S. / Shin, D.W. / Huh, M. / Kim, D.H. / Hwang, H.K. / Oh, H.J. / Song, J.W. / Kang, N.J. / Lee, B.H. et al. | 2004
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4.4 - 2:45 p.m. Novel Robust Cell Capacitor (Leaning Exterminated Ring Type Insulator) and New Storage Node Contact (Top Spacer Contact) for 70nm DRAM Technology and BeyondPark, J. M. / Hwang, Y. S. / Shin, D. W. / Huh, M. / Kim, D. H. / Hwang, H. K. / Oh, H. J. / Song, J. W. / Kang, N. J. / Lee, B. H. et al. | 2004
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SESSION 5 - Advanced Transistor Technology I| 2004
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Fully working 1.10 /spl mu/m/sup 2/ embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applicationsHyuk-Ju Ryu, / Woo-Young Chung, / You-Jean Jang, / Yong-Jun Lee, / Hyung-Seok Jung, / Chang-Bong Oh, / Hee-Sung Kang, / Young-Wug Kim, et al. | 2004
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5.1 - 1:30 p.m. Fully Working 1.10mum^2 Embedded 6T-SRAM Technology with High-k Gate Dielectric Device for Ultra Low Power ApplicationsRyu, H.-J. / Chung, W.-Y. / Jang, Y.-J. / Lee, Y.-J. / Jung, H.-S. / Oh, C.-B. / Kang, H.-S. / Kim, Y.-W. / IEEE et al. | 2004
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5.2 - 1:55 p.m. A 65nm-node LSTP (Low Standby Power) Poly-Si/a-Si/HfSiON Transistor with High I~o~n-I~s~t~a~n~d~b~y Ratio and ReliabilityYasuda, Y. / Kimizuka, N. / Iwamoto, T. / Fujieda, S. / Ogura, T. / Watanabe, H. / Tatsumi, T. / Yamamoto, I. / Ito, K. / IEEE et al. | 2004
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A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliabilityYasuda, Y. / Kimizuka, N. / Iwamoto, T. / Fujieda, S. / Ogura, T. / Watanabe, H. / Tatsumi, T. / Yamamoto, I. / Ito, K. / Yamagata, Y. et al. | 2004
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5.3 - 2:20 p.m. 55nm High Mobility SiGe(:C) pMOSFETs with HfO~2 Gate Dielectric and TlN Metal Gate for Advanced CMOSWeber, O. / Ducroquet, F. / Ernst, T. / Andrieu, F. / Damlencourt, J.-F. / Hartmann, J.-M. / Guillaumot, B. / Papon, A.-M. / Dansas, H. / Brevard, L. et al. | 2004
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55nm high mobility SiGe(:C) pMOSFETs with HfO/sub 2/ gate dielectric and TiN metal gate for advanced CMOSWeber, O. / Ducroquet, F. / Ernst, T. / Andrieu, F. / Damlencourt, J.-F. / Hartmann, J.-M. / Guillaumot, B. / Papon, A.-M. / Dansas, H. / Brevard, L. et al. | 2004
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5.4 - 2:45 p.m. Systematic Study of pFET V~t with Hf-Based Gate Stacks with Poly-Si and FUSI GatesCartier, E. / Narayanan, V. / Gusev, E. P. / Jamison, P. / Linder, B. / Steen, M. / Chan, K. K. / Frank, M. / Bojarczuk, N. / Copel, M. et al. | 2004
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Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gatesCartier, E. / Narayanan, V. / Gusev, E.P. / Jamison, P. / Linder, B. / Steen, M. / Chan, K.K. / Frank, M. / Bojarczuk, N. / Copel, M. et al. | 2004
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SESSION 6 - Strain Enhanced CMOS| 2004
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35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOSChidambaram, P.R. / Smith, B.A. / Hall, L.H. / Bu, H. / Chakravarthi, S. / Kim, Y. / Samoilov, A.V. / Kim, A.T. / Jones, P.J. / Irwin, R.B. et al. | 2004
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6.1 - 3:25 p.m. 35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOSChidambaram, P. R. / Smith, B. A. / Hall, L. H. / Bu, H. / Chakravarthi, S. / Kim, Y. / Samoilov, A. V. / Kim, A. T. / Jones, P. J. / Irwin, R. B. et al. | 2004
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6.2 - 3:50 p.m. Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS TechnologyMistry, K. / Armstrong, M. / Auth, C. / Cea, S. / Coan, T. / Ghani, T. / Hoffmann, T. / Murthy, A. / Sandford, J. / Shaheed, R. et al. | 2004
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Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technologyMistry, K. / Armstrong, M. / Auth, C. / Cea, S. / Coan, T. / Ghani, T. / Hoffmann, T. / Murthy, A. / Sandford, J. / Shaheed, R. et al. | 2004
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Electron and hole mobility enhancements in sub-10 nm-thick strained silicon directly on insulator fabricated by a bond and etch-back techniqueAberg, I. / Olubuyide, O.O. / Chleirigh, C.N. / Lauer, I. / Antoniadis, D.A. / Li, J. / Hull, R. / Hoyt, J.L. et al. | 2004
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6.3 - 4:15 p.m. Electron and Hole Mobility Enhancements in Sub-10 nm-thick Strained Silicon Directly on Insulator Fabricated by a Bond and Etch-back TechniqueAberg, I. / Olubuyide, O. O. / Chleirigh, C. N. / Lauer, I. / Antoniadis, D. A. / Li, J. / Hull, R. / Hoyt, J. L. / IEEE et al. | 2004
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MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology nodePidin, S. / Mori, T. / Nakamura, R. / Saiki, T. / Tanabe, R. / Satoh, S. / Kase, M. / Hashimoto, K. / Sugii, T. et al. | 2004
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6.4 - 4:40 p.m. MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology NodePidin, S. / Mori, T. / Nakamura, R. / Saiki, T. / Tanabe, R. / Satoh, S. / Kase, M. / Hashimoto, K. / Sugii, T. / IEEE et al. | 2004
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6.5 - 5:05 p.m. Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device ApplicationChen, C.-H. / Lee, T. L. / Hou, T. H. / Chen, C. L. / Chen, C. C. / Hsu, J. W. / Cheng, K. L. / Chiu, Y. H. / Tao, H. J. / Jin, Y. et al. | 2004
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Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device applicationChien-Hao Chen, / Lee, T.L. / Hou, T.H. / Chen, C.L. / Chen, C.C. / Hsu, J.W. / Cheng, K.L. / Chiu, Y.H. / Tao, H.J. / Jin, Y. et al. | 2004
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SESSION 7 - Advanced Interconnects| 2004
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7.1 - 3.25 p.m. Highly Reliable, 65 nm-node Cu Dual Damascene Interconnects with Full Porous-SiOCH (k=2.5) Films for Low-Power ASICsUeki, M. / Narihiro, M. / Ohtake, H. / Tagami, M. / Tada, M. / Ito, F. / Harada, Y. / Abe, M. / Inoue, N. / Arai, K. et al. | 2004
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Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICsUeki, M. / Narihiro, M. / Ohtake, H. / Tagami, M. / Tada, M. / Ito, F. / Harada, Y. / Abe, M. / Inoue, N. / Arai, K. et al. | 2004
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7.2 - 3:50 p.m. Integration of Interconnect Process Highly Manufacturable for 65nm CMOS Platform Technology (CMOS5)Honda, K. / Kanda, M. / Ishizuka, R. / Moriuchi, Y. / Matsubara, Y. / Habu, M. / Yoshida, T. / Matsuda, S. / Kittaka, H. / Miyajima, H. et al. | 2004
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Integration of interconnect process highly manufacturable for 65nm CMOS platform technology (CMOS5)Honda, K. / Kanda, M. / Ishizuka, R. / Moriuchi, Y. / Matsubara, Y. / Habu, M. / Yoshida, T. / Matsuda, S. / Kittaka, H. / Miyajima, H. et al. | 2004
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Process integration of CVD Cu seed using ALD Ru glue layer for sub-65nm Cu interconnectChoi, S.-M. / Park, K.-C. / Suh, B.-S. / Kim, I.-R. / Kang, H.-K. / Suh, K.-P. / Park, H.-S. / Ha, J.-S. / Joo, D.-K. et al. | 2004
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7.3 - 4:15 p.m. Process Integration of CVD Cu Seed Using ALD Ru Glue Layer for Sub-65nm Cu InterconnectChoi, S.-M. / Park, K.-C. / Suh, B.-S. / Kim, I.-R. / Kang, H.-K. / Suh, K.-P. / Park, H.-S. / Ha, J.-S. / Joo, D.-K. / IEEE et al. | 2004
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7.4 - 4:40 p.m. Reliability Robustness of 65nm BEOL Cu Damascene Interconnects Using Porous CVD Low-k Dielectrics with k = 2.2Lin, K. C. / Lu, Y. C. / Li, L. P. / Chen, B. T. / Chang, H. L. / Lu, H. H. / Jeng, S. M. / Jang, S. M. / Liang, M. S. / IEEE et al. | 2004
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Reliability robustness of 65nm BEOL Cu damascene interconnects using porous CVD low-k dielectrics with k = 2.2Lin, K.C. / Lu, Y.C. / Li, L.P. / Chen, B.T. / Chang, H.L. / Lu, H.H. / Jeng, S.M. / Jang, S.M. / Liang, M.S. et al. | 2004
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Damage-free CMP towards 32nm-node porous low-k (k = 1.6)/Cu integrationKondo, S. / Yoon, B.U. / Lee, S.G. / Tokitoh, S. / Misawa, K. / Yoshie, T. / Ohashi, N. / Kobayashi, N. et al. | 2004
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7.5 - 5:05 p.m. Damage-Free CMP Towards 32nm-node Porous Low-k (k=1.6)/Cu IntegrationKondo, S. / Yoon, B. U. / Lee, S. G. / Tokitoh, S. / Misawa, K. / Yoshie, T. / Ohashi, N. / Kobayashi, N. / IEEE et al. | 2004
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SESSION 8 - Flash Memory I| 2004
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Vertical floating-gate 4.5F/sup 2/ split-gate NOR flash memory at 110nm nodeLee, D. / Tsui, F. / Jeng-Wei Yang, / Feng Gao, / Wen-Juei Lu, / Yeeheng Lee, / Chi-Tsai Chen, / Huang, V. / Pin-Yao Wang, / Liu, M.H. et al. | 2004
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8.1 - 8:00 a.m. Vertical Floating-Gate 4.5F^2 Split-Gate NOR Flash Memory at 110nm NodeLee, D. / Tsui, F. / Yang, J.-W. / Gao, F. / Lu, W.-J. / Lee, Y. / Chen, C.-T. / Huang, V. / Wang, P.-Y. / Liu, M. H. et al. | 2004
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8.2 - 8:25 a.m. Scanrom, a Novel Non-Volatile Memory Cell storing 9 BitsRosmeulen, M. / Van Houdt, J. / Haspeslagh, L. / De Meyer, K. / IEEE et al. | 2004
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Scanrom, a novel non-volatile memory cell storing 9 bitsRosmeulen, M. / Van Houdt, J. / Haspeslagh, L. / De Meyer, K. et al. | 2004
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110nm NROM technology for code and data flash productsWiller, J. / Ludwig, C. / Deppe, J. / Kleint, C. / Riedel, S. / Sachse, J.-U. / Krause, M. / Mikalo, R. / Kamienski, E.S. / Parascandola, S. et al. | 2004
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8.3 - 8:50 a.m. 110nm NROM Technology for Code and Data Flash ProductsWiller, J. / Ludwig, C. / Deppe, J. / Kleint, C. / Riedel, S. / Sachse, J.-U. / Krause, M. / Mikalo, R. / Kamienski, E. v. / Parascandola, S. et al. | 2004
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Split-gate NAND flash memory at 120nm technology node featuring fast programming and eraseCheng-Yuan Hsu, / Chi-Wei Hung, / Da Sung, / Chi-Shan Wu, / Chen, S.C. / Kuo, H.H. / Pan, J.Y. / Chen, C.L. / Chuang, I.C. / Huang, V. et al. | 2004
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8.4 - 9:15 a.m. Split-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming and EraseHsu, C.-Y. / Hung, C.-W. / Sung, D. / Wu, C.-S. / Chen, S. C. / Kuo, H. H. / Pan, J. Y. / Chen, C. L. / Chuang, I. C. / Huang, V. et al. | 2004
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8.5 - 9:40 a.m. A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory ApplicationsIto, F. / Kawashima, Y. / Sakai, T. / Kanamaru, Y. / Ishii, Y. / Mizuno, M. / Hashimoto, T. / Ishimaru, T. / Mine, T. / Matsuzaki, N. et al. | 2004
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A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applicationsIto, F. / Kawashima, Y. / Sakai, T. / Kanamaru, Y. / Ishii, Y. / Mizuno, M. / Hashimoto, T. / Ishimaru, T. / Mine, T. / Matsuzaki, N. et al. | 2004
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SESSION 9 - Advanced Transistor Technology II| 2004
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9.1 - 8:00 a.m. A hp22 nm Node Low Operating Power (LOP) Technology with Sub-10 nm Gate Length Planar Bulk CMOS DevicesYasutake, N. / Ohuchi, K. / Fujiwara, M. / Adachi, K. / Hokazono, A. / Kojima, K. / Aoki, N. / Suto, H. / Watanabe, T. / Morooka, T. et al. | 2004
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A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devicesYasutake, N. / Ohuchi, K. / Fujiwara, M. / Adachi, K. / Hokazono, A. / Kojima, K. / Aoki, N. / Suto, H. / Watanabe, T. / Morooka, T. et al. | 2004
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9.2 - 8:25 a.m. A Simplified Hybrid Orientation Technology (SHOT) for High Performance CMOSDoris, B. / Zhang, Y. / Fried, D. / Beintner, J. / Dokumaci, O. / Natzle, W. / Zhu, H. / Boyd, D. / Holt, J. / Petrus, J. et al. | 2004
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A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOSDoris, B. / Zhang, Y. / Fried, D. / Beintner, J. / Dokumaci, O. / Natzle, W. / Zhu, H. / Boyd, D. / Holt, J. / Petrus, J. et al. | 2004
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9.3 - 8:50 a.m. Power-aware 65 nm Node CMOS Technology Using Variable V~d~d and Back-bias Control with Reliability Consideration for Back-bias ModeTogo, M. / Fukai, T. / Nakahara, Y. / Koyama, S. / Makabe, M. / Hasegawa, E. / Nagase, M. / Matsuda, T. / Sakamoto, K. / Fujiwara, S. et al. | 2004
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Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias modeTogo, M. / Fukai, T. / Nakahara, Y. / Koyama, S. / Makabe, M. / Hasegawa, E. / Nagase, M. / Matsuda, T. / Sakamoto, K. / Fujiwara, S. et al. | 2004
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9.4 - 9:15 a.m. Symmetrical 45nm PMOS on (110) Substrate with Excellent S/D Extension Distribution and Mobility EnhancementHwang, J. R. / Ho, J. H. / Liu, Y. C. / Shen, J. J. / Chen, W. J. / Chen, D. F. / Liao, W. S. / Hsieh, Y. S. / Lin, W. M. / Hsu, C. H. et al. | 2004
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Symmetrical 45nm PMOS on [110] substrate with excellent S/D extension distribution and mobility enhancementHwang, J.R. / Ho, J.H. / Liu, Y.C. / Shen, J.J. / Chen, W.J. / Chen, D.F. / Liao, W.S. / Hsieh, Y.S. / Lin, W.M. / Hsu, C.H. et al. | 2004
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9.5 - 9:40 a.m. 65nm CMOS High Speed, General Purpose and Low Power Transistor Technology for High Volume Foundry ApplicationFung, S. K. H. / Huang, H. T. / Cheng, S. M. / Cheng, K. L. / Wang, S. W. / Wang, Y. P. / Yao, Y. Y. / Chu, C. M. / Yang, S. J. / Liang, W. J. et al. | 2004
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65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry applicationFung, S.K.H. / Huang, H.T. / Cheng, S.M. / Cheng, K.L. / Wang, S.W. / Wang, Y.P. / Yao, Y.Y. / Chu, C.M. / Yang, S.J. / Liang, W.J. et al. | 2004
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SESSION 10 - Analog/RF Devices I| 2004
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10.1 - 10:20 a.m. Three-Dimensional Circuit Integration Based on Self-Synchronized RF-Interconnect Using Capacitive CouplingGu, Q. / Xu, Z. / Kim, J. / Ko, J. / Chang, M. F. / IEEE et al. | 2004
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Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive couplingQun Gu, / Zhiwei Xu, / Jongsun Kim, / Jenwei Ko, / Chang, M.F. et al. | 2004
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A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capabilityZamdmer, N. / Jonghae Kim, / Trzcinski, R. / Plouchart, J.-O. / Narasimha, S. / Khare, M. / Wagner, L. / Chaloux, S. et al. | 2004
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10.2 - 10:45 a.m. A 243-GHz F~T and 208-GHz F~m~a~x, 90-nm SOI CMOS SoC Technology with Low-Power Millimeter-Wave Digital and RF Circuit CapabilityZamdmer, N. / Kim, J. / Trzcinski, R. / Plouchart, J.-O. / Narasimha, S. / Khare, M. / Wagner, L. / Chaloux, S. / IEEE et al. | 2004
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10.3 - 11:10 a.m. Integration of a 90nm RF CMOS Technology (200GHz f~m~a~x - 150GHz f~T NMOS) Demonstrated by a 5GHz LNAJeamsaksiri, W. / Mercha, A. / Ramos, J. / Linten, D. / Thijs, S. / Jenei, S. / Detcheverry, C. / Wambacq, P. / Velghe, R. / Decoutere, S. et al. | 2004
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Integration of a 90nm RF CMOS technology (200GHz f/sub max/ - 150GHz f/sub T/ NMOS) demonstrated on a 5GHz LNAJeamsaksiri, W. / Mercha, A. / Ramos, J. / Linten, D. / Thijs, S. / Jenei, S. / Detcheverry, C. / Wambacq, P. / Velghe, R. / Decoutere, S. et al. | 2004
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10.4 - 11:35 a.m. Impact of Mechanical Stress Engineering on Flicker Noise CharacteristicsMaeda, S. / Jin, Y.-S. / Choi, J.-A. / Oh, S.-Y. / Lee, H.-W. / Yoo, J.-Y. / Sun, M.-C. / Ku, J.-H. / Lee, K. / Bae, S.-G. et al. | 2004
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Impact of mechanical stress engineering on flicker noise characteristicsMaeda, S. / You-Seung Jin, / Jung-A Choi, / Sun-Young Oh, / Hyun-Woo Lee, / Jae-Yoon Yoo, / Min-Chul Sun, / Ja-Hum Ku, / Kwon Lee, / Su-Gon Bae, et al. | 2004
- 105
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SESSION 11 - High k Dielectric Technology| 2004
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11.1 - 10:20 a.m. Performance and Reliability of Sub-100nm TaSiN Metal Gate Fully-depleted SOI Devices with High-K (HfO~2) Gate DielectricThean, A. V.-Y. / Vandooren, A. / Kalpat, S. / Du, Y. / To, I. / Hughes, J. / Stephens, T. / Goolsby, B. / White, T. / Barr, A. et al. | 2004
- 106
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Performance and reliability of sub-100nm TaSiN metal gate fully-depleted SOI devices with high-k (HfO/sub 2/) gate dielectricThean, A.V.-Y. / Vandooren, A. / Kalpat, S. / Du, Y. / To, I. / Hughes, J. / Stephens, T. / Goolsby, B. / White, T. / Barr, A. et al. | 2004
- 108
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Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interfaceShiraishi, K. / Yamada, K. / Torii, K. / Akasaka, Y. / Nakajima, K. / Kohno, M. / Chikyo, T. / Kitajima, H. / Arikado, T. et al. | 2004
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11.2 - 10:45 a.m. Physics in Fermi Level Pinning at the PolySi/Hf-based High-k Oxide InterfaceShiraishi, K. / Yamada, K. / Torii, K. / Akasaka, Y. / Nakajima, K. / Kohno, M. / Chikyo, T. / Kitajima, H. / Arikado, T. / IEEE et al. | 2004
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High mobility and excellent electrical stability of MOSFETs using a novel HfTaO gate dielectricXiongfei Yu, / Chunxiang Zhu, / Wang, X.P. / Li, M.F. / Chin, A. / Du, A.Y. / Wang, W.D. / Dim-Lee Kwong, et al. | 2004
- 110
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11.3 - 11:10 a.m. High Mobility and Excellent Electrical Stability of MOSFETs Using a Novel HfTaO Gate DielectricYu, X. / Zhu, C. / Wang, X. P. / Li, M. F. / Chin, A. / Du, A. Y. / Wang, W. D. / Kwong, D.-L. / IEEE et al. | 2004
- 112
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11.4 - 11:35 a.m. Dielectric Breakdown Mechanism of HfSiON/SiO~2 Gate DielectricTorii, K. / Aoyama, T. / Kamiyama, S. / Tamura, Y. / Miyazaki, S. / Kitajima, H. / Arikado, T. / IEEE et al. | 2004
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Dielectric breakdown mechanism of HfSiON/SiO/sub 2/ gate dielectricTorii, K. / Aoyama, T. / Kamiyama, S. / Tamura, Y. / Miyazaki, S. / Kitajima, H. / Arikado, T. et al. | 2004
- 115
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SESSION 12 - Device Characterization/Modeling| 2004
- 116
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Rigorous mathematical calculation of p- and n-mobility as functions of mechanical stress, electric field, current direction and substrate indices for scaled CMOS designingOkada, T. / Yoshimura, H. et al. | 2004
- 116
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12.1 - 1:30 p.m. Rigorous Mathematical Calculation of p- and n-Mobility as Functions of Mechanical Stress, Electric Field, Current Direction and Substrate Indices for Scaled CMOS DesigningOkada, T. / Yoshimura, H. / IEEE et al. | 2004
- 118
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12.2 - 1:55 p.m. Understanding Stress Enhanced Performance in Intel 90nm CMOS TechnologyGiles, M. D. / Armstrong, M. / Auth, C. / Cea, S. M. / Ghani, T. / Hoffmann, T. / Kotlyar, R. / Matagne, P. / Mistry, K. / Nagisetty, R. et al. | 2004
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Understanding stress enhanced performance in Intel 90nm CMOS technologyGiles, M.D. / Armstrong, M. / Auth, C. / Cea, S.M. / Ghani, T. / Hoffmann, T. / Kotlyar, R. / Matagne, P. / Mistry, K. / Nagisetty, R. et al. | 2004
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12.3 - 2:20 p.m. Direct Measurement of Stress Dependent Inversion Layer Mobility Using a Novel Test StructureOkagaki, T. / Tanizawa, M. / Uchida, T. / Kunikiyo, T. / Sonoda, K. / Igarashi, M. / Ishikawa, K. / Takeda, T. / Lee, P. / Yokomizo, G. et al. | 2004
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Direct measurement of stress dependent inversion layer mobility using a novel test structureOkagaki, T. / Tanizawa, M. / Uchida, T. / Kunikiyo, T. / Sonoda, K. / Igarashi, M. / Ishikawa, K. / Takeda, T. / Lee, P. / Yokomizo, G. et al. | 2004
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12.4 - 2:45 p.m. Direct Measurement of Barrier Height at the HfO~2/poly-Si Interface:Band Structure and Local EffectsPantisano, L. / Chen, P. J. / Afanas ev, V. / Ragnarsson, L. A. / Pourtois, G. / Groesenekenen, G. / IEEE et al. | 2004
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Direct measurement of barrier height at the HfO/sub 2//poly-Si interface: Band structure and local effectsPantisano, L. / Chen, P.J. / Afanas'ev, V. / Ragnarsson, L.-A. / Pourtois, G. / Groeseneken, G. et al. | 2004
- 125
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SESSION 13 - DRAM II| 2004
- 126
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13.1 - 1:30 p.m. Development of Highly Robust Nano-mixed HfxAlyOz Dielectrics for TiN/HfxAlyOz/TiN Capacitor Applicable to 65nm Generation DRAMsKil, D.-S. / Hong, K. / Lee, K.-J. / Kim, J. / Song, H.-S. / Park, K.-S. / Roh, J.-S. / Sohn, H.-C. / Kim, J.-W. / Park, S.-W. et al. | 2004
- 126
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Development of highly robust nano-mixed Hf/sub x/Al/sub y/O/sub z/ dielectrics for TiN/Hf/sub x/Al/sub y/O/sub z//TiN capacitor applicable to 65nm generation DRAMsDeok-Sin Kil, / Kwon Hong, / Kee-Jeung Lee, / Joosung Kim, / Han-Sang Song, / Ki-Seon Park, / Jae-Sung Roh, / Hyun-Chul Sohn, / Jin-Woong Kim, / Sung-Wook Park, et al. | 2004
- 128
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13.2 - 1:55 p.m. A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAMRanica, R. / Villaret, A. / Malinge, P. / Mazoyer, P. / Lenoble, D. / Candelier, P. / Jacquet, F. / Masson, P. / Bouchakour, R. / Fournel, R. et al. | 2004
- 128
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A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAMRanica, R. / Villaret, A. / Malinge, P. / Mazoyer, P. / Lenoble, D. / Candelier, P. / Jacquet, F. / Masson, P. / Bouchakour, R. / Fournel, R. et al. | 2004
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Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyondLee, C.H. / Yoon, J.M. / Lee, C. / Yang, H.M. / Kim, K.N. / Kim, T.Y. / Kang, H.S. / Ahn, Y.J. / Donggun Park, / Kinam Kim, et al. | 2004
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13.3 - 2:20 p.m. Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for Sub 60nm Technology and BeyondLee, C. H. / Yoon, J. M. / Lee, C. / Yang, H. M. / Kim, K. N. / Kim, T. Y. / Kang, H. S. / Ahn, Y. J. / Park, D. / Kim, K. et al. | 2004
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13.4 - 2:45 p.m. Higly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM ApplicationsShino, T. / Higashi, T. / Fujita, K. / Ohsawa, T. / Minami, Y. / Yamada, T. / Morikado, M. / Nakajima, H. / Inoh, K. / Hamamoto, T. et al. | 2004
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Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applicationsShino, T. / Higashi, I. / Fujita, K. / Ohsawa, T. / Minami, Y. / Yamada, T. / Morikado, M. / Nakajima, H. / Inoh, K. / Hamamoto, T. et al. | 2004
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SESSION 14 - Gate Dielectric Reliability| 2004
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14.1 - 3:25 p.m. Impact of Boron Penetration from S/D-Extension on Gate-Oxide Reliability for 65-nm Node CMOS and BeyondYamashita, T. / Ota, K. / Shiga, K. / Hayashi, T. / Umeda, H. / Oda, H. / Eimori, T. / Inuishi, M. / Ohji, Y. / Eriguchi, K. et al. | 2004
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Impact of boron penetration from S/D-extension on gate-oxide reliability for 65-nm node CMOS and beyondYamashita, T. / Ota, K. / Shiga, K. / Hayashi, T. / Umeda, H. / Oda, H. / Eimori, T. / Inuishi, M. / Ohji, Y. / Eriguchi, K. et al. | 2004
- 138
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14.2 - 3:50 p.m. Effects of Barrier Height (phi (variant)~B) and the Nature of Bi-Layer Structure on the Reliability of High-k Dielectrics with Dual Metal Gate (Ru & Ru-Ta alloy) TechnologyKim, Y. H. / Choi, R. / Jha, R. / Lee, J. H. / Misra, V. / Lee, J. C. / IEEE et al. | 2004
- 138
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Effects of barrier height (/spl Phi//sub B/) and the nature of bi-layer structure on the reliability of high-k dielectrics with dual metal gate (Ru & Ru-Ta alloy) technologyKim, Y.H. / Choi, R. / Jha, R. / Lee, J.H. / Misra, V. / Lee, J.C. et al. | 2004
- 140
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On the defect generation and low voltage extrapolation of Q/sub BD/ in SiO/sub 2//HfO/sub 2/ stacksDegraeve, R. / Crupi, F. / Kwak, D.H. / Groeseneken, G. et al. | 2004
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14.3 - 4:15 p.m. On the Defect Generation and Low Voltage Extrapolation of Q~B~D in SiO~2/HfO~2 StacksDegraeve, R. / Crupi, F. / Kwak, D. H. / Groeseneken, G. / IEEE et al. | 2004
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14.4 - 4:40 p.m. Significant Role of Cold Carriers for Dielectric Breakdown in HfSiONHirano, I. / Yamaguchi, T. / Sekine, K. / Takayanagi, M. / Eguchi, K. / Tsunashima, Y. / Satake, H. / IEEE et al. | 2004
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Significant role of cold carriers for dielectric breakdown in HfSiONHirano, I. / Yamaguchi, T. / Sekine, K. / Takayanagi, M. / Eguchi, K. / Tsunashima, Y. / Satake, H. et al. | 2004
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SESSION 15 - Emerging Memory Technologies II| 2004
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New highly scalable 3 dimensional chain FeRAM cell with vertical capacitorNagel, N. / Bruchhaus, R. / Hornik, K. / Egger, U. / Zhuang, H. / Joachim, H.-O. / Rohr, T. / Beitel, G. / Ozaki, T. / Kunishima, I. et al. | 2004
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15.1 - 3:25 p.m. New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical CapacitorNagel, N. / Bruchhaus, R. / Hornik, K. / Egger, U. / Zhuang, H. / Joachim, H.-O. / Roehr, T. / Beitel, G. / Ozaki, T. / Kunishima, I. et al. | 2004
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15.2 - 3:50 p.m. Highly Reliable and Mass-Productive FRAM Embedded Smartcard Using Advanced Integration TechnologiesJoo, H. J. / Song, Y. J. / Kim, H. H. / Kang, S. K. / Park, J. H. / Kang, Y. M. / Kang, E. Y. / Lee, S. Y. / Jeong, H. S. / Kim, K. et al. | 2004
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Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologiesJoo, H.J. / Song, Y.J. / Kim, H.H. / Kang, S.K. / Park, J.H. / Kang, Y.M. / Kang, E.Y. / Lee, S.Y. / Jeong, H.S. / Kinam Kim, et al. | 2004
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15.3 - 4:15 p.m. A 0.602 mum^2 Nestled Chain Cell Structure Formed By One Mask Etching Process For 64 Mbit FeRAMKanaya, H. / Tomioka, K. / Matsushita, T. / Omura, M. / Ozaki, T. / Kumura, Y. / Shimojo, Y. / Morimoto, T. / Hidaka, O. / Shuto, S. et al. | 2004
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A 0.602 /spl mu/m/sup 2/ nestled 'Chain' cell structure formed by one mask etching process for 64 Mbit FeRAMKanaya, H. / Tomioka, K. / Matsushita, T. / Omura, M. / Ozaki, T. / Kumura, Y. / Shimojo, Y. / Morimoto, T. / Hidaka, O. / Shuto, S. et al. | 2004
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15.4 - 4:40 p.m. Ultra-High Speed Direct Tunneling Memory (DTM) for Embedded RAM ApplicationsTsunoda, K. / Sato, A. / Tashiro, H. / Ohira, K. / Nakanishi, T. / Tanaka, H. / Arimoto, Y. / IEEE et al. | 2004
- 152
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Ultra-high speed Direct Tunneling Memory (DTM) for embedded RAM applicationsTsunoda, K. / Sato, A. / Tashiro, H. / Ohira, K. / Nakanishi, T. / Tanaka, H. / Arimoto, Y. et al. | 2004
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RUMP SESSIONS| 2004
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Is DRAM dead? Will Flash rule the world?Atwood, G. / Kim, K. et al. | 2004
- 156
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What's beyond the planar MOSFET?Bernstein, K. / Lin, M.-R. / Mashiko, K. / Omura, Y. / Graham, J. / Saraswat, K. et al. | 2004
- 157
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Strained Si for enhanced CMOS performanceAntoniadis, D. / Takagi, S. et al. | 2004
- 159
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SESSION 16 - Advanced Transistor Technology III| 2004
- 160
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On the integration of CMOS with hybrid crystal orientationsYang, M. / Chan, V. / Ku, S.H. / Ieong, M. / Shi, L. / Chan, K.K. / Murthy, C.S. / Mo, R.T. / Yang, H.S. / Lehner, E.A. et al. | 2004
- 160
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16.1 - 8:00 a.m. On the Integration of CMOS with Hybrid Crystal OrientationsYang, M. / Chan, V. / Ku, S. H. / Ieong, M. / Shi, L. / Chan, K. K. / Murthy, C. S. / Mo, R. T. / Yang, H. S. / Lehner, E. A. et al. | 2004
- 162
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16.2 - 8:25 a.m. An Enhanced 90nm High Performance Technology with Strong Performance Improvements from Stress and Mobility Increase through Simple Process ChangesKhamankar, R. / Bu, H. / Bowen, C. / Chakravarthi, S. / Chidambaram, P. R. / Bevan, M. / Krishnan, A. / Niimi, H. / Smith, B. / Blatchford, J. et al. | 2004
- 162
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An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changesKhamankar, R. / Bu, H. / Bowen, C. / Chakravarthi, S. / Chidambaram, P.R. / Bevan, M. / Krishnan, A. / Niimi, H. / Smith, B. / Blatchford, J. et al. | 2004
- 164
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16.3 - 8:50 a.m. New Guideline of Vdd and Vth Scaling for 65nm Technology and BeyondMorifuji, E. / Yoshida, T. / Tsuno, H. / Kikuchi, Y. / Matsuda, S. / Yamada, S. / Noguchi, T. / Kakumu, M. / IEEE et al. | 2004
- 164
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New guideline of Vdd and Vth scaling for 65nm technology and beyondMorifuji, E. / Yoshida, T. / Tsuno, H. / Kikuchi, Y. / Matsuda, S. / Yamada, S. / Noguchi, T. / Kakumu, M. et al. | 2004
- 166
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High performance CMOSFET technology for 45nm generationOishi, A. / Komoda, T. / Morimasa, Y. / Sanuki, T. / Yamasaki, H. / Hamaguchi, M. / Oouchi, K. / Matsuo, K. / Iinuma, T. / Itoh, T. et al. | 2004
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16.4 - 9.15 a.m. High Performance CMOSFET Technology for 45nm generationOishi, A. / Komoda, T. / Morimasa, Y. / Sanuki, T. / Yamasaki, H. / Hamaguchi, M. / Oouchi, K. / Matsuo, K. / Iinuma, T. / Itoh, T. et al. | 2004
- 168
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Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation techniqueKinoshita, A. / Tsuchiya, Y. / Yagishita, A. / Uchida, K. / Koga, J. et al. | 2004
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16.5 - 9:40 a.m. Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation TechniqueKinoshita, A. / Tsuchiya, Y. / Yagishita, A. / Uchida, K. / Koga, J. / IEEE et al. | 2004
- 171
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SESSION 17 - Process Technology| 2004
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Novel fabrication process to realize ultra-thin (EOT = 0.7nm) and ultra-low leakage SiON gate dielectricsMatsushita, D. / Muraoka, K. / Nakasaki, Y. / Kato, K. / Inumiya, S. / Eguchi, K. / Takayanagi, M. et al. | 2004
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17.1 - 8:00 a.m. Novel Fabrication Process to Realize Ultra-thin (EOT = 0.7nm) and Ultra-low Leakage SiON Gate DielectricsMatsushita, D. / Muraoka, K. / Nakasaki, Y. / Kato, K. / Inumiya, S. / Eguchi, K. / Takayanagi, M. / IEEE et al. | 2004
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Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOSShima, A. / Yun Wang, / Talwar, S. / Hiraiwa, A. et al. | 2004
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17.2 - 8:25 a.m. Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing for 50-nm Gate CMOSShima, A. / Wang, Y. / Talwar, S. / Hiraiwa, A. / IEEE et al. | 2004
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Extended scaling of ultrathin gate oxynitride toward sub-65nm CMOS by optimization of UV photo-oxidation, soft plasma/thermal nitridation & stress enhancementChi-Chun Chen, / Chang, V.S. / Jin, Y. / Chen, C.-H. / Lee, T.-L. / Chen, S.-C. / Liang, M.-S. et al. | 2004
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17.3 - 8:50 a.m. Extended Scaling of Ultrathin-Gate Oxynitride Toward Sub-65nm CMOS by Optimization of UV Photo-Oxidation, Soft Plasma/Thermal Nitridation & Stress EnhancementChen, C.-C. / Chang, V. S. / Jin, Y. / Chen, C.-H. / Lee, T.-L. / Chen, S.-C. / Liang, M.-S. / IEEE et al. | 2004
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Ultra-low cost and high performance 65nm CMOS device fabricated with plasma dopingLallement, F. / Duriez, B. / Grouillet, A. / Arnaud, F. / Tavel, B. / Wacquant, F. / Stolk, P. / Woo, M. / Erokhin, Y. / Scheuer, J. et al. | 2004
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17.4 - 9:15 a.m. Ultra-Low Cost and High Performance 65nm CMOS Device Fabricated with Plasma DopingLallement, F. / Duriez, B. / Grouillet, A. / Arnaud, F. / Tavel, B. / Wacquant, F. / Stolk, P. / Woo, M. / Erokhin, Y. / Scheuer, J. et al. | 2004
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17.5 - 9:40 a.m. B~2H~6 Plasma Doping with "In-situ He Pre-amorphization"Sasaki, Y. / Jin, C. G. / Tamura, H. / Mizuno, B. / Higaki, R. / Satoh, T. / Majima, K. / Sauddin, H. / Takagi, K. / Ohmi, S. et al. | 2004
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B/sub 2/H/sub 6/ plasma doping with "in-situ He pre-amorphization"Sasaki, Y. / Jin, C.G. / Tamura, H. / Mizuno, B. / Higaki, R. / Satoh, T. / Majima, K. / Sauddin, H. / Takagi, K. / Ohmi, S. et al. | 2004
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SESSION 18 - Advanced Metal Gate Materials| 2004
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Dual workfunction fully silicided metal gatesCabral, C. / Kedzierski, J. / Linder, B. / Zafar, S. / Narayanan, V. / Fang, S. / Steegen, A. / Kozlowski, P. / Carruthers, R. / Jammy, R. et al. | 2004
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18.1 - 10:20 a.m. Dual Workfunction Fully Silicided Metal GatesCabral, C. / Kedzierski, J. / Linder, B. / Zafar, S. / Narayanan, V. / Fang, S. / Steegen, A. / Kozlowski, P. / Carruthers, R. / Jammy, R. et al. | 2004
- 186
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Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flowPark, D.-G. / Luo, Z.J. / Edleman, N. / Zhu, W. / Nguyen, P. / Wong, K. / Cabral, C. / Jamison, P. / Lee, B.H. / Chou, A. et al. | 2004
- 186
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18.2 - 10:45 a.m. Thermally Robust Dual-Work Function ALD-MN~x MOSFETs Using Conventional CMOS Process FlowPark, D.-G. / Luo, Z. J. / Edleman, N. / Zhu, W. / Nguyen, P. / Wong, K. / Cabral, C. / Jamison, P. / Lee, B. H. / Chou, A. et al. | 2004
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Laminated metal gate electrode with tunable work function for advanced CMOSBae, S.H. / Bai, W.P. / Wen, H.C. / Mathew, S. / Bera, L.K. / Balasubramanian, N. / Yamada, N. / Li, M.F. / Kwong, D.L. et al. | 2004
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18.3 - 11:10 a.m. Laminated Metal Gate Electrode with Tunable Work Function for Advanced CMOSBae, S. H. / Bai, W. P. / Wen, H. C. / Mathew, S. / Bera, L. K. / Balasubramanian, N. / Yamada, N. / Li, M. F. / Kwong, D. L. / IEEE et al. | 2004
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18.4 - 11:35 a.m. Demonstration of Fully Ni-Silicided Metal Gates on HfO~2 Based High-k Gate Dielectrics as a Candidate for Low Power ApplicationsAnil, K. G. / Veloso, A. / Kubicek, S. / Schram, T. / Augendre, E. / de Marneffe, J.-F. / Devriendt, K. / Lauwers, A. / Brus, S. / Henson, K. et al. | 2004
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Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applicationsAnil, K.G. / Veloso, A. / Kubicek, S. / Schram, T. / Augendre, E. / de Marneffe, J.-F. / Devriendt, K. / Lauwers, A. / Brus, S. / Henson, K. et al. | 2004
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Dual work function metal gate CMOS using CVD metal electrodesNarayanan, V. / Callegari, A. / McFeely, F.R. / Nakamura, K. / Jamison, P. / Zafar, S. / Cartier, E. / Steegen, A. / Ku, V. / Nguyen, P. et al. | 2004
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18.5 - 12:00 p.m. Dual Work Function Metal Gate CMOS using CVD Metal ElectrodesNarayanan, V. / Callegari, A. / McFeely, F. R. / Nakamura, K. / Jamison, P. / Zafar, S. / Cartier, E. / Steegen, A. / Ku, V. / Nguyen, P. et al. | 2004
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SESSION 19 - Novel Device Concepts| 2004
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19.1 - 10:20 a.m. 5nm-Gate Nanowire FinFETYang, F.-L. / Lee, D.-H. / Chen, H.-Y. / Chang, C.-Y. / Liu, S.-D. / Huang, C.-C. / Chung, T.-X. / Chen, H.-W. / Liu, Y.-H. / IEEE et al. | 2004
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5nm-gate nanowire FinFETFu-Liang Yang, / Di-Hong Lee, / Hou-Yu Chen, / Chang-Yun Chang, / Sheng-Da Liu, / Cheng-Chuan Huang, / Tang-Xuan Chung, / Hung-Wei Chen, / Chien-Chao Huang, / Yi-Hsuan Liu, et al. | 2004
- 198
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19.2 - 10:45 a.m. Selectively-Formed High Mobility SiGe-on-Insulator pMOSFETs with Ge-rich Strained Surface Channels Using Local Condensation TechniqueTezuka, T. / Nakaharai, S. / Moriyama, Y. / Sugiyama, N. / Takagi, S.-I. / IEEE et al. | 2004
- 198
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Selectively-formed high mobility SiGe-on-Insulator pMOSFETs with Ge-rich strained surface channels using local condensation techniqueTezuka, T. / Nakaharai, S. / Moriyama, Y. / Sugiyama, N. / Shin-ichi Takagi, et al. | 2004
- 200
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A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performanceSung-Young Lee, / Eun-Jung Yoon, / Sung-Min Kim, / Chang Woo Oh, / Ming Li, / Jeong-Dong Choi, / Kyoung-Hwan Yeo, / Min-Sang Kim, / Hye-Jin Cho, / Sung-Hwan Kim, et al. | 2004
- 200
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19.3 - 11:10 a.m. A Novel Sub-50 nm Multi-Bridge-Channel MOSFET (MBCFET) with Extremely High PerformanceLee, S.-Y. / Yoon, E.-J. / Kim, S.-M. / Oh, C. W. / Li, M. / Choi, J.-D. / Yeo, K.-H. / Kim, M.-S. / Cho, H.-J. / Kim, S.-H. et al. | 2004
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19.4 - 11:35 a.m. High Velocity Electron Injection MOSFETs for Ballistic Transistors using SiGe/Strained-Si Heterojunction Source StructuresMizuno, T. / Sugiyama, N. / Tezuka, T. / Moriyama, Y. / Nakaharai, S. / Maeda, T. / Takagi, S. / IEEE et al. | 2004
- 202
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High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained-Si heterojunction source structuresMizuno, T. / Sugiyama, N. / Tezuka, T. / Moriyama, Y. / Nakaharai, S. / Maeda, T. / Takagi, S. et al. | 2004
- 204
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Channel design and mobility enhancement in strained germanium buried channel MOSFETsShang, H. / Chu, J.O. / Wang, X. / Mooney, P.M. / Lee, K. / Ott, J. / Rim, K. / Chan, K. / Guarini, K. / Ieong, M. et al. | 2004
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19.5 - 12:00 p.m. Channel Design and Mobility Enhancement in Strained Germanium Buried Channel MOSFETsShang, H. / Chu, J. O. / Wang, X. / Mooney, P. M. / Lee, K. / Ott, J. / Rim, K. / Chan, K. / Guarini, K. / Ieong, M. et al. | 2004
- 207
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SESSION 20 - High k Transistor Reliability| 2004
- 208
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A model for negative bias temperature instability (NBTI) in oxide and high /spl kappa/ pFETs 13/spl times/-C6D8C7F5F2Zafar, S. / Lee, B.H. / Stathis, J. / Callegari, A. / Tak Ning, et al. | 2004
- 208
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20.1 - 1:30 p.m. A Model for Negative Bias Temperature Instability (NBTI) in Oxide and High kappa pFETsZafar, S. / Lee, B. / Stathis, J. / Callegar, A. / Ning, T. / IEEE et al. | 2004
- 210
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20.2 - 1:55 p.m. SiN-capped HfSiON Gate Stacks with Improved Bias Temperature Instabilities for 65 nm-node Low-Standby-Power TransistorsTamura, Y. / Sasaki, T. / Izumi, N. / Ootsuka, F. / Yasuhira, M. / Hoshi, T. / Kume, S. / Amai, H. / Ida, T. / Aoyama, T. et al. | 2004
- 210
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SiN-capped HfSiON gate stacks with improved bias temperature instabilities for 65 nm-node low-standby-power transistorsTamura, Y. / Sasaki, T. / Izumi, N. / Ootsuka, F. / Yasuhira, M. / Hoshi, T. / Kume, S. / Amai, H. / Ida, T. / Aoyama, T. et al. | 2004
- 212
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Detrimental impact of hydrogen on negative bias temperature instabilities in HfO/sub 2/-based pMOSFETsHoussa, M. / De Gendt, S. / Autran, J.L. / Groeseneken, G. / Heyns, M.M. et al. | 2004
- 212
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20.3 - 2:20 p.m. Detrimental Impact of Hydrogen on Negative Bias Temperature Instabilities in HfO~2-Based pMOSFETsHoussa, M. / De Gendt, S. / Autran, J. L. / Groeseneken, G. / Heyns, M. M. / IEEE et al. | 2004
- 214
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The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature InstabilityChanghwan Choi, / Kang, C.S. / Kang, C.Y. / Choi, R. / Cho, H.J. / Kim, Y.H. / Rhee, S.J. / Akbar, M. / Lee, J.C. et al. | 2004
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20.4 - 2:45 p.m. The Effects of Nitrogen and Silicon Profile on High-K MOSFET Performance and Bias Temperature InstabilityChoi, C. / Kang, C. S. / Kang, C. Y. / Choi, R. / Cho, H. J. / Kim, Y. H. / Rhee, S. J. / Akbar, M. / Lee, J. C. / IEEE et al. | 2004
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SESSION 21- Analog/RF Devices II| 2004
- 218
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Engineering of voltage nonlinearity in high-k MIM capacitor for analog/mixed-signal ICsSun Jung Kim, / Byung Jin Cho, / Li, M.-F. / Ding, S.-J. / Yu, M.B. / Chunxiang Zhu, / Chin, A. / Kwong, D.-L. et al. | 2004
- 218
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21.1 - 1:30 p.m. Engineering of Voltage Nonlinearity in High-K MIM Capacitor for Analog/Mixed-Signal ICsKim, S. J. / Cho, B. J. / Li, M.-F. / Ding, S.-J. / Yu, M. B. / Zhu, C. / Chin, A. / Kwong, D.-L. / IEEE et al. | 2004
- 220
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21.2 - 1:55 p.m. Ultra-thin Chip with Permalloy Film for High Performance MS / RF CMOSOhguro, T. / Sato, N. / Matsuo, M. / Kojima, K. / Momose, H. S. / Ishimaru, K. / Ishiuchi, H. / IEEE et al. | 2004
- 220
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Ultra-thin chip with permalloy film for high performance MS/RF CMOSOhguro, T. / Sato, N. / Matsuo, M. / Kojima, K. / Momose, H.S. / Ishimaru, K. / Ishiuchi, H. et al. | 2004
- 222
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21.3 - 2:20 p.m. High Quality High-k MIM Capacitor by Ta~2O~5/HfO~2/Ta~2O~5 Multilayered Dielectric and NH~3 Plasma Interface Treatments for Mixed-Signal/RF ApplicationsJeong, Y.-K. / Won, S.-J. / Kwon, D.-J. / Song, M.-W. / Kim, W.-H. / Park, M.-H. / Jeong, J.-H. / Oh, H.-S. / Kang, H.-K. / Suh, K.-P. et al. | 2004
- 222
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High quality high-k MIM capacitor by Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/ multi-layered dielectric and NH/sub 3/ plasma interface treatments for mixed-signal/RF applicationsYong-kuk Jeong, / Seok-jun Won, / Dae-jin Kwon, / Min-woo Song, / Weon-hong Kim, / Moon-han Park, / Joo-hyun Jeong, / Han-su Oh, / Ho-kyu Kang, / Kwang-pyuk Suh, et al. | 2004
- 224
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21.4 - 2:45 p.m. A Comparison of State-of-the-Art NMOS and SiGe HBT Devices for Analog/Mixed-signal/RF Circuit ApplicationsKuhn, K. / Basco, R. / Becher, D. / Hattendorf, M. / Packan, P. / Post, I. / Vandervoorn, P. / Young, I. / IEEE et al. | 2004
- 224
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A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applicationsKuhn, K. / Basco, R. / Becher, D. / Hattendorf, M. / Packan, P. / Post, I. / Vandervoorn, P. / Young, I. et al. | 2004
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SESSION 22 - Advanced CMOS Technology II| 2004
- 228
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The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAMSoon-Moon Jung, / Jaehoon Jang, / Wonseok Cho, / Jaehwan Moon, / Kunho Kwak, / Bonghyun Choi, / Byungjun Hwang, / Hoon Lim, / Jaehun Jeong, / Jonghyuk Kim, et al. | 2004
- 228
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22.1 - 3:25 p.m. The Revolutionary and Truly 3-Deminsional 25F^2 SRAM Technology with the Smallest S^3 (Stacked Single-Crystal Si) Cell, 0.16mum^2, and SSTFT (Staced Single-Crystal Thin Film Transistor) for Ultra High Density SRAMJung, S.-M. / Jang, J. / Cho, W. / Moon, J. / Kwak, K. / Choi, B. / Hwang, B. / Lim, H. / Jeong, J. / Kim, J. et al. | 2004
- 230
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A CPU on a plastic film substrateTakayama, T. / Ohno, Y. / Goto, Y. / Machida, A. / Fujita, M. / Maruyama, J. / Kato, K. / Koyama, J. / Yamazaki, S. et al. | 2004
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22.2 - 3:50 p.m. A CPU on a Plastic Film SubstrateTakayama, T. / Ohno, Y. / Goto, Y. / Machida, A. / Fujita, M. / Maruyama, J. / Kato, K. / Koyama, J. / Yamazaki, S. / IEEE et al. | 2004
- 232
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Soft error free, low power and low cost superSRAM with 0.98 /spl mu/m/sup 2/ cell by utilizing existing 0.15 /spl mu/m-DRAM processFujii, Y. / Ishigaki, Y. / Hosokawa, T. / Dei, M. / Maki, Y. / Nishida, A. / Izutsu, T. / Nakashima, Y. / Toyota, R. / Koga, T. et al. | 2004
- 232
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22.3 - 4:15 p.m. Soft Error Free, Low Power and Low Cost superSRAM with 0.98mum^2 Cell By Utilizing Existing 0.15mum-DRAM ProcessFujii, Y. / Ishigaki, Y. / Hosokawa, T. / Dei, M. / Maki, Y. / Nishida, A. / Izutsu, T. / Nakashima, Y. / Toyota, R. / Koga, T. et al. | 2004
- 234
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22.4 - 4:40 p.m. A New Vertically Stacked Poly-Si MOSFET with Partially Depleted SOI Operation for Densely Integrated SoC ApplicationsMatsuoka, H. / Mine, T. / Nakazato, K. / Moniwa, M. / Takahashi, Y. / Matsuoka, M. / Chakihara, H. / Fujimoto, A. / Okuyama, K. / IEEE et al. | 2004
- 234
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A new vertically stacked poly-Si MOSFET with partially depleted SOI operation for densely integrated SoC applicationsMatsuoka, H. / Mine, T. / Nakazato, K. / Moniwa, M. / Takahashi, Y. / Matsuoka, M. / Chakihara, H. / Fujimoto, A. / Okuyama, K. et al. | 2004
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SESSION 23 - Flash Memory II| 2004
- 238
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23.1 - 3:25 p.m. A 70nm NOR Flash Technology with 0.049 mum^2 Cell SizePark, C. / Sim, S. / Han, J. / Jeong, C. / Jang, Y. / Park, J. / Kim, J. / Park, K. / Kim, K. / IEEE et al. | 2004
- 238
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A 70nm NOR flash technology with 0.049 /spl mu/m/sup 2/ cell sizeChankwang Park, / Sangpil Sim, / Jungin Han, / Chul Jeong, / Younggoan Jang, / Junghwan Park, / Jaehoon Kim, / Kyucharn Park, / Kinam Kim, et al. | 2004
- 240
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Full integration and characterization of Localized ONO Memory (LONOM) for embedded flash technologyCho, I.W. / Lim, B.R. / Kim, J.-H. / Kim, S.S. / Kim, K.C. / Lee, B.J. / Bae, G.J. / Lee, N.I. / Kim, S.H. / Koh, K.W. et al. | 2004
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23.2 - 3:50 p.m. Full Integration and Characterization of Localized ONO Memory (LONOM) for Embedded Flash TechnologyCho, I. W. / Lim, B. R. / Kim, J.-H. / Kim, S. S. / Kim, K. C. / Lee, B. J. / Bae, G. J. / Lee, N. I. / Kim, S. H. / Koh, K. W. et al. | 2004
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23.3 - 4:15 p.m. Charge-injection Length in Silicon Nanocrystal Memory CellsOsabe, T. / Ishii, T. / Mine, T. / Sano, T. / Arigane, T. / Fukumura, T. / Kurata, H. / Saeki, S. / Ikeda, Y. / Yano, K. et al. | 2004
- 242
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Charge-injection length in silicon nanocrystal memory cellsOsabe, T. / Ishii, T. / Mine, T. / Sano, T. / Arigane, T. / Fukumura, T. / Kurata, H. / Saeki, S. / Ikeda, Y. / Yano, K. et al. | 2004
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23.4 - 4:40 p.m. Sub 40nm Tri-Gate Charge Trapping Nonvolatile Memory Cells for High Density ApplicationsSpecht, M. / Kommling, R. / Dreeskornfeld, L. / Weber, W. / Hofmann, F. / Alvarez, D. / Kretz, J. / Luyken, R. J. / Roesner, W. / Reisinger, H. et al. | 2004
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Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applicationsSpecht, M. / Kommling, R. / Dreeskornfeld, L. / Weber, W. / Hofmann, F. / Alvarez, D. / Kretz, J. / Luyken, R.J. / Rosner, W. / Reisinger, H. et al. | 2004
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Author index| 2004
- i
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2004 Symposium on VLSI Technology. Digest of Technical Papers - Title| 2004
- ii
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Copyright| 2004
- iii
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Foreword - Welcome to the 2004 Symposium on VLSI TechnologyYuan Taur, / Maeguchi, K. et al. | 2004
- iv
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Executive Committees| 2004
- v
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Technical Program Committees| 2004
- vi
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Table of Contents| 2004
- xiii
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2004 VLSI Technology Symposium Short Course| 2004
- xv
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Session Quick Index| 2004
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2005 Symposium on VLSI Circuits (IEEE Cat. No. 05CH37640)| 2004
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2004 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.04CH37526)| 2004