1.19-C SoC Design Environment with Automated Configurable Bus Generation for Rapid Prototyping (Englisch)
- Neue Suche nach: Lee, S.-H.
- Neue Suche nach: Lee, J.-G.
- Neue Suche nach: Kim, S.
- Neue Suche nach: Hwangbo, W.
- Neue Suche nach: Kyung, C.-M.
- Neue Suche nach: IEEE
- Neue Suche nach: Lee, S.-H.
- Neue Suche nach: Lee, J.-G.
- Neue Suche nach: Kim, S.
- Neue Suche nach: Hwangbo, W.
- Neue Suche nach: Kyung, C.-M.
- Neue Suche nach: Tang, T.-A.
- Neue Suche nach: Huang, Y.
- Neue Suche nach: IEEE
In:
ASIC
6
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122-125
;
2005
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ISBN:
- Aufsatz (Konferenz) / Print
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Titel:1.19-C SoC Design Environment with Automated Configurable Bus Generation for Rapid Prototyping
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Beteiligte:Lee, S.-H. ( Autor:in ) / Lee, J.-G. ( Autor:in ) / Kim, S. ( Autor:in ) / Hwangbo, W. ( Autor:in ) / Kyung, C.-M. ( Autor:in ) / Tang, T.-A. / Huang, Y. / IEEE
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Kongress:International conference; 6TH, ASIC ; 2005 ; Shanghai, China
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Erschienen in:ASIC , 6 ; 122-125INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS ; 1, 6 ; 122-125
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Verlag:
- Neue Suche nach: IEEE,
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Erscheinungsdatum:01.01.2005
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Format / Umfang:4 pages
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Anmerkungen:Also known as ASICON 2005. IEEE cat no: 05TH8820
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ISBN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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T-1 Therma-Aware Design Techniques for Nanometer VLSI ChipXie, Y. / IEEE et al. | 2005
- 1
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Tutorial 1 Thermal-Aware Design Techniques for Nanometer VLSI ChipYuan Xie, / Zhigang Hu, et al. | 2005
- 1
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A low-swing differential interface circuit for high-speed on-chip asynchronous interconnectionHuazhong Yang, / Fei Qiao, / Gang Huang, / Hui Wang, et al. | 2005
- 2
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Tutorial 2 Challenge to ASIC Design for Future Wireless CommunicationLin Yang, et al. | 2005
- 2
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T-2 Challenge to ASIC Design for future CommunicationYang, L. / IEEE et al. | 2005
- 3
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S-1 Power Reduction in High-Speed Inter-Chip Data CommunicationsKuroda, T. / IEEE et al. | 2005
- 6
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Floating-point unit processing denormalized numbersLi Zheng, / He Hu, / Sun Yihe, et al. | 2005
- 8
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S-2 Low Power Design for Embedded Systems: Today and TomorrowZafalon, R. / IEEE et al. | 2005
- 9
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S-3 Recent Results in Low Power ResearchWong, M. D. F. / IEEE et al. | 2005
- 10
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Fast and efficiently binding of functional units for low power designZhipeng Liu, / Jinian Bian, / Jianfeng Huang, / Yunfeng Wang, et al. | 2005
- 11
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S-4 Challengers in the Design of Transceivers for 802.11 Wireless LAN Systems: Past, Present and FutureZagari, M. / IEEE et al. | 2005
- 14
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Fast algorithm for leakage power reduction by input vector controlXiaotao Chang, / Dongrui Fan, / Yinhe Han, / Zhimin Zhang, / Xiaowei Li, et al. | 2005
- 15
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S-5 CMOS RF transcer design, from systems to chipsZhang, P. / IEEE et al. | 2005
- 19
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Low power SRAM design using charge sharing techniqueGu Ming, / Yang Jun, / Xue Jun, et al. | 2005
- 21
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S-6 Techniques for CMOS Single Photon Imaging and ProcessingCharbon, E. / IEEE et al. | 2005
- 24
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An optimization of VLSI architecture for DFE used in EthernetWang Xuejing, / Ye Fan, / Ren Junyan, et al. | 2005
- 27
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S-7 Challenge and Opportunity in Analog and RF ElectronicsMashiko, K. / IEEE et al. | 2005
- 32
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S-8 Design for Manufacturability: Challenges and OpportunitiesSylvester, D. / IEEE et al. | 2005
- 33
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SLCAO: an effective system level communication architectures optimization methodology for system-on- chipsYawen Niu, / Jinian Bian, / Haili Wang, / Kun Tong, / Liang Zhu, et al. | 2005
- 35
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S-9 Lithography-Aware Physical DesignPan, D. Z. / IEEE et al. | 2005
- 37
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A low complexity near-lossless image compression method and its ASIC design for wireless endoscopy systemXiang Xie, / Guo Lin Li, / Xin Kai Chen, / Chun Zhang, / Zhi Hua Wang, et al. | 2005
- 37
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S-10 Taming the DFM Beast into Adorable Pet-A Comprehensive ApproachPitchumani, V. / IEEE et al. | 2005
- 38
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S-11 Design for Manufacturing with Increasing VariabilityLin, X.-W. / IEEE et al. | 2005
- 41
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SoC design environment with automated configurable bus generation for rapid prototypingSang-Heon Lee, / Jae-Gon Lee, / Seonpil Kim, / Woong Hwangbo, / Chong-Min Kyung, et al. | 2005
- 43
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1.1-I SOC Logic Development Using Configurable, Application-Specific ProcessorsLeibson, S. / IEEE et al. | 2005
- 44
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1.1-C An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-ChipTabrizi, N. / Bagherzadeh, N. / IEEE et al. | 2005
- 46
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An ASIC design of a novel pipelined and parallel sorting accelerator for a multiprocessor-on-a-chipTabrizi, N. / Bagherzadeh, N. et al. | 2005
- 48
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1.2-C Optimizing SoC Platform Architecture for Multimedia ApplicationsTang, L. / Yang, Y. / Wei, S. / IEEE et al. | 2005
- 50
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SOC logic development using configurable, application-specific processorsLeibson, S. et al. | 2005
- 51
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Design of low-power double-edge triggered flip-flopYu Chien-Cheng, / Chin Ping-Yuan, et al. | 2005
- 52
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1.3-C Implementation of Adaptive Blind Equalizer with Carrier Recovery for QAM Receiver ChipZhang, Y. / Yu, L. / IEEE et al. | 2005
- 53
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Leading zero anticipation for latency improvement in floating-point fused multiply-add unitsMei Xiao-Lu, et al. | 2005
- 57
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A 64/spl times/64-bit modified Booth multiplier utilizing multiplexer-select Booth encoderXinyu Wu, / Chi Huang, / Jinmei Lai, / Chenshou Sun, et al. | 2005
- 58
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1.4-C A Low Power VLSI Implementation for JPEG2000 CodecMeng, Y. / Liu, L. / Li, G. / Zhang, L. / Wang, Z. / IEEE et al. | 2005
- 62
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An innovative design of the DDR/DDR2 SDRAM compatible controllerChen Shuang-yan, / Wang Dong-hui, / Shan Rui, / Hou Chao-huan, et al. | 2005
- 62
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1.5-C Evaluation of Thermal-Aware Design Techniques for MicroprocessorsRichardson, T. D. / Xie, Y. / IEEE et al. | 2005
- 66
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A ew Charge-Pump based Countermeasure against ifferential Power AnalysisCorsonello, P. / Perri, S. / Margala, M. et al. | 2005
- 66
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1.6-C A New Charge-pump Based Countermeasure Against Differential Power AnalysisCorsonello, P. / Perri, S. / Margala, M. / IEEE et al. | 2005
- 68
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Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation acceleratorJae-Gon Lee, / Woong Hwangbo, / Seonpil Kim, / Chong-Min Kyung, et al. | 2005
- 70
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1.2-I On-Chip Decoupling Chapacitor Budgeting By Sequence of Linear ProgrammingQi, Z. / Li, H. / Tan, S. X.-D. / Cai, Y. / Hong, X. / IEEE et al. | 2005
- 73
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Low power set-associative cache with single-cycle partial tag comparisonJian Chen, / Ruihua Peng, / Yuzhuo Fu, et al. | 2005
- 74
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1.7-C A Novel Asynchronous Multiple Function Multiple-accumulatorGao, J. / Chen, J. / IEEE et al. | 2005
- 78
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1.8-C Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage ScalingMeng, Y. / Liu, L. / Zhang, L. / Wang, Z. / IEEE et al. | 2005
- 78
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Hardware-software partition of fixed-point hardware accelerator from statistical perspectiveFan Zhou, / Jun Yang, / Longxing Shi, / Yu Zhang, et al. | 2005
- 82
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1.9-C A Hardware Efficient VLSI Architecture For FFT Processor in OFDM SystemsWu, J. / Liu, K. / Shen, B. / Min, H. / IEEE et al. | 2005
- 82
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A high-speed low-power D flip-flopChandrasekaran, R. / Yong Lian, / Ram Singh Rana, et al. | 2005
- 86
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1.10-C A Low-Swing Differential Interface Circuit for High-Speed On-Chip Asynchronous InterconnectionYang, H. / Qiao, F. / Huang, G. / Wang, H. / IEEE et al. | 2005
- 86
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Challenges in PowerPC440-FS soft core development: timing perspectiveBiggs, T. / Umino, K. / Kaijian Shi, et al. | 2005
- 90
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Duplicated register file design for embedded simultaneous multithreading microprocessorChengjie Zang, / Imai, S. / Kimura, S. et al. | 2005
- 90
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1.11-C Floating-Point Unit Processing Denormalized NumbersLi, Z. / He, H. / Sun, Y. / IEEE et al. | 2005
- 94
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1.12-C Fast and Efficiently Binding of Functional Units For Low Power DesignLiu, Z. / Bian, J. / Huang, J. / Wang, Y. / IEEE et al. | 2005
- 94
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Optimizing SoC platform architecture for multimedia applicationsTang Lei, / Yang Yanhui, / Wei Shaojun, et al. | 2005
- 98
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1.13-C Fast Algorithm for Leakage Power Reduction by Input Vector ControlChang, X. / Fan, D. / Han, Y. / Zhang, Z. / Li, X. / IEEE et al. | 2005
- 98
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On-chip decoupling capacitor budgeting by sequence of linear programmingZhenyu Qi, / Hang Li, / Tan, S.X.-D. / Yici Cai, / Xianlong Hong, et al. | 2005
- 102
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1.14-C Low Power SRAM Design Using Charge Sharing TechniqueGu, M. / Yang, J. / Xue, J. / IEEE et al. | 2005
- 102
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Codes reallocation and prediction for power efficiency in I-cache memoryZhu Xiaoping, / Tay Teng Tiow, et al. | 2005
- 106
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1.15-C An Optimization of VLSI Architecture for DFE Used in EthernetWang, X. / Ye, F. / Ren, J. / IEEE et al. | 2005
- 107
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An efficient low complexity LDPC encoder based on LU factorization with pivotingJia-ning Su, / Zhou Jiang, / Ke Liu, / Xiao-yang Zeng, / Hao Min, et al. | 2005
- 110
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1.16-C iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target EnvironmentLee, J.-G. / Kim, H.-O. / Na, S. / Kim, Y.-I. / Kyung, C.-M. / IEEE et al. | 2005
- 110
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iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target EnvironmentJae-Gon Lee, / Hyung-Ock Kim, / Sangkwon Na, / Young-Il Kim, / Chong-Min Kyung, et al. | 2005
- 111
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To improve the voice quality over IP using channel codingAgrawal, R. / Gupta, N. et al. | 2005
- 114
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1.17-C SLCAO: An Effective System Level Communication Architectures Optimization Methodology for System-on-ChipsNiu, Y. / Bian, J. / Wang, H. / Tong, K. / Zhu, L. / IEEE et al. | 2005
- 118
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1.18-C A Low Complexity Near-lossless Image Compression Method and its ASIC Design for Wireless Endoscopy SystemXie, X. / Li, G. / Chen, X. / Zhang, C. / Wang, Z. / IEEE et al. | 2005
- 122
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1.19-C SoC Design Environment with Automated Configurable Bus Generation for Rapid PrototypingLee, S.-H. / Lee, J.-G. / Kim, S. / Hwangbo, W. / Kyung, C.-M. / IEEE et al. | 2005
- 123
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Design of a high-speed low-power CAMCanghai Gu, / Hefei Zhu, / Xiaofang Zhou, / Hao Min, / Dian Zhou, et al. | 2005
- 126
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1.20-C Design of Low-Power Double-Edge Triggered Flip-FlopYu, C.-C. / Chin, P.-Y. / IEEE et al. | 2005
- 128
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An efficient algorithm for nonpreemptive periodic task scheduling under energy constraintsYufeng Xie, / Zuodong Wang, / Shaojun Wei, et al. | 2005
- 128
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1.21-C Leading Zero Anticipation for Latency Improvement in Floating-Point Fused Multiply-Add UnitsMei, X. / IEEE et al. | 2005
- 132
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1.22-C A 64x64-bit Modified Booth Multiplier Utilizing Multiplexer-Select Booth EncoderWu, X. / Huang, C. / Lai, J. / Sun, C. / IEEE et al. | 2005
- 132
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High speed sense amplifier circuit for low-voltage SONOS memory systemsGuangjun yang, / Liyang pan, / Dong wu, / Jun zhu, et al. | 2005
- 136
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1.23-C An Innovative Design of the DDR/DDR2 SDRAM Compatible ControllerChen, S. / Wang, D. / Shan, R. / Hou, C. / IEEE et al. | 2005
- 137
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Bus buffer modeling and optimization for a microprocessorXufan Wu, / Jun Yang, / Longxing Shi, et al. | 2005
- 140
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1.24-C Top-down Implementation of Pipelined AES Cipher and its Verification with FPGA-based Simulation AcceleratorLee, J.-G. / Hwangbo, W. / Kim, S. / Kyung, C.-M. / IEEE et al. | 2005
- 143
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A low-power baseband-processor for UHF RFID tagHe Yan, / Hu Jianyun, / Li Qiang, / Min Hao, et al. | 2005
- 144
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1.25-C Low Power Set-Associative Cache with Single-Cycle Partial Tag ComparisonChen, J. / Peng, R. / Fu, Y. / IEEE et al. | 2005
- 147
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Implementation of adaptive blind equalizer with carrier recovery for QAM receiver chipYongxue Zhang, / Lixin Yu, et al. | 2005
- 148
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1.26-C Hardware-Software partition of Fixed-point hardware Accelerator from Statistical PerspectiveZhou, F. / Yang, J. / Shi, L. / Zhang, Y. / IEEE et al. | 2005
- 152
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1.27-C A High-Speed Low-Power D Flip-FlopChandrasekaran, R. / Lian, Y. / Rana, R. S. / IEEE et al. | 2005
- 153
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High speed radix-16 design of a scalable Montgomery multiplierYibo Fan, / Xiaoyang Zeng, / Yu Yu, / Gang Wang, / Huang Deng, / Qianling Zhang, et al. | 2005
- 156
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1.28-C Challenges in PowerPC440-FS Soft Core Development: Timing perspectiveBiggs, T. / Umino, K. / Shi, K. / IEEE et al. | 2005
- 158
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Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS techniqueKe Wu, / Song Jia, / Zhongjian Chen, / Xuewen Gan, et al. | 2005
- 160
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1.29-C Duplicated Register File Design for Embedded Simultaneous Multithreading MicroprocessorZang, C. / Imai, S. / Kimura, S. / IEEE et al. | 2005
- 163
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A new HW/SW co-design methodology to generate a system level platform based on LISAShao Yang, / Yu Qian, / Zhang Tie-Jun, / Shan Rui, / Hou Chao-Huan, et al. | 2005
- 164
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1.30-C Codes Reallocation and Prediction For Power Efficiency in I-Cache MemoryZhu, X. / Tiow, T. T. / IEEE et al. | 2005
- 168
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1.31-C An Efficient Low Complexity LDPC Encoders Based on LU Factorization With PivotingSu, J. / Jiang, Z. / Liu, K. / Zeng, X. / Min, H. / IEEE et al. | 2005
- 169
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New methods of FPGA co-verification for system on chip (SoC)Lin Yi-fan, / Zeng Xiao-yang, / Wu Min, / Chen Jun, / Bao Rencheng, et al. | 2005
- 172
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1.32-C To Improve The Voice Quality Over IP Using Channel CodingAgrawal, R. / Gupta, N. / IEEE et al. | 2005
- 173
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VLSI architecture of EBCOT tier-2 encoder for JPEG2000Leibo Liu, / Ning Chen, / Li Zhang, / Zhihua Wang, et al. | 2005
- 179
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1.33-C Considering The Effect Of Standard Cell Placement in Mixed-Size PlacementYan, H. / Hong, X. / Zhou, Q. / Li, Z. / Yang, H. H. / IEEE et al. | 2005
- 179
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Considering The ffect Of Standard Cell Placement In Mi ed-Size PlacementAi Ia An, / Ianlong Ong, / Iang Hou, / Huoyuan I, / Annah Onghua Ang, et al. | 2005
- 181
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Flexible platform design of IEEE 802.15.3a MAC over UWB with optimized protocol acceleratorYu Cai, / Yaohui Wu, / Hui Li, / Feng Liang, / Zucheng Zhou, et al. | 2005
- 183
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1.34-P Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage ScalingMeng, Y. / Liu, L. / Zhang, L. / Wang, Z. / IEEE et al. | 2005
- 183
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Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage ScalingYicong Meng, / Leibo Liu, / Li Zhang, / Zhihua Wang, et al. | 2005
- 185
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Low-power adiabatic sequential circuits using two-phase power-clock supplyYangbo Wu, / Huiying Dong, / Yi Wang, / Jianping Hu, et al. | 2005
- 187
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1.35-P Design of A High-speed Low-Power CAMGu, C. / Zhu, H. / Zhou, X. / Min, H. / Zhou, D. / IEEE et al. | 2005
- 189
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A hardware architecture of MIMO-OFDM synchronizerHao Xuefei, / Chen Jie, et al. | 2005
- 191
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1.36-P An efficient algorithm for nonpreemptive periodic task scheduling under energy constraintsXie, Y. / Wang, Z. / Wei, S. / IEEE et al. | 2005
- 195
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1.37-P High Speed Sense Amplifier Circuit for Low-Voltage SONOS Memory SystemsYang, G. / Pan, L. / Wu, D. / Zhu, J. / IEEE et al. | 2005
- 198
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A low power VLSI implementation for JPEG2000 codecYicong Meng, / LeiboLiu, / Li Zhang, / Zhihua Wang, et al. | 2005
- 199
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1.38-P Bus Buffer Modeling and Optimization for a MicroprocessorWu, X. / Yang, J. / Shi, L. / IEEE et al. | 2005
- 203
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1.39-P A Low-power Baseband-processor for UHF RFID TagHe, Y. / Hu, J. / Li, Q. / Min, H. / IEEE et al. | 2005
- 203
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Performance exploration and optimization of SDRAM-controller architecture on SDRAM accessZhang Yu, / Ling Ming, / Pu Hanlai, / Zhou Fan, et al. | 2005
- 207
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1.40-P High Speed RADIX-16 Design of A Scalable MONTGOMERY MultiplierFan, Y. / Zeng, X. / Yu, Y. / Wang, G. / Deng, H. / Zhang, Q. / IEEE et al. | 2005
- 208
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Low-power FIR filter based on standard cellQi Yue, / Li Zhancai, / Wang Qin, et al. | 2005
- 211
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1.41-P Implementation of Low-Voltage True-Single-Phase-Clocking (TSPC) Logic using Bulk Dynamic Threshold MOS TechniqueWu, K. / Jia, S. / Chen, Z. / Gan, X. / IEEE et al. | 2005
- 212
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Processor design considerations for wireless sensor networkYongjun Xu, / Lingyi Liu, / Peifu Shen, / Tao Lv, / Xiaowei Li, et al. | 2005
- 215
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1.42-P A New HW/SW Co-design methodology to Generate a System Level Platform Based on LISAShao, Y. / Yu, Q. / Zhang, T.-J. / Shan, R. / Hou, C. / IEEE et al. | 2005
- 215
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Evaluation of thermal-aware design techniques for microprocessorsRichardson, T.D. / Yuan Xie, et al. | 2005
- 219
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1.43-P New Methods of FPGA co-verification for System on Chip (SoC)Lin, Y. / Zeng, X. / Wu, M. / Chen, J. / Bao, R. / IEEE et al. | 2005
- 223
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1.44-P VLSI Architecture of EBCOT Tier-2 Encoder for JPEG2000Liu, L. / Chen, N. / Zhang, L. / Wang, Z. / IEEE et al. | 2005
- 223
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A novel asynchronous multiple function multiply-accumulatorJian Gao, / Jie Chen, et al. | 2005
- 227
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An Itra-high Speed Real-time T ProcessorShiqun hang, / Dunshan Yu, / Shimin Sheng, et al. | 2005
- 227
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1.45-P An Ultra-high Speed Real-time FFT ProcessorZhang, S. / Yu, D. / Sheng, S. / IEEE et al. | 2005
- 231
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1.46-P Flexible Platform Design of IEEE 802.15.3a MAC over UWB with Optimized Protocol AcceleratorCai, Y. / Wu, Y. / Li, H. / Liang, F. / Zhou, Z. / IEEE et al. | 2005
- 232
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A hardware efficient VLSI architecture for FFT processor in OFDM systemsJianming Wu, / Ke Liu, / Bo Shen, / Hao Min, et al. | 2005
- 235
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1.47-P Low-Power Adiabatic Sequential Circuits Using Two-Phase Power-Clock SupplyWu, Y. / Dong, H. / Wang, Y. / Hu, J. / IEEE et al. | 2005
- 236
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An efficient equalizer for DVB-T receiversLiu Zhi, / Jiang Zhou, / Wang Jing, / Huang Chenling, / Zeng Xiaoyang, et al. | 2005
- 239
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1.48-P A Hardware Architecture of MIMO-OFDM SynchronizerHao, X. / Chen, J. / IEEE et al. | 2005
- 240
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A new algorithm of digital matched filter with a segment processing methodXuan Guan, / Jie Chen, et al. | 2005
- 243
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1.49-P Hardware/Software Co-design of a Java Co-processor for a 32-bit RISC system and the implementation of the Hardware partitionWang, F. / Yu, Y. / Zhou, X. / Min, H. / Zhou, D. / IEEE et al. | 2005
- 243
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AR AR /SO T AR CO- SI O A AVA CO-PROC SSOR OR A 3 -BIT RISC S ST MA T IMP M TATIO O T AR AR PARTITIOFang Wang, / Yu Yu, / Xiaofang Hou, / Hao Min, / Dian Hou, et al. | 2005
- 244
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An implemented VLSI architecture of inverse quantizer for AVS HDTV video decoderBin Sheng, / Wen Gao, / Di Wu, et al. | 2005
- 247
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1.50-P Performance Exploration and Optimization of SDRAM-Controller Architecture on SDRAM AccessZhang, Y. / Ling, M. / Pu, H. / Zhou, F. / IEEE et al. | 2005
- 248
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CMOS digital integrated temperature sensorZeng Jianping, / Li Yu, / Xie Haiqing, / Wen Jian, et al. | 2005
- 251
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1.51-P Low-power FIR Filter Based on Standard CellQi, Y. / Li, Z. / Wang, Q. / IEEE et al. | 2005
- 253
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Clarifying the chaotic phenomenon in an MESFET oscillator by Lur's system formHsi-Chiang Chou, / Ming Chou Liao, / Chi-Jung Chung, et al. | 2005
- 255
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1.52-P Processor Design Considerations for Wireless Sensor NetworkXu, Y. / Liu, L. / Shen, P. / Lv, T. / Li, X. / IEEE et al. | 2005
- 257
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VLSI architectures of domain adaptive fuzzy logic systemZhang Xun, / Wang Peng, / Jin Dongming, et al. | 2005
- 258
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2.1-I High-performance and Low-voltage Challenges for Sub-45nm Microprocessor CircuitsKrishnamurthy, R. K. / Mathew, S. K. / Anders, M. A. / Hsu, S. K. / Kaul, H. / Borkar, S. / IEEE et al. | 2005
- 261
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A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000Yi-Zhen Zhang, / Chao Xu, / Liang-Bin Chen, et al. | 2005
- 262
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2.1-C A VLSI Architecture for Motion Compensation Interpolation in H.264/AVCSong, Y. / Liu, Z. / Goto, S. / Ikenaga, T. / IEEE et al. | 2005
- 265
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Reconfigurable VLSI architecture for VBSME in MPEG-4 AVC/H.264Cao Wei, / Mao Zhi Gang, et al. | 2005
- 266
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2.2-C A Design of 500MHz 10-Read 6-Write Register FileYu, Q. / Wang, D.-h. / Zhang, T.-j. / Hou, C.-h. / IEEE et al. | 2005
- 270
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2.3-C A Low-Power Complementary Pass-Transistor Adiabatic Multiplier Based on 4-2 CompressorsYe, X. / Hu, J. / Tao, W. / IEEE et al. | 2005
- 270
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A novel synchronization scheme in HDTV system with adaptive detection and low implementation complexityKe Liu, / Huarong Zheng, / Jianing Su, / Bo Shen, / Hao Min, et al. | 2005
- 274
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2.4-C An Efficient Architecture for Computing Division over GF(2m)Zhou, J. / Jiang, X. / Chen, H. / IEEE et al. | 2005
- 278
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2.5-C Silent CMOS Circuits Aiming for System-on-ChipYuan, J. / IEEE et al. | 2005
- 279
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A VLSI architecture for motion compensation interpolation in H.264/AVCYang Song, / Zhenyu Liu, / Goto, S. / Ikenaga, T. et al. | 2005
- 282
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2.6-C A Robust and Low Complexity Implementation of Synchronization for DVB-T ReceiverZheng, H. / Yan, J. / Su, J. / Zeng, X. / IEEE et al. | 2005
- 283
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High-performance and low-voltage challenges for sub-45nm microprocessor circuitsKrishnamurthy, R.K. / Mathew, S.K. / Anders, M.A. / Hsu, S.K. / Kaul, H. / Borkar, S. et al. | 2005
- 286
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2.7-C Area-efficient VLSI Architecture of Joint Carrier Recovery and Blind Equalization For QAM DemodulatorJiang, Z. / Tian, J. / Liu, Z. / Zeng, X. / IEEE et al. | 2005
- 287
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Design of adiabatic multi-port register fileWang Fang, / Jia Song, / Ji Lijiu, et al. | 2005
- 290
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2.8-C A High-Performance Low-Power 2-D 8x8 IDCT Processor with Asynchronous PipelineMa, X. / Gao, J. / Chen, J. / IEEE et al. | 2005
- 291
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Microprocessor development using SFL for educational purposesKhongsomboon, K. / Kondoh, N. / Shimizu, N. et al. | 2005
- 294
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2.9-C A Modified Decimation Filter Design for Oversampled Sigma Delta A/D ConvertersChen, L. / Zhao, Y. / Gao, D. / Wen, W. / Wang, Z. / Zhu, X. / Peng, H. / IEEE et al. | 2005
- 294
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A Modified ecimation ilter esign for Oversampled Sigma elta A/ ConvertersChen Lei, / Zhao Yuanfu, / Gao Deyuan, / Wen Wu, / Wang Zongmin, / Zhu Xiaofei, / Peng Heping, et al. | 2005
- 295
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Theory of current transmission switches and its application to design of a novel current-mode CMOS ternary Schmitt triggerGuoqiang Hang, et al. | 2005
- 298
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2.10-C An Efficient Equalizer for DVB-T ReceiversLiu, Z. / Jiang, Z. / Wang, J. / Huang, C. / Zeng, X. / IEEE et al. | 2005
- 300
-
Design and implementation of an EOS chipGe, L. / Yoshimura, T. et al. | 2005
- 302
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2.11-C A new algorithm of Digital Matched Filter with a Segment Processing MethodGuan, X. / Hu, D. / Chen, J. / IEEE et al. | 2005
- 304
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Five-valued circuit quantitative theory and design of five-valued twisted-ring counterWang, P. / Ying Liu, / Yang, M. / Almaini, A.E.A. et al. | 2005
- 306
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2.12-C An Implemented VLSI Architecture of Inverse Quantizer for AVS HDTV Video DecoderSheng, B. / Gao, W. / Wu, D. / IEEE et al. | 2005
- 309
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A voltage level converter circuit design with low power consumptionChin Ping-Yuan, / Yu Chien-Cheng, et al. | 2005
- 310
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2.13-C CMOS Digital Integrated Temperature SensorZeng, J. / Li, Y. / Xie, H. / Wen, J. / IEEE et al. | 2005
- 311
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A design of 500MHz 10-read 6-write register fileYu Qian, / Wang Dong-hui, / Zhang Tie-jun, / Hou Chao-huan, et al. | 2005
- 314
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2.14-C Clarifying the chaotic Phenomenon in an MESFET Oscillator by Lur's System FormChou, H.-C. / Liao, M. C. / Chung, C.-J. / IEEE et al. | 2005
- 317
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A low-power complementary pass-transistor tree multiplier based on adiabatic 4-2 compressorsXien Ye, / Jianping Hu, / Weijiong Tao, et al. | 2005
- 318
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2.15-P VLSI Architectures of Domain Adaptive Fuzzy Logic SystemZhang, X. / Wang, P. / Jin, D.-m. / IEEE et al. | 2005
- 321
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An efficient architecture for computing division over GF(/sup 2/m) in elliptic curve cryptographyJian-Yang Zhou, / Xiao-Gang Jiang, / Hui-Huang Chen, et al. | 2005
- 322
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2.16-P A Dual-Symbol Coding Arithmetic Coder Architecture Desigh For High Speed EBCOT Coding Engine In JPEG2000Zhang, Y.-Z. / Xu, C. / Chen, L.-B. / IEEE et al. | 2005
- 326
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2.17-P Reconfigurable VLSI Architecture for VBSME in MPEG-4 AVC/H.264Chao, W. / Mao, Z. / IEEE et al. | 2005
- 327
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Silent CMOS circuits aiming for system-on-chipJiren Yuan, et al. | 2005
- 330
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2.18-P A Novel Synchronization Scheme in HDTV System with Adaptive Detection and Low Implementation ComplexityLiu, K. / Zheng, H. / Su, J. / Shen, B. / Min, H. / IEEE et al. | 2005
- 332
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A robust and low complexity implementation of synchronization for DVB-T receiverHuarong Zheng, / Jiefeng Yan, / Jianing Su, / Xiaoyang Zeng, et al. | 2005
- 334
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2.19-P Power Complexity Analysis of Adiabatic SRAMWang, F. / Jia, S. / Ji, L. / IEEE et al. | 2005
- 334
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Power Comple ity Analysis of Adiabatic SRAMang ang, / ia Song, / i ijiu, et al. | 2005
- 337
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Area-efficient VLSI architecture of joint carrier recovery and blind equalization for QAM demodulatorJiang Zhou, / Tian Junhua, / Liu Zhi, / Zeng Xiaoyang, et al. | 2005
- 338
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2.20-P Design of Adiabatic Multi-Port Register FileWang, F. / Jia, S. / Ji, L. / IEEE et al. | 2005
- 341
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A high-performance low-power 2D 8/spl times/8 IDCT processor with asynchronous pipelineXu Ma, / Jian Gao, / Jie Chen, et al. | 2005
- 342
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2.21-P Microprocessor Development using SFL for Education PurposeKhongsomboon, K. / Kondoh, N. / Shimizu, N. / IEEE et al. | 2005
- 346
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2.22-P Theory of current transmission switches and its application to design of a novel current-mode CMOS ternary Schmitt triggerHang, G. / IEEE et al. | 2005
- 350
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A novel method to realize automatic gain adjust for infrared readout integrated circuitLiu Dan, / Zhang Yacong, / Chen Zhongjian, / Zhao Baoying, / Ji Lijiu, et al. | 2005
- 350
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2.23-P Design and Implementation of an EOS ChipGe, L. / Yoshimura, T. / IEEE et al. | 2005
- 354
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2.24-P Five-Valued Circuit Quantitative Theory and Design of Five-Valued Twisted-ring CounterWang, P. / Liu, Y. / Yang, M. / Almaini, A. E. A. / IEEE et al. | 2005
- 355
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A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization techniqueZhanguo Xi, / Yajie Qin, / Zhiliang Hong, et al. | 2005
- 358
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2.25-P A Voltage Level Converter Circuit Design with Low Power ConsumptionChi, P.-Y. / Yu, C.-C. / IEEE et al. | 2005
- 360
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A 2.4 GHz Fully Integrated Class-A Power Ampifier In 0.35μm SiGe BiCMOS TechnologyWang, A. / Xiaokang Guan, / Haigang Feng, / Qu Wu, / Rouying Zhan, / Li-Wu Yang, et al. | 2005
- 360
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A new structure of low-noise CMOS differential amplifierWei Lan, / Gao Jim, / Chen Zhongjian, / Ji Lijiu, et al. | 2005
- 360
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3.1-I A 2.4 GHz Fully Integrated Class-A Power Amplifier In 0.35 mu m SiGe BiCMOS TechnologyWang, A. / Guan, X. / Feng, H. / Wu, Q. / Zhan, R. / Yang, L.-W. / IEEE et al. | 2005
- 364
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3.1-C High Efficiency, Inductorless Step-Down DC/DC ConverterShao, B. / Yang, Y. / Wang, Y. / Hong, Z. / IEEE et al. | 2005
- 365
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A fully CMOS-integrated pH-ISFET interface circuitJinbao Wei, / Haigang Yang, / Hongguang Sun, / Zengjin Lin, / Shanhong Xia, et al. | 2005
- 368
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3.2-C A Novel Minimum-Voltage Active-Clamping PFC ControllerQin, S. / Wu, X. / Yan, X. / IEEE et al. | 2005
- 369
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A novel low-voltage low-power CMOS voltage reference based on subthreshold MOSFETsWang Jianping, / Lai Xinquan, / Li Yushan, / Zhang Jie, / Guo Xiaofeng, et al. | 2005
- 372
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3.3-C Analysis and Design of Makowski Charge-Pump CellLiu, L. / Chen, Z. / IEEE et al. | 2005
- 374
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A direct conversion WLAN receiverJingguang Wang, / Jinju Wang, / Yumei Huang, / Weilun Shen, / Xiaofeng Yi, / Zhiliang Hong, et al. | 2005
- 377
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3.4-C Design and Application of the Novel Low-Threshold Comparator Using HysteresisGuo, X. / Lai, X. / Li, Y. / Wang, J. / Zhang, J. / IEEE et al. | 2005
- 378
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A 10-bit 30-MS/s 50mW pipelined A/D converterChen Xi, / He Lenian, / Yan Xiaolang, et al. | 2005
- 381
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3.5-C A 2.4-GHz Fully CMOS Integrated Transmitter for 802.11b Wireless LANHe, J. / Gao, X. / Shen, W. / Yi, X. / Huang, Y. / Hong, Z. / IEEE et al. | 2005
- 381
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A 2.4-GHz Fully CMOS Integrated Transmitter for 802.1lb Wireless LANJirou He, / Xiaoping Gao, / Weilun Shen, / Xiaofeng Yi, / Yumei Huang, / Zhiliang Hong, et al. | 2005
- 383
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A fast locking charge-pump PLL with adaptive bandwidthYan Ge, / Wennan Feng, / Zhongjian Chen, / Song Jia, / Lijiu Ji, et al. | 2005
- 385
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3.6-C Wideband Two-Integrator Oscillator-MixerOliveira, L. B. / Fernandes, J. R. / Filanovsky, I. M. / Verhoeven / IEEE et al. | 2005
- 387
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A new high-speed low-voltage charge pump for PLL applicationsHong Yu, / Yasuaki Inoue, / Yan Han, et al. | 2005
- 389
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3.7-C On-Chip DC-DC Voltage Down Converter for Low-Power IC ChipZhou, Q. / Yu, M. / IEEE et al. | 2005
- 391
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A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiverLu Ping, / Wang Yan, / Li Lian, / Ren Junyan, et al. | 2005
- 393
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3.8-C Design of A Switched-current High-speed Truly Random Number GeneratorZhou, T. / Yu, M. / Ye, Y.-z. / IEEE et al. | 2005
- 395
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High efficiency, inductorless step-down DC/DC converterShao Bin, / Yang Yujia, / Wang Ying, / Hong Zhiliang, et al. | 2005
- 397
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3.9-C An Automatic calibration technique for the OPAMP and Its Former Stage Output OffsetGuo, S. / Qiu, Y. / IEEE et al. | 2005
- 401
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3.10-C A Novel Method to Realize Automatic Gain Adjust for Infrared Readout Integrated CircuitLiu, D. / Zhang, Y. / Chen, Z. / Lu, W. / IEEE et al. | 2005
- 403
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A self-powered sensor module using vibration-based energy generation for ubiquitous systemsJun Pan, / Baocheng Xue, / Inoue, Y. et al. | 2005
- 405
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3.11-C A 3.3-V, 1.9-GHz, High Linear CMOS Up-Mixer With Multi-tanh Linearization TechniqueXi, Z.-g. / Qin, Y.-j. / Hong, Z. / IEEE et al. | 2005
- 407
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A CMOS differential current-controlled second generation current conveyorWang Chunhua, / Li Jin, et al. | 2005
- 410
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3.12-C A New Structure of Low-Noise CMOS Differential AmplifierWei, L. / Gao, J. / Chen, Z. / Ji, L. / IEEE et al. | 2005
- 411
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A 12-bit 250-MHz current-steering DACChun-Yueh Huang, / Tsung-Tien Hou, / Hung-Yu Wang, et al. | 2005
- 414
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3.13-C A Fully CMOS-integrated pH-ISFET Interface CircuitWei, J. / Yang, H. / Sun, H. / Lin, Z. / Xia, S. / IEEE et al. | 2005
- 415
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A 1.8V transmitter for 10/100 Mbps Ethernet physical layerTao Cheng, / Yang Li, / Li Ning, / Lu Ping, / Ren Junyan, / Li Lian, et al. | 2005
- 417
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3.2-I Non-Traditional Architectures for AD- and DA-ConvertersSignell, S. / IEEE et al. | 2005
- 419
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A method to effectively decrease the settling time of gain-boost OTAFeipeng Huang, / Yumei Huang, / Dedong Ze, / Zhiliang Hong, et al. | 2005
- 419
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3.14-C A Novel Low-voltage Low-power CMOS Voltage Reference Based on Subthreshold MOSFETsWang, J. / Lai, X. / Li, Y. / Zhang, J. / Guo, X. / IEEE et al. | 2005
- 423
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3.15-C A Direct Conversion WLAN ReceiverWang, J. / Huang, Y. / Shen, W. / Yi, X. / Hong, Z. / IEEE et al. | 2005
- 423
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A phase-locked loop for receivers of UHF wireless microphoneChun-Yueh Huang, / I-Jeng Chao, / Hung-Yu Wang, et al. | 2005
- 427
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3.16-C A 10-bit 30-MS/s 50mW Pipelined A/D ConverterChen, X. / He, L. / Yan, X. / IEEE et al. | 2005
- 431
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Circuit design and verification for ultra low current sensing amplifier aimed at bio-sensor applicationsLei Zhang, / Xiangqing He, / Zhiqing Yu, et al. | 2005
- 431
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3.17-C A Fast Locking Charge-Pump PLL with Adaptive BandwidthGe, Y. / Feng, W. / Chen, Z. / Song, J. / Ji, L. / IEEE et al. | 2005
- 435
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3.18-C A New High-Speed Low-Voltage Charge Pump for PLL ApplicationsYu, H. / Inoue, Y. / Han, Y. / IEEE et al. | 2005
- 436
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A novel clock and data recovery scheme based on sigma-delta quantizationYuyu Liu, / Ning Ge, / Huazhong Yang, / Hui Wang, et al. | 2005
- 439
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3.19-C A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiverLu, P. / Wang, Y. / Li, L. / Ren, J. / IEEE et al. | 2005
- 441
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Design of ultra wideband MOS differential VCOYan-qing Ning, / Zhi-hua Wang, / Hong-yi Chen, et al. | 2005
- 443
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3.20-C A Self-Powered Sensor Module Using Vibration-Based Energy Generation for Ubiquitous SystemsPan, J. / Xue, B. / Inoue, Y. / IEEE et al. | 2005
- 446
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A novel minimum-voltage active-clamping PFC controllerQin Song, / Wu Xiaobo, / Yan Xiaolang, et al. | 2005
- 447
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3.21-C A CMOS differential current-controlled second generation current conveyorWang, C. / Li, J. / IEEE et al. | 2005
- 451
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Non-traditional architectures for AD- and DA- convertersSignell, S. et al. | 2005
- 451
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3.22-C A 12-bit 250-MHz Current-Steering DACHuang, C.-Y. / Hou, T.-T. / Wang, H.-Y. / IEEE et al. | 2005
- 454
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A current-mode CMOS bandgap reference for differential signal processingDan Li, / Jinghua Ye, / Zhiliang Hong, et al. | 2005
- 455
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3.23-C A 1.8V Transmitter for 10/100 Mbps Ethernet Physical LayerTao, C. / Yang, L. / Li, N. / Lu, P. / Ren, J. / Li, L. / IEEE et al. | 2005
- 459
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On-chip boost DC-DC converter in color OLED driver & controller ICs for mobile applicationDing Ge, / Zhiliang Chen, et al. | 2005
- 459
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3.24-C A Method to Effectively Decrease the Settling Time of Gain-Boost OTAHuang, F. / Huang, Y. / Ze, D. / Hong, Z. / IEEE et al. | 2005
- 463
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3.25-C A Phase-Locked Loop for Receivers of UHF Wireless MicrophoneHuang, C.-Y. / Chao, I.-J. / Wang, H.-Y. / IEEE et al. | 2005
- 464
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An intuitive implementation of continuous-time Gm-C filterSha Li, / Chi Zhang, et al. | 2005
- 467
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A ully CMOS Integrated R Transceiver for biquitous Sensor etworks in Sub- z ISM-bandHae-Moon Seo, / Yeon-Kuk Moon, / Yong-Kuk Park, / Kwang-Ho Won, / Myung-Hyun Yoon, / Jun-Jae Yoo, / Sung-Dong Kim, et al. | 2005
- 467
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3.26-C A Fully CMOS Integrated RF Transceiver for Ubiquitous Sensor Networks in Sub-GHz ISM-BandSeo, H.-M. / Moon, Y.-K. / Park, Y.-K. / Won, K.-H. / Yoon, M.-H. / Yoo, J.-J. / Kim, S.-D. / IEEE et al. | 2005
- 469
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CMOS 1.5V bandgap voltage referenceMao Jingwen, / Chen Tingqian, / Chen Cheng, / Ren Junyan, / Yang Li, et al. | 2005
- 471
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3.27-C Circuit Design and Verification for Ultra Low Current Sensing Amplifier Aimed at Bio-Sensor ApplicationsZhang, L. / He, X. / Yu, Z. / IEEE et al. | 2005
- 473
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A mixed-signal driver chip for 65K-color passive-matrix OLEDWenyu Xiao, / Zhiliang Chen, et al. | 2005
- 475
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3.28-C A Novel Clock and Data Recovery Scheme Based on Sigma-Delta QuantizationLiu, Y. / Ge, N. / Yang, H. / Wang, H. / IEEE et al. | 2005
- 478
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A 40dB, 100MHz CMOS IF variable gain amplifier for DVB-C receiversTinghua Yun, / Li Yin, / Shoulong Tang, / Jianhui Wu, et al. | 2005
- 479
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3.29-C Design of Ultra Wideband MOS Differential VCONing, Y. / Wang, Z. / Chen, H. / IEEE et al. | 2005
- 483
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3.30-C A Current-mode CMOS Bandgap Reference for Differential Signal ProcessingLi, D. / Ye, J. / Hong, Z. / IEEE et al. | 2005
- 483
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The design of a start-up circuit for boost DC-DC converter with low supply voltageYuan Bing, / Lai Xinquan, / Wang Hongyi, / Wang Yi, et al. | 2005
- 487
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3.31-C On-Chip Boost DC-DC Converter in Color OLED Driver & Controller ICs for Mobile ApplicationGe, D. / Chen, Z. / IEEE et al. | 2005
- 488
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A CMOS correlator for UWB front-end circuitChunjiang Tu, / Boan Liu, / Hongyi Chen, et al. | 2005
- 491
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3.32-C An intuitive implementation of Continuous-Time Gm-C filterLi, S. / zhang, C. / IEEE et al. | 2005
- 493
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A 5-GHz CMOS quadrature modulator for direct conversion transmittersWen-Hu Zhao, et al. | 2005
- 495
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3.33-C CMOS 1.5V Bandgap Voltage ReferenceMao, J. / Chen, T. / Chen, C. / Ren, J. / Yang, L. / IEEE et al. | 2005
- 497
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Analysis and design of Makowski charge-pump cellLifang Liu, / Zhiliang Chen, et al. | 2005
- 499
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A New Structure for Capacitor-Mismatch-Insensitive Multiply-By-Two AmplificationZare-Hoseini, H. / Shoaei, O. / Kale, I. et al. | 2005
- 499
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3.34-C A New Structure for Capacitor-Mismatch-Insensitive Multiply-By-Two AmplificationShoaei, H. Z.-H. O. / Kale, I. / IEEE et al. | 2005
- 503
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A 14-/spl mu/A 3-ppm//spl deg/C CMOS bandgap voltage referenceChunhua Yao, / Boan Liu, / Yuwen Xia, et al. | 2005
- 504
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3.35-C A Mixed-Signal Driver Chip for 65K-Color Passive-Matrix OLEDXiao, W. / Chen, Z. / IEEE et al. | 2005
- 508
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3.36-C A 40dB, 100MHz CMOS IF Variable Gain Amplifier for DVB-C ReceiversYun, T. / Yin, L. / Tang, S. / Wu, J. / IEEE et al. | 2005
- 512
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3.37-P The Design of a Start-up Circuit for BOOST DC-DC Converter with Low Supply VoltageYuan, B. / Lai, X. / Wang, H. / Wang, Y. / IEEE et al. | 2005
- 512
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A new impedance matching method of CMOS mixer with common-source input stageTang Shou-long, et al. | 2005
- 516
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LCoS chip with integrated 8-bit gamma compensated digital data driver| 2005
- 516
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3.38-P A CMOS Correlator for UWB Front-end CircuitTu, C. / Liu, B. / Chen, H. / IEEE et al. | 2005
- 520
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3.39-P A 5-GHz CMOS Quadrature Modulator for Direct Conversion TransmittersZhao, W. / IEEE et al. | 2005
- 524
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3.40-P A 14-uA 3-ppm/^oC CMOS Bandgap Voltage ReferenceYao, C. / Liu, B. / Xia, Y. / IEEE et al. | 2005
- 525
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A fully integrated 1.2-GHz CMOS phase-locked loopKun Zhao, / Jiahan Man, / Qing Ye, / Tianchun Ye, et al. | 2005
- 528
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A BIPO AR Current Mirror ith ow VoltageChen Fuji, / Lai Xinquan, / Li Yushan, / Song Lijun, et al. | 2005
- 528
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3.41-P A BIPOLAR Current Mirror With Low VoltageChen, F. / Lai, X. / Li, Y. / Song, L. / IEEE et al. | 2005
- 529
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A curvature-compensated bandgap reference with improved PSRRXiao Du, / Li Wei-min, / Zhu Xiao-fei, / Fu Xiao-dong, et al. | 2005
- 532
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3.42-P A New Impedance Matching Method of CMOS Mixer with Common-Source Input StageTang, S. / IEEE et al. | 2005
- 534
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A low-voltage low-power CMOS sample-and-hold circuitZheng Xiao-yan, / Guo Shu-bao, / Wang Jiang, / Qiu Yu-lin, et al. | 2005
- 536
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3.43-P LCoS chip with integrated 8-bit Gamma Compensated Digital Data DriverDai, Y. / Geng, W. / Liu, Y. / Sun, Z. / IEEE et al. | 2005
- 539
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A low noise CMOS wideband PLL with a new AAC LC-VCOXuan Wu, / Wen Sun, / Zuotian Chen, / Longxin Shi, et al. | 2005
- 540
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3.44-P A Low-Phase-Noise CMOS Ring Oscillator with Differential ControlLu, Z. / Lai, F. / Ma, J. / IEEE et al. | 2005
- 540
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A ow-Phase- oise CMOS Ring Oscillator with ifferential Controlhi-Qiang Lu, / Feng-Chang Lai, / Jian-Guo Ma, et al. | 2005
- 544
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3.45-P A Fully Integrated 1.2-GHz CMOS Phase-Locked LoopZhao, K. / Man, J. / Ye, Q. / Ye, T. / IEEE et al. | 2005
- 544
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A high-accuracy BiCMOS constant current charge circuitChen Fuji, / Lai Xinquan, / Li Yushan, / Zhao Junhong, et al. | 2005
- 548
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3.46-P A Curvature-Compensated Bandgap Reference with Improved PSRRDu, X. / Li, W. / Zhu, X. / Fu, X. / IEEE et al. | 2005
- 549
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Design and application of the novel low-threshold comparator using hysteresisGuo Xiaofeng, / Lai Xinquan, / Li Yushan, / Wang Jianping, / Zhang Jie, et al. | 2005
- 552
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3.47-P A Low-Voltage Low-Power CMOS Sample-and-Hold CircuitZheng, X. / Guo, S. / Wang, J. / Qiu, Y. / IEEE et al. | 2005
- 554
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A novel digital soft-start circuit for DC-DC switching regulatorLai Xinquan, / Guo Jianping, / Yu Weixue, / Cao Yu, et al. | 2005
- 556
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3.48-P A Low Noise CMOS Wideband PLL with a New AAC LC-VCOWu, X. / Sun, W. / Chen, Z. / Shi, L. / IEEE et al. | 2005
- 559
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A low quiescent current and reset time adjustable power-on reset circuitLai Xinquan, / Yu Weixue, / Ligang, / Cao Yu, et al. | 2005
- 560
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3.49-P A High-Accuracy BiCMOS Constant Current Charge CircuitChen, F. / Lai, X. / Li, Y. / Zhao, J. / IEEE et al. | 2005
- 564
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A novel design of supply voltage selectorLai Xinquan, / Geng Weisheng, / Chen Fuji, / Dong Xianhui, et al. | 2005
- 564
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3.50-P A Novel Digital Soft-Start Circuit for DC-DC Switching RegulatorLai, X. / Guo, J. / Yu, W. / Cao, Y. / IEEE et al. | 2005
- 568
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The design of a novel feedforward control circuit for DC-DC converterLai Xinquan, / Wang Yi, / Yuan Bing, / Wang Hongyi, et al. | 2005
- 568
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3.51-P A Low Quiescent Current and Reset Time Adjustable Power-on Reset CircuitLai, X. / Yu, W. / Li, G. / Cao, Y. / IEEE et al. | 2005
- 572
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3.52-P A Novel Design of Supply Voltage SelectorLai, X. / Geng, W. / Chen, F. / Dong, X. / IEEE et al. | 2005
- 573
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Pulsed multilevel current drive circuitry with LDMOS for monolithic deformable mirrorTuo Wu, / Hongyi Chen, / Dahong Qian, et al. | 2005
- 576
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3.53-P The Design of a Novel Feed-Forward Control Circuit for DC-DC ConverterLai, X. / Wang, Y. / Yuan, B. / Wang, H. / IEEE et al. | 2005
- 578
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An improved charge pump with high efficiency for low voltage operationsNa Yan, / Hao Min, et al. | 2005
- 580
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3.54-P Pulsed multilevel current drive circuitry with LDMOS for Monolithic Deformable MirrorWu, T. / Chen, H. / Qian, D. / IEEE et al. | 2005
- 582
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A fully integrated 0.18-/spl mu/m CMOS low noise amplifier for 2.4-GHz applicationsYu Shen, / Huazhong Yang, / Rong Luo, et al. | 2005
- 584
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3.55-P An Improved Charge Pump with High Efficiency for Low Supply Voltages OperationsNa, Y. / Min, H. / IEEE et al. | 2005
- 587
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A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receiversYeon Kug Moon, / Hae-Moon Seo, / Kwang-Ho Won, / Yong-Kuk Park, / Myung-Hyun Yoon, / June-Jae Yoo, / Seong-Dong Kim, et al. | 2005
- 588
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3.56-P A Fully Integrated 0.18-um CMOS Low Noise Amplifier for 2.4-GHz ApplicationsShen, Y. / Yang, H. / Luo, R. / IEEE et al. | 2005
- 591
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Design of a DLL-gated 1.25G clock synthesizer for impulse UWB systemChen Chen, / Boan Liu, et al. | 2005
- 592
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3.57-P A CMOS Continuous-Time Gm-C Filter and Programmable Gain Amplifier for WPAN ReceiversMoon, Y. K. / Seo, H.-M. / Won, K.-H. / Park, Y.-K. / Yoon, M.-H. / Yoo, J.-J. / Kim, S.-D. / IEEE et al. | 2005
- 595
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High performance current comparator with gain boosting structureJie Fan, / Ju Tang, / Guizhen Yan, et al. | 2005
- 596
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3.58-P Design of a DLL-Based 1.25G Clock Synthesizer for Impulse UWB SystemChen, C. / Liu, B. / IEEE et al. | 2005
- 600
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3.59-P High Performance Current Comparator with Gain Boosting StructureFan, J. / Tang, J. / Yan, G. / IEEE et al. | 2005
- 603
-
A CMOS RF bandpass filter based on the active inductorZhiqiang Gao, / Jianguo Ma, / Mingyan Yu, / Yizheng Ye, et al. | 2005
- 604
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3.60-P A CMOS RF Bandpass Filter Based on The Active InductorGao, Z. / Ma, J. / Yu, M. / Ye, Y. / IEEE et al. | 2005
- 607
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High efficient rectifier circuit eliminating threshold voltage drop for RFID transpondersHu Jianyun, / He Yan, / Min Hao, et al. | 2005
- 608
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3.61-P High Efficient Rectifier Circuit Eliminating Threshold Voltage Drop for RFID TranspondersHu, J. / He, Y. / Min, H. / IEEE et al. | 2005
- 611
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A low phase noise VCO using enhanced LC resonator in an single-chip ASK receiverZheng Ren, / Yongsheng Xu, / Yanling Shi, / Yong Wang, / Yonggang Tao, et al. | 2005
- 612
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3.62-P A low Phase Noise VCO using Enhanced LC Resonator in an Single-Chip ASK ReceiverRen, Z. / Xu, Y. / Shi, Y. / Wang, Y. / Tao, Y. / IEEE et al. | 2005
- 616
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A design of high speed AGTL+ output bufferDonglin Wang, / Shaoqing Li, / Zhenyu Zhao, et al. | 2005
- 616
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3.63-P A Design of High Speed AGTL+ Output BufferWang, D. / Li, S. / Zhao, Z. / IEEE et al. | 2005
- 620
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3.64-P Design and Verification of CMOS HSTL Buffers-YF_HSTL018Gao, S. / Chen, J. / Ma, J. / Liu, T. / IEEE et al. | 2005
- 621
-
Design and verification of CMOS HSTL buffers - YF/spl I.bar/HSTL018Shaoquan Gao, / Jihua Chen, / Jianwu Ma, / Ting Liu, et al. | 2005
- 624
-
3.65-P A 5GHz CMOS Monolithic Fractional-N Frequency SynthesizerShen, W. / Hu, K. / Yi, X. / Zhou, Y. / Hong, Z. / IEEE et al. | 2005
- 626
-
A 5GHz CMOS monolithic fractional-N frequency synthesizerWeilun Shen, / Kangmin Hu, / Xiaofeng Yi, / Ye Zhou, / Zhiiang Hong, et al. | 2005
- 628
-
3.66-P Low noise operational amplifier design with current driving bulk in 0.25um CMOS technologyLi, Z. / Ma, J. / Yu, M. / Ye, Y. / IEEE et al. | 2005
- 630
-
Low noise operational amplifier design with current driving bulk in 0.25/spl mu/m CMOS technologyZhiyuan Li, / Jianguo Ma, / Mingyan Yu, / Yizheng Ye, et al. | 2005
- 633
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3.67-P CMOS-Based Gas Sensor: SoC ApproachMohd-Yasin, F. / Tye, K. F. / Lee, C. Y. / Reaz, M. B. I. / IEEE et al. | 2005
- 635
-
3.68-P Implement Any Fractional Order Multilayer Dynamics Associative Neural NetworkPu, Y. / IEEE et al. | 2005
- 635
-
CMOS-based gas sensor: SoC approachMohd-Yasin, F. / Tye, K.F. / Lee, C.Y. / Reaz, M.B.L. et al. | 2005
- 638
-
Implement any fractional order multilayer dynamics associative neural networkPu Yifei, et al. | 2005
- 639
-
4.1-I Test Modification and Compression Technique for Reducing Total Test Volume with Dictionary DataHayashi, T. / Hiraiwa, N. / Shinogi, T. / Takase, H. / Kita, H. / IEEE et al. | 2005
- 642
-
Wideband two-integrator oscillator-mixerOliveira, L.B. / Fernandes, J.R. / Filanovsky, I.M. / Verhoeven, C.J.M. et al. | 2005
- 645
-
4.1-C A Current Sensing Circuit for IDDQ TestingKim, T. S. / Hong, S. H. / Kim, J. B. / IEEE et al. | 2005
- 646
-
On-chip DC-DC voltage down converter for low-power IC chipQianneng Zhou, / Mingyan Yu, / Jianguo Ma, / Yizheng Ye, et al. | 2005
- 649
-
4.2-C Out of Band Interference Measurement of Negative Feedback AmplifiersTotev, E. D. / Verhoeven, C. J. M. / IEEE et al. | 2005
- 651
-
Design of a switched-current high-speed truly random number generatorZhou Tong, / Yu Ming-yan, / Ye Yi-zheng, et al. | 2005
- 653
-
4.3-C A New Test Data Compression/Decompression Scheme To Reduce SOC Test TimeLong, J. / Feng, J. / Zhu, L. / Xu, W. / Wang, X. / IEEE et al. | 2005
- 656
-
An automatic calibration technique for the OPAMP and its former stage output offsetGuo Shubao, / Zheng Xiaoyan, / Qiu Yulin, et al. | 2005
- 657
-
4.2-I Measurement Techniques for Smart Sensor Interfaces implemented in CMOS technologyMeijer Gerard, C. M. / Xiujun, L. / IEEE et al. | 2005
- 661
-
A novel method for the construction of self-dual circuitsWang Wei, / Jiang Jianhui, et al. | 2005
- 661
-
4.4-C Design and Implementation of DFT Strategy in ASIC Design of Resilient Packet RingZhang, F. / Li, J. / Chen, H. / Jin, D. / Zeng, L. / IEEE et al. | 2005
- 665
-
4.5-C A Low-cost BIST Scheme for ADC TestingWang, Y. / Wang, J. / Lai, F. / Ye, Y. / IEEE et al. | 2005
- 666
-
A current sensing circuit for IDDQ testingTae Sang Kim, / Seung Ho Hong, / Jeong Beom Kim, et al. | 2005
- 669
-
4.6-C A Way of Enhancing Test Quality and Restraining the Increase of Test Cost for Deep Sub-micron Integrated CircuitsDu, J. / Zhao, Y. / Yu, L. / IEEE et al. | 2005
- 670
-
Test modification and compression technique for reducing total test volume with dictionary dataHayashi, T. / Hiraiwa, N. / Shinogi, T. / Takase, H. / Kita, H. et al. | 2005
- 673
-
4.7-P The Implementation Method about Verifying to VLIW DSPDing, X. / He, H. / Zhang, Y. / Sun, Y. / Yu, Y. / IEEE et al. | 2005
- 676
-
Out of band interference measurement of negative feedback amplifiersTotev, E.D. / Verhoeven, C.J.M. et al. | 2005
- 677
-
4.8-P A P1500-Compliant Wrapper and TAM Controller Co-Design SchemeWu, C. / Wang, H. / Yang, S. / IEEE et al. | 2005
- 681
-
4.9-P Study on Detection of Longest Path Delay for Digital CircuitMa, M. / Li, Z. / Jin, G. / IEEE et al. | 2005
- 681
-
Measurement techniques for smart sensor interfaces implemented in CMOS technologyMeijer, G.C.M. / Li Xiujun, et al. | 2005
- 685
-
A new test data compression/decompression scheme to reduce SOC test timeLong Jieyi, / Feng Jianhua, / Zhu Iida, / Xu Wenhua, / Wang Xinan, et al. | 2005
- 685
-
4.10-P A Novel Method for the Construction of Self-Dual CircuitsWang, W. / Jiang, J. / IEEE et al. | 2005
- 689
-
Design and implementation of DFT strategy in ASIC design of resilient packet ringFan Zhang, / Jishi Li, / Hong Chen, / Depeng Jin, / Lieguang Zeng, et al. | 2005
- 689
-
5.1-I FBDD: A Folded Logic Synthesis SystemWu, D. / Zhu, J. / IEEE et al. | 2005
- 694
-
A low-cost BIST scheme for ADC testingWang Yong-sheng, / Wang Jin-xiang, / Lai Feng-chang, / Ye Yi-zheng, et al. | 2005
- 695
-
5.1-C FPGA Design on Saturation Correction in Radar Digital IF ReceiverYao, Z. / Zhang, F. / IEEE et al. | 2005
- 699
-
5.2-C FPGA Implementation of Image Rotation Using Modified Compensated CORDICJiang, X. / Zhou, J. / Shi, J. / Chen, H. / IEEE et al. | 2005
- 699
-
A way of enhancing test quality and restraining the increase of test cost for deep sub-micron integrated circuitsJun Du, / Yuanfu Zhao, / Lixin Yu, et al. | 2005
- 703
-
5.3-C An optimized Adder ACcumulator for high speed MACsZicari, P. / Perri, S. / Corsonello, P. / Cocorullo, G. / IEEE et al. | 2005
- 704
-
The implementation method about verifying to VLIW DSPXie Ding, / Hu He, / Yanjun Zhang, / Yihe Sun, / Yongkang Yu, et al. | 2005
- 707
-
5.4-C Design and FPGA Implementation of OLT for EPONZou, J. / Lin, R. / Liu, M. / IEEE et al. | 2005
- 709
-
A P1500-compliant wrapper and TAM controller co-design schemeWu Chao, / Wang Hong, / Yang Shiyuan, et al. | 2005
- 711
-
5.5-C Design and Implementation of Reconfigurable AES IP Core using FPGAsXu, J. / Liu, Y.-f. / Dai, Z.-b. / Sun, Y. / IEEE et al. | 2005
- 714
-
5.6-C FPGA Implementation of Alterable Parameters RSA Public-Key Cryptographic CoprocessorWen, N. / Dai, Z. b. / Zhang, Y. / IEEE et al. | 2005
- 714
-
Study on analyzing and modeling of delay activity for digital circuitMinjie Ma, / Zheying Li, / Guangyu Jin, et al. | 2005
- 718
-
5.7-C Application of DRFM in High Frequency Ground Wave RadarCheng, Q. / Shi, Z. / Dong, P. / He, B. / IEEE et al. | 2005
- 719
-
FPLACEMENT: new placement software for FPGA with bus resourcesHong Shengyan, / Tang Pushan, / Tong Jiarong, et al. | 2005
- 722
-
5.8-C Pre-processing Speech Signals in FPGAsXu, J. / Ariyaeeinia, A. / Sotudeh, R. / Ahmad, Z. / IEEE et al. | 2005
- 723
-
VLSI dynamically reconfigurable hardware for finite state machine design and analysesTraore, D. / Mao Zhi Gang, et al. | 2005
- 726
-
5.9-P Design of a 16-bit real time stack processor in FPGADu, Y. Y. / IEEE et al. | 2005
- 730
-
5.10-P FPLACEMENT: New Placement Software for FPGA with Bus ResourcesHong, S. / Tang, P. / Tong, J. / IEEE et al. | 2005
- 733
-
Research on generating the constants T[i] of MD5 algorithm based on FPGAsLiu Yuan-feng, / Dai Zi-bin, / Xu Jian, et al. | 2005
- 734
-
5.11-P VLSI Dynamically Reconfigurable Hardware for Finite State Machine Design and AnalyseTraore, D. / Mao, Z. G. / IEEE et al. | 2005
- 737
-
Hardware design of real-time offline Jawi character recognition chip using discrete wavelet transform| 2005
- 739
-
5.12-P Application of FPGA In High Frequency Ground Wave Radar's responderShi, Z. / Dong, P. / Cheng, Q. / IEEE et al. | 2005
- 741
-
FPGA design on saturation correction in radar digital IF receiverZhendong Yao, / Fugui Zhang, et al. | 2005
- 743
-
5.13-P Research on generating the constants T[i] of MD5 algorithm based on FPGAsLiu, Y.-f. / Dai, Z. / Xu, J. / IEEE et al. | 2005
- 746
-
5.14-P Hardware Design of Real-time OffLine Jawi Character Recognition Chip using Discrete Wavelet TransformZaidi, r. / mashkuri, y. / Rosli, S. / IEEE et al. | 2005
- 746
-
FBDD: a folded logic synthesis systemWu, D. / Jianwen Zhu, et al. | 2005
- 750
-
6.1-I Design with Fluctuations of Device Characteristics-TCAD can be of any help?Nishi, K. / IEEE et al. | 2005
- 752
-
FPGA implementation of image rotation using modified compensated CORDICXiao-Gang Jiang, / Jian-Yang Zhou, / Jiang-Hong Shi, / Hui-Huang Chen, et al. | 2005
- 756
-
6.1-C Deterministic Skip Lists in Analog Topological PlacementMaruvada, S. C. / Berkman, A. / Krishnamoorthy, K. / Balasa, F. / IEEE et al. | 2005
- 757
-
An optimized adder accumulator for high speed MACsZicari, P. / Perri, S. / Corsonello, P. / Cocorullo, G. et al. | 2005
- 760
-
6.2-C A Fast and Stable Force-Directed Placment with Implicit Buffer PlanningLuo, L. / Zhou, Q. / Cai, Y. / Hong, X. / Wang, Y. / Yang, H. H. / IEEE et al. | 2005
- 761
-
Design and FPGA implementation of OLT for EPONJunni Zou, / Rujian Lin, / Minglai Liu, et al. | 2005
- 764
-
6.3-C An Efficient Algorithm for Hexagon/Triangle Placement by ExtendingWei, Y. / Dong, S. / Hong, X. / IEEE et al. | 2005
- 765
-
Design and implementation of reconfigurable AES IP core using FPGAsXu Jian, / Liu Yuan-feng, / Dai Zi-bin, / Sun Yi, et al. | 2005
- 768
-
6.4-C Congestion and Performance Driven Full-chip Scalable Routing FrameworkYao, H. / Cai, Y. / Hong, X. / Zhou, Q. / IEEE et al. | 2005
- 769
-
FPGA implementation of alterable parameters RSA public-key cryptographic coprocessorWen Nuan, / Dai Zi Bin, / ZhangYong Fu, et al. | 2005
- 772
-
6.5-C Interconnect Delay Optimization Using a Novel Hibrid Insertion StrategyLiu, X. / Chen, S. / IEEE et al. | 2005
- 774
-
Application of DRFM in high frequency ground wave radarCheng Quan, / Shi Zhenhua, / Dong Peng, / He Bolin, et al. | 2005
- 776
-
6.6-C Power/Ground Network Aware and Row-Based Solutions to Crosstalk Driven Routing ProblemLiang, J. / Jing, T. / Hong, X. / Xiong, J. / He, L. / IEEE et al. | 2005
- 778
-
Pre-processing speech signals in FPGAsJun Xu, / Ariyaeeinia, A. / Sotudeh, R. / Zaki Ahmad, et al. | 2005
- 780
-
6.7-C A Fast Placement Approach for Large Scale Modules Based on Less Flexibility First PrinciplesWei, S. / Dong, S. / Hong, X. / Wu, Y. / IEEE et al. | 2005
- 783
-
Design of a 16-bit real time stack processor in FPGADu Yuyuan, et al. | 2005
- 784
-
6.8-C An ECO Algorithm for Resolving OPC and Crosstalk ViolationsXiang, H. / Huang, L. / Chao, K.-Y. / Wong, M. D. F. / IEEE et al. | 2005
- 787
-
3D placement algorithm considering vertical channels and guided by 2D placement solutionGuilin Liu, / Zhuoyuan Li, / Qiang Zhou, / Xianlong Hong, / Hannah Honghua Yang, et al. | 2005
- 788
-
6.9-C A New FPGA Packing Algorithm Based on the Modeling Method for Logic BlockNi, G. / Tong, J. / Lai, J. / IEEE et al. | 2005
- 792
-
6.10-C 3D placement algorithm considering vertical channels and guided by 2D placement solutionLiu, G. / Li, Z. / Zhou, Q. / Hong, X. / Yang, H. H. / IEEE et al. | 2005
- 792
-
Design tools for 3D mixed mode placementZhuoyuan Li, / Haixia Yan, / Xianlong Hong, / Qiang Zhou, / Jinian Bian, / Yang, H.H. / Pitchumani, V. et al. | 2005
- 796
-
6.11-C Design Tools for 3D Mixed Mode PlacementLi, Z. / Yan, H. / Hong, X. / Zhou, Q. / Bian, J. / Yang, H. H. / Pitchumani, V. / IEEE et al. | 2005
- 797
-
Area optimization in deep sub-micron VLSI designWang Dong-Hui, / Yu Qian, / Liu Yan, et al. | 2005
- 800
-
6.12-C Area optimization in deep sub-micro VLSI designWang, D. / Yu, Q. / Liu, Y. / IEEE et al. | 2005
- 802
-
New metal fill considerations for nanometer technologiesXiaopeng Dong, / Inhwan Seo, / Kao, W. et al. | 2005
- 804
-
6.13-C New Metal Fill Considerations for Nanometer TechnologiesDong, X. / Seo, I. / Kao, W. / IEEE et al. | 2005
- 806
-
FPGA placement using genetic algorithm with simulated annealingYang, M. / Almaini, A.E.A. / Wang, L. / Pengjun Wang, et al. | 2005
- 808
-
6.14-C FPGA Placement Using Genetic Algorithm with Simulated AnnealingMeng, Y. / Almaini, A. E. A. / Wang, L. / Wang, P. / IEEE et al. | 2005
- 811
-
A universal hierarchical FPGA partitioning algorithmYuanfeng Chen, / Pushan Tang, / Jinmei Lai, / Jiarong Tong, et al. | 2005
- 812
-
6.15-P An Universal Hierarchical FPGA Partitioning AlgorithmChen, Y. / Tang, P. / Lai, J. / Tong, J. / IEEE et al. | 2005
- 815
-
A research on optimum-searching quadratic optimization for very large-scale standard cell placementYongqiang Lu, / Xianlong Hong, / Qiang Zhou, / Yici Cai, / Zhuoyuan Li, et al. | 2005
- 816
-
6.16-P A Research on Optimum-Searching Quadratic Optimization for Very Large-Scale Standard Cell PlacementLu, Y. / Hong, X. / Zhou, Q. / Cai, Y. / Li, Z. / IEEE et al. | 2005
- 820
-
6.17-P A Datapath Routing Algorithm Using Bit Regularity ExtractionZhang, W. / Zhou, Q. / Cai, Y. / Hong, X. / IEEE et al. | 2005
- 820
-
A datapath routing algorithm using bit regularity extractionWei Zhang, / Qiang Zhou, / Yici Cai, / Xianlong Hong, et al. | 2005
- 824
-
6.18-P Analog Constraints Extraction based on the Signal Flow AnalysisZhou, Z. / Dong, S. / Hong, X. / Hao, Q. / Chen, S. / IEEE et al. | 2005
- 825
-
Analog constraints extraction based on the signal flow analysisZhe Zhou, / Sheqin Dong, / Xianlong Hong, / Qingsheng Hao, / Song Chen, et al. | 2005
- 828
-
6.19-P Hexagon/Triangle Packing Using Improved Least Flexibility First Principle AlgorithmLiu, T. / Wu, W. M. / Wu, Y. / Bian, J. / IEEE et al. | 2005
- 830
-
Hexagon/triangle packing using improved least flexibility first principle algorithmTao Liu, / Wei-Ming Wu, / Yu-Liang Wu, / Ji-Nian Bian, et al. | 2005
- 832
-
6.20-P VLSI Floorplan Based on Less Flexibility First Principle and Linear ProgrammingYuan, J. / Dong, S. / Hong, X. / Wu, Y. / IEEE et al. | 2005
- 832
-
VLSI Floorplan Based on Less Flexibility First Principle and Linear ProgrammingJun Yuan, / Sheqin Dong, / Xianlong Hong, / Yuliang Wu, et al. | 2005
- 834
-
Deterministic skip lists in analog topological placementMaruvada, S.C. / Berkman, A. / Krishnamoorthy, K. / Balasa, F. et al. | 2005
- 836
-
6.21-P A Shortest-Path-Search Algorithm with Symmetric Constraints for Analog Circuit RoutingDu, C. / Cai, Y. / Hong, X. / Zhou, Q. / IEEE et al. | 2005
- 838
-
Design with fluctuations of device characteristics - TCAD can be of any help?Nishi, K. et al. | 2005
- 840
-
7.1-I Hardware-Software Cosynthesis of Multitask MPSoCs with Real-Time ConstraintsLee, C. / Ha, S. / IEEE et al. | 2005
- 844
-
A shortest-path-search algorithm with symmetric constraints for analog circuit routingChangxu Du, / Yici Cai, / Xianlong Hong, / Qiang Zhou, et al. | 2005
- 846
-
7.1-C A Technique to Exploit Memory Locality for Fast Instruction Set SimulationQin, W. / Hu, B. / IEEE et al. | 2005
- 848
-
A fast and stable force-directed placement with implicit buffer planningLijuan Luo, / Qiang Zhou, / Yici Cai, / Xianlong Hong, / Yibo Wang, / Yang, H.H. et al. | 2005
- 850
-
7.2-C Transition Traversal Coverage Estimation for Symbolic Model CheckingXu, X. / Kimura, S. / Horikawa, K. / Tsuchiya, T. / IEEE et al. | 2005
- 852
-
An efficient algorithm for hexagon/triangle placement by extending the application of the sequence pair representationYaoguang Wei, / Sheqin Dong, / Xianlong Hong, et al. | 2005
- 854
-
7.3-C Automatic Instruction Generation for Application Specific Co-processorSang, S. / Li, X. / Ye, Y. / IEEE et al. | 2005
- 856
-
Congestion and performance driven full-chip scalable routing frameworkHailong Yao, / Yici Cai, / Xianlong Hong, / Qiang Zhou, et al. | 2005
- 858
-
7.4-C Virtual Embedded Operating System for Hardware/Software Co-designXiong, z. / Zhang, M. / Li, S. / Liu, S. / Chao, Y. / IEEE et al. | 2005
- 860
-
Interconnect delay optimization using a novel hybrid insertion strategyXiangyuan Liu, / Shuming Chen, et al. | 2005
- 862
-
7.5-C FSM Decomposition for Power Gating Design Automation in Sequential CircuitsLiu, B. / Cai, Y. / Zhou, Q. / Bian, j. / Hong, X. / IEEE et al. | 2005
- 864
-
Power/ground network aware and row-based solutions to the crosstalk driven routing problemJinghong Liang, / Tong Jing, / Xianlong Hong, / Jinjun Xiong, / Lei He, et al. | 2005
- 866
-
7.2-I Industrial Scale Formal Verification Using Concurrent GSTEYang, J. / Ghughal, R. / Tiemeyer, A. / IEEE et al. | 2005
- 868
-
A fast placement approach for large scale modules based on less flexibility first principlesShaojun Wei, / Sheqin Dong, / Xianlong Hong, / Youliang Wu, et al. | 2005
- 870
-
7.6-C BDD Minimization Based on Genetic Tabu Hybrid StrategyWang, M. / Yu, H. / IEEE et al. | 2005
- 873
-
An ECO algorithm for resolving OPC and coupling capacitance violationsHua Xiang, / Li-Da Huang, / Kai-Yuan Chao, / Wong, M.D.F. et al. | 2005
- 874
-
7.7-C Mapping of IP Cores to Network-on-Chip Architectures Based on Traffic LoadsChia-Ming / Chi, H.-C. / Lee, M.-C. / IEEE et al. | 2005
- 877
-
A new FPGA packing algorithm based on the modeling method for logic blockGang Ni, / Jiarong Tong, / Jinmei Lai, et al. | 2005
- 878
-
7.8-C Domain Coverage Metric for ValidationLuo, C. / Gao, G. / Yang, J. / IEEE et al. | 2005
- 881
-
Implementation of a flexible development platform for simultaneous support of software and hardware development flowKi-Yong Ahn, / Seonpil Kim, / Jae-Moon Kim, / Chong-Min Kyung, et al. | 2005
- 882
-
7.9-C Feedback Driven High Level Synthesis for Performance OptimizationLi, H. / Katkoori, S. / Liu, Z. / IEEE et al. | 2005
- 886
-
RTL property checking technology based on ATPG and ILPShaohe Wu, / Minchuan Chen, / Weimin Wu, / Jinian Bian, et al. | 2005
- 886
-
7.10-C Implementation of a Flexible Development Platform for Simultaneous Support of Software and Hardware Development FlowAhn, K.-Y. / Kim, S. / Kim, J.-M. / Kyung, C.-M. / IEEE et al. | 2005
- 890
-
7.11-P RTL Property Checking Technology Based on ATPG and ILPWu, S. / Chen, M. / Wu, W. / Bian, J. / IEEE et al. | 2005
- 891
-
Verification of a configurable processor core for system-on-a-chip designsHaihua Shen, / Heng Zhang, / Tong Xu, et al. | 2005
- 894
-
7.12-P Verification of a Configurable Processor Core for System-on-a-Chip DesignsShen, H. / Zhang, H. / Xu, T. / IEEE et al. | 2005
- 895
-
Extraction of feedback information from circuit netlistsRuijing Shen, / Xiangqing He, / Liu Yang, et al. | 2005
- 898
-
7.13-P Extraction of Feedback Information from Circuit NetlistsShen, R. / He, X. / Yang, L. / IEEE et al. | 2005
- 900
-
A fast algorithm for power optimization using multiple voltages in data path synthesisJianfeng Huang, / Jinian Bian, / Zhipeng Liu, / Yunfeng Wang, et al. | 2005
- 902
-
7.14-P A Fast Algorithm for Power Optimization Using Multiple Voltages in Data Path SynthesisHuang, J. / Bian, J. / Liu, Z. / Wang, Y. / IEEE et al. | 2005
- 905
-
Datapath verification with SystemC reference modelDongjun Lou, / Jingkun Yuan, / Daguang Li, / Jacobs, C. et al. | 2005
- 906
-
7.15-P Datapath Verification With SystemC Reference ModelLou, D. / Yuan, J. / Li, D. / Jacobs, C. / IEEE et al. | 2005
- 910
-
7.16-P RTL Satisfiability Solving Using an ATPG based ApproachChen, M. / Wu, W. / Bian, J. / IEEE et al. | 2005
- 910
-
RTL satisfiability solving using an ATPG based approachMinchuan Chen, / Weimin Wu, / Jinian Bian, et al. | 2005
- 914
-
8.1-I Frontend Model Generation for SAT-Based Property CheckingWedler, M. / Stoffel, D. / Kunz, W. / IEEE et al. | 2005
- 915
-
A technique to exploit memory locality for fast instruction set simulationWei Qin, / Bo Hu, et al. | 2005
- 919
-
Hardware-software cosynthesis of multitask MPSoCs with real-time constraintsChoonseung Lee, / Soonhoi Ha, et al. | 2005
- 920
-
8.1-C VLSI Interconnect Signal Analysis Using Projection Framework MethodSuzuki, G. / IEEE et al. | 2005
- 925
-
Transition traversal coverage estimation for symbolic model checkingXu, X. / Kimura, S. / Horikawa, K. / Tsuchiya, T. et al. | 2005
- 926
-
8.2-C A SystemC-based NoC Simulation Framework supporting Heterogeneous CommunicatorXu, N. / Leng, X. / Liu, R. / Zhou, Z. / IEEE et al. | 2005
- 930
-
8.3-C A Delay Metric for VLSI InterconnectDu, Z. / Wen, Z. / Yu, L. / IEEE et al. | 2005
- 930
-
Industrial scale formal verification using concurrent GSTEJin Yang, / Ghughal, R. / Tiemeyer, A. et al. | 2005
- 934
-
8.4-C Gate Delay Estimation Based on Close-Ended Line ModelDong, G. / Yang, Y. / Li, Y. / IEEE et al. | 2005
- 934
-
Automatic instruction generation for application specific co-processorShengtian Sang, / Xiaoming Li, / Yizheng Ye, et al. | 2005
- 938
-
8.5-C Compact Model for RF CMOS Differential Transformers Up to 30 GHzJiao, C. / Gao, W. / Yu, Z. / IEEE et al. | 2005
- 939
-
Virtual embedded operating system for hardware/software co-designZhihui Xiong, / Maojun Zhang, / Sikun Li, / Shaohua Liu, / Yafei Chao, et al. | 2005
- 942
-
8.6-C A Novel Method to Simulating Transient Response of InterconnectsShi, X. / Yang, D. / Wang, G. / IEEE et al. | 2005
- 944
-
FSM decomposition for power gating design automation in sequential circuitsBin Liu, / Yici Cai, / Qiang Zhou, / Jinian Bian, / Xianlong Hong, et al. | 2005
- 946
-
8.2-I Applying Formal Techniques in Simulation-based VerificationYunshan, Z. / IEEE et al. | 2005
- 948
-
BDD minimization based on genetic tabu hybrid strategyWang Mingquan, / Yu Haibin, et al. | 2005
- 952
-
8.7-C Energy Oriented Optimization of Dynamic Management Strategy for Scratch-Pad MemoryJin, J. / Pu, H. / Ling, M. / IEEE et al. | 2005
- 953
-
Mapping of IP cores to network-on-chip architectures based on communication task graphsChia-Ming Wu, / Hsin-Chou Chi, / Ming-Chao Lee, et al. | 2005
- 956
-
8.8-C SFG Modeling for Consistency Checking of Mixed-Signal SoCLi, Z. / Li, S. / Ma, M. / Li, L. / IEEE et al. | 2005
- 957
-
Domain coverage metric for validationLuo Chun, / Gao Gugang, / Yang Jun, et al. | 2005
- 960
-
8.9-C Power Property Analysis for CMOS Integrated CircuitsXu, Y. / Xu, C. / Li, X. / IEEE et al. | 2005
- 961
-
Feedback driven high level synthesis for performance optimizationHao Li, / Katkoori, S. / Zhipeng Liu, et al. | 2005
- 962
-
8.10-C A Structural Behavioural Modelling Approach for Top-Level Analogue Mixed-Signal Functional VerificationsWu, P. B. / IEEE et al. | 2005
- 963
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A Structural Behavioural Modelling Approach for Top-Level Analogue Mixed-Signal Functional VerificationsWu, P.B. et al. | 2005
- 967
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8.11-C Experimental Studies on SAT-based Test Pattern Generation for Industrial CircuitsShi, J. / Fey, G. / Drechsler, R. / Glowatz, A. / Schloffel, J. / Hapke, F. / IEEE et al. | 2005
- 970
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Experimental studies on SAT-based test pattern generation for industrial circuitsJunhao Shi, / Fey, G. / Drechsler, R. / Glowatz, A. / Schloffel, J. / Hapke, F. et al. | 2005
- 971
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8.12-P Modeling Lossy Substrates with Direct Boundary Element MethodWang, X. / Zhang, M. / Yu, W. / Wang, Z. / IEEE et al. | 2005
- 973
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Modeling lossy substrates with direct boundary element methodXiren Wang, / Mensheng Zhang, / Wenjian Yu, / Zeyi Wang, et al. | 2005
- 975
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8.13-P Minimum Error Based Affine Arithmetic For Variational Timing AnalysisZou, Y. / Zhang, M. / Cai, Y. / Zhou, Q. / Hong, X. / IEEE et al. | 2005
- 978
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Minimum error based affine arithmetic for variational timing analysisYi Zou, / Mengsheng Zhang, / Yici Cai, / Qiang Zhou, / Xianlong Hong, et al. | 2005
- 979
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8.14-P Modeling of Capacitor Array Mismatch Effect in Embedded CMOS CR SAR ADCLin, Z. / Yang, H. / Zhong, L. / Sun, J. / Xia, S. / IEEE et al. | 2005
- 982
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Modeling of capacitor array mismatch effect in embedded CMOS CR SAR ADCZengjin Lin, / Haigang Yang, / Lungui Zhong, / Jiabin Sun, / Shanhong Xia, et al. | 2005
- 983
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8.15-P Interconnect Delay and Slew Computation with the First Three MomentsSun, J. / Ye, T. / Qiu, S. / IEEE et al. | 2005
- 987
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Interconnect delay and slew computation with the first three momentsJiaxing Sun, / Tianchun Ye, / Shanqin Qiu, et al. | 2005
- 987
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8.16-P Broyden method for the self-consistent solution of Schrodinger and Poisson equationsSun, L. / Yang, W. / Xiang, C. / Yu, Z. / Tian, L. / IEEE et al. | 2005
- 991
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8.17-P Novel ESD Protection Design Methodology and Latchup Prevention for a 0.5-um CMOS ASIC LibraryWang, Y. / Jia, S. / Chen, Z. / Ji, L. / IEEE et al. | 2005
- 991
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Broyden method for the self-consistent solution of Schrodinger and Poisson equationsSun Lin, / Yang Wenwei, / Xiang Cailan, / Yu Zhiping, / Tian Lilin, et al. | 2005
- 995
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Stability Analysis of C- C Converter sing Behavioral Modeling TechniqueLai Xinquan, / Li Gang, / Guo Jianping, / Cao Yu, et al. | 2005
- 995
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8.18-P Stability Analysis of DC-DC Converter Using Behavioral Modeling TechniqueLai, X. / Li, G. / Guo, J. / Cao, Y. / IEEE et al. | 2005
- 995
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Novel ESD protection design methodology and latchup prevention for a 0.5-/spl mu/m CMOS ASIC libraryWang Yuan, / Jia Song, / Chen Zhongjian, / Ji Lijiu, et al. | 2005
- 999
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8.19-P Mixed-signal System Modeling Methodology With VHDL-AMSYang, D. / Shi, X. / Wang, G. / IEEE et al. | 2005
- 1003
-
8.20-P Macromodel of Switched-Capacitor Sigma-Delta ModulatorCheng, J. / Wen, Z. / Wei, T. / IEEE et al. | 2005
- 1005
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Mixed-signal system modeling methodology with VHDL-AMSDong-sheng Yang, / Xin-zhi Shi, / Gao-feng Wang, et al. | 2005
- 1007
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8.21-P I-V Characteristic of BJMOSFET Based on SOIZeng, Y. / Li, X. / Zhang, Y. / Zhang, L. / IEEE et al. | 2005
- 1010
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VLSI interconnect signal analysis using a projection framework methodSuzuki, G. et al. | 2005
- 1011
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9.1-C Two Dimensional Device Simulation and Fabrication of Mesa SOI Vertical Dual Carrier Field Effect Transistor with Effective Channel Length of 30nm for Switching ASIC and SOCHuang, C. / Yang, Y. H. / Xu, Y. Z. / Chao, Y. F. / Yang, R. / Li, G. H. / Tang, Z. M. / Xu, P. / Huang, D. H. / Lin, C. L. et al. | 2005
- 1015
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9.2-C Fast Mode Decision Algorithm In H.264 For Video CommunicationsGao, S. / Lu, T.-j. / IEEE et al. | 2005
- 1017
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Frontend model generation for SAT-based property checkingMarkus Wedler, / Dominik Stoffel, / Wolfgang Kunz, et al. | 2005
- 1019
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9.3-C A Pilot Based EM Channel Estimator for OFDM SystemsYun, C. / Bo, S. / Zhi, L. / IEEE et al. | 2005
- 1023
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9.4-C Impact of Process Variation on Soft Error Vulnerability for Nanometer VLSI CircuitsDing, Q. / Luo, R. / Wang, F. / Xie, Y. / IEEE et al. | 2005
- 1023
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Macromodel of switched-capacitor sigma-delta modulatorCheng Jianping, / Wen Zuoxia, / Wei Tongli, et al. | 2005
- 1027
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I-V characteristic of BJMOSFET based on SOIZeng Yun, / Li Xiaolei, / Zhang Yan, / Zhang Ling, et al. | 2005
- 1027
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9.5-C A Novel Heuristic Approarch for Bounding Maximum and Minimum Leakage PowerZhang, G. / Xu, Y. / Zhao, J. / IEEE et al. | 2005
- 1031
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9.6-C A Mixed Design Flow for FPGA Prototyping of Design with Scan CircuitsLi, L. / Fajar, E. / Kurimoto, K.-i. / Goto, S. / IEEE et al. | 2005
- 1032
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A systemC-based NoC simulation framework supporting heterogeneous communicatorsXu Ningyi, / Leng Xianglun, / Liu Renfei, / Zhou Zucheng, et al. | 2005
- 1035
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9.7-C Hierarchy Watermarking Technique for IP Core ProtectionSun, G. / Gao, Z. / Ni, M. / IEEE et al. | 2005