Variations in timing and leakage power of 45nm library cells due to lithography and stress effects [7275-21] (Englisch)
- Neue Suche nach: Sadra, K.
- Neue Suche nach: Terry, M.
- Neue Suche nach: Rajagopal, A.
- Neue Suche nach: Soper, R.A.
- Neue Suche nach: Kolarik, D.
- Neue Suche nach: Aton, T.
- Neue Suche nach: Hornung, B.
- Neue Suche nach: Khamankar, R.
- Neue Suche nach: Hurat, P.
- Neue Suche nach: Kasthuri, B.
- Neue Suche nach: SPIE (Society)
- Neue Suche nach: Sadra, K.
- Neue Suche nach: Terry, M.
- Neue Suche nach: Rajagopal, A.
- Neue Suche nach: Soper, R.A.
- Neue Suche nach: Kolarik, D.
- Neue Suche nach: Aton, T.
- Neue Suche nach: Hornung, B.
- Neue Suche nach: Khamankar, R.
- Neue Suche nach: Hurat, P.
- Neue Suche nach: Kasthuri, B.
- Neue Suche nach: Singh, Vivek K.
- Neue Suche nach: Rieger, Michael L.
- Neue Suche nach: SPIE (Society)
In:
Design for manufacturability through design-process integration
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7275 0K
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2009
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Print
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Titel:Variations in timing and leakage power of 45nm library cells due to lithography and stress effects [7275-21]
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Beteiligte:Sadra, K. ( Autor:in ) / Terry, M. ( Autor:in ) / Rajagopal, A. ( Autor:in ) / Soper, R.A. ( Autor:in ) / Kolarik, D. ( Autor:in ) / Aton, T. ( Autor:in ) / Hornung, B. ( Autor:in ) / Khamankar, R. ( Autor:in ) / Hurat, P. ( Autor:in ) / Kasthuri, B. ( Autor:in )
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Kongress:3rd, Design for manufacturability through design-process integration ; 2009 ; San Jose, CA
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Erschienen in:PROCEEDINGS - SPIE THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING ; 72755 ; 7275 0K
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Verlag:
- Neue Suche nach: SPIE
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Erscheinungsort:Bellingham, Wash.
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Erscheinungsdatum:01.01.2009
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Format / Umfang:7275 0K
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Anmerkungen:Includes bibliographical references and author index.
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ISBN:
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ISSN:
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Medientyp:Aufsatz (Konferenz)
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Format:Print
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Sprache:Englisch
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Schlagwörter:
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Datenquelle:
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Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 72750A
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Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyondLiebmann, Lars / Pileggi, Larry / Hibbeler, Jason / Rovner, Vyacheslav / Jhaveri, Tejas / Northrop, Greg et al. | 2009
- 72750B
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Illustration of illumination effects on proximity, focus spillover, and design rulesWang, Lynn T. / Yeh, Anthony / Kem, Lilly / Neureuther, Andrew R. et al. | 2009
- 72750C
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2D design rule and layout analysis using novel large-area first-principles-based simulation flow incorporating lithographic and stress effectsPrins, Steven L. / Blatchford, James / Olubuyide, Oluwamuyiwa / Riley, Deborah / Chang, Simon / Hong, Qi-Zhong / Kim, T. S. / Borges, Ricardo / Lin, Li et al. | 2009
- 72750D
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Exploration of complex metal 2D design rules using inverse lithographyChang, Simon / Blatchford, James / Prins, Steve / Jessen, Scott / Dam, Thuc / Xiao, Guangming / Pang, Linyong / Gleason, Bob et al. | 2009
- 72750E
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Compensating non-optical effects using electrically driven optical proximity correctionBanerjee, Shayak / Agarwal, Kanak B. / Culp, James A. / Elakkumanan, Praveen / Liebmann, Lars W. / Orshansky, Michael et al. | 2009
- 72750G
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Impact of lithography variability on analog circuit behaviorProgler, Christopher / Banerjee, Bhaskar / Haniff, M. F. / Mahzabeen, T. et al. | 2009
- 72750H
-
Design specific variation in pattern transfer by via/contact etch process: full-chip analysisSukharev, Valeriy / Markosian, Ara / Kteyan, Armen / Manukyan, Levon / Khachatryan, Nikolay / Choy, Jun-Ho / Lazaryan, Hasmik / Hovsepyan, Henrik / Onoue, Seiji / Kikuchi, Takuo et al. | 2009
- 72750J
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Interval-value based circuit simulation for statistical circuit designTang, Qian Ying / Spanos, Costas J. et al. | 2009
- 72750K
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Variations in timing and leakage power of 45nm library cells due to lithography and stress effectsSadra, Kayvan / Terry, Mark / Rajagopal, Arjun / Soper, Robert A. / Kolarik, Donald / Aton, Tom / Hornung, Brian / Khamankar, Rajesh / Hurat, Philippe / Kasthuri, Bala et al. | 2009
- 72750L
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Parameter-specific electronic measurement and analysis of sources of variation using ring oscillatorsWang, Lynn T.-N. / Pang, Liang-Teck / Neureuther, Andrew R. / Nikolić, Borivoje et al. | 2009
- 72750M
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Manufacturing system based on tolerance deduced from design intentionKyoh, Suigen / Maeda, Shimon / Kobayashi, Sachiko / Inoue, Soichi et al. | 2009
- 72750N
-
Directional 2D functions as models for fast layout pattern transfer verificationTorres, J. Andres / Hofmann, Mark / Otto, Oberdan et al. | 2009
- 72750O
-
Algorithm for determining printability and colouring of a target layout for double patterningGhan, Justin / Sezginer, Apo et al. | 2009
- 72750P
-
Score-based fixing guidance generation with accurate hot-spot detection methodPark, Yong-Hee / Kim, Dong-Hyun / Choi, Jung-Hoe / Hong, Ji-Suk / Park, Chul-Hong / Lee, Sang-Hoon / Yoo, Moon-Hyun / Cho, Jun-Dong et al. | 2009
- 72750Q
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Verification of extraction repeating pattern efficiency from many actual device dataShoji, Masahiro / Inoue, Tadao / Yamabe, Masaki et al. | 2009
- 72750R
-
Design ranking and analysis methodology for standard cells and full chip physical optimizationVaserman, Yosi / Shauly, Eitan et al. | 2009
- 72750S
-
Practical implementation of via and wire optimization at the SoC levelYuan, Chi-Min / Assad, Guy / Jarvis, Bob / Olivares, Marc / Riviere Cazaux, Lionel / Sharma, Puneet / Subramanian, Jayathi / Thompson, Matt / Wu, Kevin et al. | 2009
- 72750T
-
Test structures for 40 nm design rule evaluationHo, Jonathan / Wang, Yan / Lin, Benjamin et al. | 2009
- 72750U
-
Computational requirements for OPCSpence, Chris / Goad, Scott et al. | 2009
- 72750V
-
Hotspot management for spacer patterning technology with die-to-database wafer inspection systemHagio, Yoshinori / Nagahama, Ichirota / Matsuoka, Yasuo / Mukai, Hidefumi / Hashimoto, Koji et al. | 2009
- 72750W
-
Source-mask selection using computational lithography incorporating physical resist modelsKapasi, Sanjay / Robertson, Stewart / Biafore, John / Smith, Mark D. et al. | 2009
- 72750X
-
Application of pixel-based mask optimization technique for high transmission attenuated PSMSakajiri, Kyohei / Trichkov, Alexander / Granik, Yuri / Hendrickx, Eric / Vandenberghe, Geert / Kempsell, Monica / Fenger, Germain / Boehm, Klaus / Scheruebl, Thomas et al. | 2009
- 72750Y
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Transistor layout configuration effect on actual gate LERAyal, Guy / Shauly, Eitan / Rotshtein, Israel / Menadeva, Ovadya / Siany, Amit / Peltinov, Ram / Shacham-Diamand, Yosi et al. | 2009
- 72750Z
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The PIXBAR OPC for contact-hole pattern in sub-70-nm generationChen, KunYuan / Liao, ChunCheng / Chen, ShuHao / Wey, Todd / Cheng, Phoeby / Chou, Pinjan / Schacht, Jochen / Chou, Dyiann / Jayaram, Srividya et al. | 2009
- 72751A
-
Circuit-topology driven OPC for increased performance/yield ratioPierzchala, Edmund / Pikus, Fedor / Torres, J. Andres et al. | 2009
- 72751B
-
Systematic study of the impact of curved active and poly contours on transistor performanceMoroz, Victor / Choi, Munkang / Lin, Xi-Wei et al. | 2009
- 72751C
-
Lithography aware statistical context characterization of 40nm logic cellsRubin, Mark E. / Kobayashi, Naohiro / Yanagihara, Toshiaki et al. | 2009
- 72751E
-
Implementing self-aligned double patterning on non-gridded design layoutsDai, Huixiong / Sweis, Jason / Bencher, Chris / Chen, Yongmei / Shu, Jen / Xu, Xumou / Ngai, Chris / Huckabay, Judy / Weling, Milind et al. | 2009
- 72751F
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High-precision contouring from SEM image in 32-nm lithography and beyondShindo, Hiroyuki / Sugiyama, Akiyuki / Komuro, Hitoshi / Hojo, Yutaka / Matsuoka, Ryoichi / Sturtevant, John L. / Do, Thuy / Kusnadi, Ir / Fenger, Germain / De Bisschop, Peter et al. | 2009
- 72751G
-
Uniformity-aware standard cell design with accurate shape controlZhang, Hongbo / Wong, Martin D. F. / Chao, Kai-Yuan / Deng, Liang / Choi, Soo-Han et al. | 2009
- 72751H
-
Contour-based optical proximity correctionZhou, Brian / Zhu, Liang / Zhang, Yingchun / Gu, Yili / Kang, Xiaohui et al. | 2009
- 72751I
-
Model-based adaptive fragmentationLiu, Daisy / Li, Cheng He / Kang, Xiao Hui et al. | 2009
- 72751J
-
Process variation aware OPC modeling for leading edge technology nodesZhang, Qiaolin / Croffie, Ebo / Fan, Yongfa / Li, Jianliang / Lucas, Kevin / Falch, Brad / Melvin, Lawerence et al. | 2009
- 72751K
-
Large-scale double-patterning compliant layouts for DP engine and design rule developmentCork, Christopher / Lucas, Kevin / Hapli, John / Raffard, Herve / Barnes, Levi et al. | 2009
- 72751L
-
Statistical approach to design DRAM bitcell considering overlay errorsPyo, Yu-Jin / Kim, Dae-Wook / Park, Jai-Kyun / Doh, Ji-Seong / Kang, Hyun-Jae / Hong, Ji-Suk / Park, Chul-Hong / Lee, Sang-Hoon / Yoo, Moon-Hyun et al. | 2009
- 72751M
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Enhanced layout optimization of sub-45nm standard: memory cells and its effectsPaek, Seung Weon / Jang, Dae Hyun / Park, Joo Hyun / Ha, Naya / Kim, Byung-Moo / Won, Hyo Sig / Choi, Kyu-Myung / Lin, Kuang-Kuo / Klaver, Simon / Malik, Shobhit et al. | 2009
- 72751N
-
Integration of mask and silicon metrology in DFMMatsuoka, Ryoichi / Mito, Hiroaki / Sugiyama, Akiyuki / Toyoda, Yasutaka et al. | 2009
- 72751O
-
Implementing a framework to generate a unified OPC database from different EDA vendors for 45nm and beyondAbdelwahed, Shady A. / Al-Iman, Mohamed / Fathy, Rami / Hindawy, Nader / Schacht, Jochen / Shen, Regina / Huang, Chia Wei / Tsai, Pei Ru / Wu, Te Hung / Yang, Chuen Huei et al. | 2009
- 72751P
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Timing-aware metal fill for optimized timing impact and uniformityKatakamsetty, Usha / Hui, Colin / Huang, Li-Da / Weng, Lannie / Wu, Peter et al. | 2009
- 72751Q
-
Process variability band analysis for quantitative optimization of exposure conditionsSturtevant, John L. / Jayaram, Srividya / Hong, Le et al. | 2009
- 72751R
-
Hotspot detection and design recommendation using silicon calibrated CMP modelHui, Colin / Wang, Xian Bin / Huang, Haigou / Katakamsetty, Ushasree / Economikos, Laertis / Fayaz, Mohammed / Greco, Stephen / Hua, Xiang / Jayathi, Subramanian / Yuan, Chi-Min et al. | 2009
- 72751S
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Convergent automated chip level lithography checking and fixing at 45nmPerez, Valerio / Quek, Shyue Fong / Yeo, Sky / Hui, Colin / Lin, Kuang Kuo / Ng, Walter / Cote, Michel / Kasthuri, Bala / Hurat, Philippe / Thompson, Matt A. et al. | 2009
- 72751T
-
Modeling and simulation of transistor performance shift under pattern-dependent RTA processYe, Yun / Liu, Frank / Cao, Yu et al. | 2009
- 727501
-
Front Matter: Volume 7275| 2009
- 727505
-
Hierarchical modeling of spatial variability with a 45nm exampleQian, Kun / Nikolić, Borivoje / Spanos, Costas J. et al. | 2009
- 727506
-
Layout electrical cooptimization for increased tolerance to process variationsRiviere-Cazaux, Lionel / Hurat, Philippe / Kasthuri, Bala / Layton, Larry / Verghese, Nishath et al. | 2009
- 727507
-
Tiny footprint programmable electrical defocus monitorsPoppe, Wojtek / Au, Patrick / Jayasuriya, Darshana / Rubinstein, Juliet / Neureuther, Andrew R. et al. | 2009
- 727509
-
The nebulous hotspot and algorithm variabilityWong, Alfred K. K. / Lam, Edmund Y. et al. | 2009
- 727511
-
Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verificationCain, Jason P. / Capodieci, Luigi et al. | 2009
- 727513
-
Variability aware interconnect timing models for double patterningChin, Eric Y. / Neureuther, Andrew R. et al. | 2009
- 727514
-
Design-overlay interactions in metal double patterningGhaida, Rani S. / Gupta, Puneet et al. | 2009
- 727515
-
Detecting context sensitive hot spots in standard cell librariesWuu, Jen-Yi / Pikus, Fedor G. / Torres, Andres / Marek-Sadowska, Malgorzata et al. | 2009
- 727516
-
Clustering and pattern matching for an automatic hotspot classification and detection systemGhan, Justin / Ma, Ning / Mishra, Sandipan / Spanos, Costas / Poolla, Kameshwar / Rodriguez, Norma / Capodieci, Luigi et al. | 2009
- 727517
-
Developing DRC plus rules through 2D pattern extraction and clustering techniquesDai, Vito / Capodieci, Luigi / Yang, Jie / Rodriguez, Norma et al. | 2009
- 727518
-
Electrical impact of line-edge roughness on sub-45nm node standard cellBan, Yongchan / Sundareswaran, Savithri / Panda, Rajendran / Pan, David Z. et al. | 2009
- 727519
-
Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulationShauly, Eitan / Torres, Andres / Friedrich, Loran / Cohen-Yasour, Moran / Menadeva, Ovadya / Pikus, Fedor et al. | 2009
-
Hierarchical modeling of spatial variability with a 45nm example [7275-04]Qian, K. / Nikolic, B. / Spanos, C.J. / SPIE (Society) et al. | 2009
-
Clustering and pattern matching for an automatic hotspot classification and detection system [7275-50]Ghan, J. / Ma, N. / Mishra, S. / Spanos, C. / Poolla, K. / Rodriguez, N. / Capodieci, L. / SPIE (Society) et al. | 2009
-
Systematic study of the impact of curved active and poly contours on transistor performance [7275-56]Moroz, V. / Choi, M. / Lin, X.-W. / SPIE (Society) et al. | 2009
-
Layout electrical cooptimization for increased tolerance to process variations [7275-37]Riviere-Cazaux, L. / Hurat, P. / Kasthuri, B. / Layton, L. / Verghese, N. / SPIE (Society) et al. | 2009
-
Hotspot management for spacer patterning technology with die-to-database wafer inspection system [7275-33]Hagio, Y. / Nagahama, I. / Matsuoka, Y. / Mukai, H. / Hashimoto, K. / SPIE (Society) et al. | 2009
-
Transistor layout configuration effect on actual gate LER [7275-36]Ayal, G. / Shauly, E. / Rotshtein, I. / Menadeva, O. / Siany, A. / Peltinov, R. / Shacham-Diamand, Y. / SPIE (Society) et al. | 2009
-
The PIXBAR OPC for contact-hole pattern in sub-70-nm generation [7275-38]Chen, K. / Liao, C. / Chen, S. / Wey, T. / Cheng, P. / Chou, P. / Schacht, J. / Chou, D. / Jayaram, S. / SPIE (Society) et al. | 2009
-
Implementing self-aligned double patterning on non-gridded design layouts [7275-59]Dai, H. / Sweis, J. / Bencher, C. / Chen, Y. / Shu, J. / Xu, X. / Ngai, C. / Huckabay, J. / Weling, M. / SPIE (Society) et al. | 2009
-
Illustration of illumination effects on proximity, focus spillover, and design rules [7275-11]Wang, L.T.-N. / Yeh, A. / Kem, L. / Neureuther, A.R. / SPIE (Society) et al. | 2009
-
Impact of lithography variability on analog circuit behavior [7275-17]Progler, C. / Banerjee, B. / Haniff, M.F. / Mahzabeen, T. / SPIE (Society) et al. | 2009
-
Score-based fixing guidance generation with accurate hot-spot detection method [7275-26]Park, Y.-H. / Kim, D.-H. / Choi, J.-H. / Hong, J.-S. / Park, C.-H. / Lee, S.-H. / Yoo, M.-H. / Cho, J.-D. / SPIE (Society) et al. | 2009
-
Design ranking and analysis methodology for standard cells and full chip physical optimization [7275-29]Vaserman, Y. / Shauly, E. / SPIE (Society) et al. | 2009
-
Test structures for 40 nm design rule evaluation [7275-31]Ho, J. / Wang, Y. / Lin, B. / SPIE (Society) et al. | 2009
-
Source-mask selection using computational lithography incorporating physical resist models [7275-34]Kapasi, S. / Robertson, S. / Biafore, J. / Smith, M.D. / SPIE (Society) et al. | 2009
-
Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification [7275-44]Cain, J.P. / Capodieci, L. / SPIE (Society) et al. | 2009
-
Developing DRC plus rules through 2D pattern extraction and clustering techniques [7275-52]Dai, V. / Capodieci, L. / Yang, J. / Rodriguez, N. / SPIE (Society) et al. | 2009
-
Electrical impact of line-edge roughness on sub-45nm node standard cell [7275-53]Ban, Y. / Sundareswaran, S. / Panda, R. / Pan, D.Z. / SPIE (Society) et al. | 2009
-
Model-based adaptive fragmentation [7275-67]Liu, D. / Li, C.H. / Kang, X.H. / SPIE (Society) et al. | 2009
-
Contour-based optical proximity correction [7275-66]Zhou, B. / Zhu, L. / Zhang, Y. / Gu, Y. / Kang, X. / SPIE (Society) et al. | 2009
-
2D design rule and layout analysis using novel large-area first-principles-based simulation flow incorporating lithographic and stress effects [7275-12]Prins, S.L. / Blatchford, J. / Olubuyide, O. / Riley, D. / Chang, S. / Hong, Q.-Z. / Kim, T.S. / Borges, R. / Lin, L. / SPIE (Society) et al. | 2009
-
Variations in timing and leakage power of 45nm library cells due to lithography and stress effects [7275-21]Sadra, K. / Terry, M. / Rajagopal, A. / Soper, R.A. / Kolarik, D. / Aton, T. / Hornung, B. / Khamankar, R. / Hurat, P. / Kasthuri, B. et al. | 2009
-
Parameter-specific electronic measurement and analysis of sources of variation using ring oscillators [7275-22]Wang, L.T.-N. / Pang, L.-T. / Neureuther, A.R. / Nikolic, B. / SPIE (Society) et al. | 2009
-
Verification of extraction repeating pattern efficiency from many actual device data [7275-28]Shoji, M. / Inoue, T. / Yamabe, M. / SPIE (Society) et al. | 2009
-
Practical implementation of via and wire optimization at the SoC level [7275-30]Yuan, C.-M. / Assad, G. / Jarvis, B. / Olivares, M. / Cazaux, L.R. / Sharma, P. / Subramanian, J. / Thompson, M. / Wu, K. / SPIE (Society) et al. | 2009
-
Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation [7275-54]Shauly, E. / Torres, A. / Friedrich, L. / Cohen-Yasour, M. / Menadeva, O. / Pikus, F. / SPIE (Society) et al. | 2009
-
High-precision contouring from SEM image in 32-nm lithography and beyond [7275-60]Shindo, H. / Sugiyama, A. / Komuro, H. / Hojo, Y. / Matsuoka, R. / Sturtevant, J.L. / Do, T. / Kusnadi, I. / Fenger, G. / De Bisschop, P. et al. | 2009
-
Convergent automated chip level lithography checking and fixing at 45nm [7275-77]Perez, V. / Quek, S.F. / Yeo, S. / Hui, C. / Lin, K.K. / Ng, W. / Cote, M. / Kasthuri, B. / Hurat, P. / Thompson, M.A. et al. | 2009
-
Manufacturing system based on tolerance deduced from design intention [7275-23]Kyoh, S. / Maeda, S. / Kobayashi, S. / Inoue, S. / SPIE (Society) et al. | 2009
-
Uniformity-aware standard cell design with accurate shape control [7275-62]Zhang, H. / Wong, M.D.F. / Chao, K.-Y. / Deng, L. / Choi, S.-H. / SPIE (Society) et al. | 2009
-
Interval-value based circuit simulation for statistical circuit design [7275-20]Tang, Q.Y. / Spanos, C.J. / SPIE (Society) et al. | 2009
-
Process variation aware OPC modeling for leading edge technology nodes [7275-68]Zhang, Q. / Croffie, E. / Fan, Y. / Li, J. / Lucas, K. / Falch, B. / Melvin, L. / SPIE (Society) et al. | 2009
-
Enhanced layout optimization of sub-45nm standard: memory cells and its effects [7275-71]Paek, S.W. / Jang, D.H. / Park, J.H. / Ha, N. / Kim, B.-M. / Won, H.S. / Choi, K.-M. / Lin, K.-K. / Klaver, S. / Malik, S. et al. | 2009
-
Integration of mask and silicon metrology in DFM [7275-72]Matsuoka, R. / Mito, H. / Sugiyama, A. / Toyoda, Y. / SPIE (Society) et al. | 2009
-
Exploration of complex metal 2D design rules using inverse lithography [7275-13]Chang, S. / Blatchford, J. / Prins, S. / Jessen, S. / Dam, T. / Xiao, G. / Pang, L. / Gleason, B. / SPIE (Society) et al. | 2009
-
Compensating non-optical effects using electrically driven optical proximity correction [7275-15]Banerjee, S. / Agarwal, K.B. / Culp, J.A. / Elakkumanan, P. / Liebmann, L.W. / Orshansky, M. / SPIE (Society) et al. | 2009
-
Directional 2D functions as models for fast layout pattern transfer verification [7275-24]Torres, J.A. / Hofmann, M. / Otto, O. / SPIE (Society) et al. | 2009
-
Statistical approach to design DRAM bitcell considering overlay errors [7275-70]Pyo, Y.-J. / Kim, D.-W. / Park, J.-K. / Doh, J.-S. / Kang, H.-J. / Hong, J.-S. / Park, C.-H. / Lee, S.-H. / Yoo, M.-H. / SPIE (Society) et al. | 2009
-
Circuit-topology driven OPC for increased performance/yield ratio [7275-55]Pierzchala, E. / Pikus, F. / Torres, J.A. / SPIE (Society) et al. | 2009
-
Timing-aware metal fill for optimized timing impact and uniformity [7275-74]Katakamsetty, U. / Hui, C. / Huang, L.-D. / Weng, L. / Wu, P. / SPIE (Society) et al. | 2009
-
Computational requirements for OPC [7275-32]Spence, C. / Goad, S. / SPIE (Society) et al. | 2009
-
Application of pixel-based mask optimization technique for high transmission attenuated PSM [7275-35]Sakajiri, K. / Trichkov, A. / Granik, Y. / Hendrickx, E. / Vandenberghe, G. / Kempsell, M. / Fenger, G. / Boehm, K. / Scheruebl, T. / SPIE (Society) et al. | 2009
-
Modeling and simulation of transistor performance shiff under pattern-dependent RTA process [7275-78]Ye, Y. / Liu, F. / Cao, Y. / SPIE (Society) et al. | 2009
-
Design specific variation in pattern transfer by via/contact etch process: full-chip analysis [7275-18]Sukharev, V. / Markosian, A. / Kteyan, A. / Manukyan, L. / Khachatryan, N. / Choy, J.-H. / Lazaryan, H. / Hovsepyan, H. / Onoue, S. / Kikuchi, T. et al. | 2009
-
Implementing a framework to generate a unified OPC database from different EDA vendors for 45nm and beyond [7275-73]Abdelwahed, S.A. / Al-Iman, M. / Fathy, R. / Hindawy, N. / Schacht, J. / Shen, R. / Huang, C.W. / Tsai, P.R. / Wu, T.H. / Yang, C.H. et al. | 2009
-
Process variability band analysis for quantitative optimization of exposure conditions [7275-75]Sturtevant, J.L. / Jayaram, S. / Hong, L. / SPIE (Society) et al. | 2009
-
The nebulous hotspot and algorithm variability [7275-09]Wong, A.K.K. / Lam, E.Y. / SPIE (Society) et al. | 2009
-
Algorithm for determining printability and colouring of a target layout for double patterning [7275-27]Ghan, J. / Sezginer, A. / SPIE (Society) et al. | 2009
-
Variability aware interconnect timing models for double patterning [7275-46]Chin, E.Y. / Neureuther, A.R. / SPIE (Society) et al. | 2009
-
Detecting context sensitive hot spots in standard cell libraries [7275-49]Wuu, J.-Y. / Pikus, F.G. / Torres, A. / Marek-Sadowska, M. / SPIE (Society) et al. | 2009
-
Large-scale double-patterning compliant layouts for DP engine and design rule development [7275-69]Cork, C. / Lucas, K. / Hapli, J. / Raffard, H. / Barnes, L. / SPIE (Society) et al. | 2009
-
Hotspot detection and design recommendation using silicon calibrated CMP model [7275-76]Hui, C. / Wang, X.B. / Huang, H. / Katakamsetty, U. / Economikos, L. / Fayaz, M. / Greco, S. / Hua, X. / Jayathi, S. / Yuan, C.-M. et al. | 2009
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Tiny footprint programmable electrical defocus monitors [7275-06]Poppe, W. / Au, P. / Jayasuriya, D. / Rubinstein, J. / Neureuther, A.R. / SPIE (Society) et al. | 2009
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Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond [7275-10]Liebmann, L. / Pileggi, L. / Hibbeler, J. / Rovner, V. / Jhaveri, T. / Northrop, G. / SPIE (Society) et al. | 2009
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Design-overlay interactions in metal double patterning [7275-47]Ghaida, R.S. / Gupta, P. / SPIE (Society) et al. | 2009
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Lithography aware statistical context characterization of 40nm logic cells [7275-57]Rubin, M.E. / Kobayashi, N. / Yanagihara, T. / SPIE (Society) et al. | 2009