Electron spin qubits in quantum dots (Englisch)
- Neue Suche nach: Hanson, R.
- Neue Suche nach: Elzerman, J.M.
- Neue Suche nach: Willems van Beveren, L.H.
- Neue Suche nach: Vandersypen, L.M.K.
- Neue Suche nach: Kouwenhoven, L.P.
- Neue Suche nach: Hanson, R.
- Neue Suche nach: Elzerman, J.M.
- Neue Suche nach: Willems van Beveren, L.H.
- Neue Suche nach: Vandersypen, L.M.K.
- Neue Suche nach: Kouwenhoven, L.P.
In:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
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533-536
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2004
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ISBN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Electron spin qubits in quantum dots
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Beteiligte:Hanson, R. ( Autor:in ) / Elzerman, J.M. ( Autor:in ) / Willems van Beveren, L.H. ( Autor:in ) / Vandersypen, L.M.K. ( Autor:in ) / Kouwenhoven, L.P. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.2004
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Format / Umfang:311142 byte
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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IEEE International Electron Devices Meeting - IEDM - Cover| 2004
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IEEE International Electron Devices Meeting 2004 - IEDM Technical Digest - Title| 2004
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Copyright| 2004
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Welcome from the General ChairWelser, J. et al. | 2004
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The beginnings of the IEDMPritchard, R.L. et al. | 2004
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Award presentations| 2004
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IEDM Executive Committee| 2004
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Subcommittees| 2004
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Session Quick Index| 2004
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Breaker page| 2004
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Table of Contents| 2004
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Author index| 2004
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Notes [blank]| 2004
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IEEE IEDM [Back Cover]| 2004
- 1
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Plenary Session| 2004
- 3
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IEDM - a view as a participant and a customerParillo, L.C. et al. | 2004
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1.1 IEDM - A View as a Participant and a CustomerParrillo, L. C. / IEEE et al. | 2004
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Future semiconductor manufacturing: challenges and opportunitiesIwai, H. et al. | 2004
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1.2 Future Semiconductor Manufacturing-Challenges and OpportunitiesIwai, H. / IEEE et al. | 2004
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Emerging technologies on siliconBrillouet, M. et al. | 2004
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1.3 Emerging Technologies on SiliconBrillouet, M. / IEEE et al. | 2004
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Displays, sensors and MEMS - MEMS technologies and applicationsYoung, D. / De Boeck, J. et al. | 2004
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2.1 High-Speed MEMS-based Gas ChromatographyAgah, M. / Lambertus, G. R. / Sacks, R. D. / Wise, K. D. / IEEE et al. | 2004
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High-speed MEMS-based gas chromatographyAgah, M. / Lambertus, G.R. / Sacks, R.D. / Wise, K.D. et al. | 2004
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A reliable and compact polymer-based package for capacitive RF-MEMS switchesOya, Y. / Okubora, A. / Van Spengen, M. / Soussan, P. / Stoukatch, S. / Rottenberg, X. / Ratchev, P. / Tilmans, H. / De Raedt, W. / Beyne, E. et al. | 2004
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2.2 A Reliable and Compact Polymer-Based Package for Capacitive RF-MEMS SwitchesOya, Y. / Okubora, A. / Van Spengen, M. / Soussan, P. / Stoukatch, S. / Rottenberg, X. / Ratchev, P. / Tilmans, H. / DeRoedt, W. / Beyne, E. et al. | 2004
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Fully integrated CMOS and high voltage compatible RF MEMS technologyLingpeng Guan, / Sin, J.K.O. / Haitao Liu, / Zhibin Xiong, et al. | 2004
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2.3 A Fully Integrated CMOS and High Voltage Compatible RF MEMS TechnologyGuan, L. / Sin, J. K. O. / Liu, H. / Xiong, Z. / IEEE et al. | 2004
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2.4 Post-Fabrication Laser Trimming of Micromechanical FiltersAbdelmoneum, M. A. / Demirci, M. M. / Li, S.-S. / Nguyen, C. T.-C. / IEEE et al. | 2004
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Post-fabrication laser trimming of micromechanical filtersAbdelmoneum, M.A. / Demirci, M.M. / Sheng-Shian Li, / Nguyen, C.T.C. et al. | 2004
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A trench-sidewall single-wafer-MEMS technology and its typical application in high-performance accelerometersXinxin Li, / Baoluo Cheng, / Yuelin Wang, / Lei Gu, / Jian Dong, / Heng Yang, / Zhaohui Song, et al. | 2004
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2.5 A Trench-Sidewall Single-wafer-MEMS Technology and its Typical Application in High-Performance AccelerometersLi, X. / Cheng, B. / Wang, Y. / Gu, L. / Dong, J. / Yang, H. / Song, Z. / IEEE et al. | 2004
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An electrothermally-actuated, dual-mode micromirror for large bi-directional scanningAnkur Jain, / Todd, S. / Huikai Xie, et al. | 2004
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2.6 An Electrothermally-Actuated, Dual-Mode Micromirror for Large Bi-Directional ScanningJain, A. / Todd, S. / Xie, H. / IEEE et al. | 2004
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2.7 Novel Ferroelectrics-Based Micro-Acoustic Devices and Their Ultrasonic ApplicationsZhu, Y.-P. / Ren, T.-L. / Yang, Y. / Wu, X.-M. / Zhang, N.-X. / Liu, L.-T. / Tan, Z.-M. / Wang, H.-N. / Cai, J. / Wang, S.-D. et al. | 2004
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Novel ferroelectrics-based micro-acoustic devices and their ultrasonic applicationsYi-Ping Zhu, / Tian-Ling Ren, / Yi Yang, / Xiao-Ming Wu, / Ning-Xin Zhang, / Li-Tian Liu, / Zhi-Min Tan, / Hai-Ning Wang, / Jian Cai, / Shui-Di Wang, et al. | 2004
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Session 3 - Integrated Circuits and Manufacturing DRAM| 2004
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Highly scalable sub-50nm vertical double gate trench DRAM cellSchloesser, T. / Manger, D. / Weis, R. / Slesazeck, S. / Lau, F. / Tegen, S. / Sesterhenn, M. / Muemmler, M. / Nuetzel, J. / Temmler, D. et al. | 2004
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3.1 Highly Scalable Sub-50nm Vertical Double Gate Trench DRAM CellSchloesser, T. / Manger, D. / Weis, R. / Slesazeck, S. / Lau, F. / Tegen, S. / Sesterhenn, M. / Muemmler, K. / Nuetzel, J. / Temmler, D. et al. | 2004
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Enhanced data retention of damascene-finFET DRAM with local channel implantation and <100> fin surface orientation engineeringChul Lee, / Jae-man Yoon, / Choong-Ho Lee, / Jong Chul Park, / Tae Yong Kim, / Hee Soo Kang, / Suk Kang Sung, / Eun Suk Cho, / Hye Jin Cho, / Young Joon Ahn, et al. | 2004
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3.2 Enhanced Data Retention of Damascene-finFET DRAM with Local Channel Implantation and <100> Fin Surface Orientation EngineeringLee, C. / Yoon, J.-M. / Lee, C.-H. / Park, J. C. / Kim, T. Y. / Kang, H. S. / Sung, S. K. / Cho, E. S. / Cho, H. J. / Ahn, Y. J. et al. | 2004
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Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention timeOkonogi, K. / Ohyu, K. / Toda, A. / Kobayashi, H. et al. | 2004
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3.3 Lattice Strain Design in W/WN/Poly-Si Gate DRAM for Improving Data Retention TimeOkonogi, K. / Ohyu, K. / Toda, A. / Kobayashi, H. / IEEE et al. | 2004
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A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMsKim, D.H. / Kim, J.Y. / Huh, M. / Hwang, Y.S. / Park, J.M. / Han, D.H. / Kim, D.I. / Cho, M.H. / Lee, B.H. / Hwang, H.K. et al. | 2004
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3.4 Mechanically Enhanced Storage Node for Virtually Unlimited Height (MESH) Capacitor Aiming at Sub 70nm DRAMsKim, D. H. / Kim, J. Y. / Huh, M. / Hwang, Y. S. / Park, J. M. / Han, D. H. / Kim, D. I. / Cho, M. H. / Lee, B. H. / Hwang, H. K. et al. | 2004
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A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technologyAmon, J. / Kieslich, A. / Heineck, L. / Schuster, T. / Faul, J. / Luetzen, J. / Fan, C. / Huang, C.C. / Fischer, B. / Enders, G. et al. | 2004
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3.5 A Highly Manufacturable Deep Trench Based DRAM Cell Layout with a Planar Array Device in a 70nm TechnologyAmon, J. / Kieslich, A. / Heineck, L. / Schuster, T. / Faul, J. / Luetzen, J. / Fan, C. / Huang, C.-C. / Fischer, B. / Enders, G. et al. | 2004
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Session 4 - Process Technology Fully-Silicided (FUSI) Gates| 2004
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4.1 Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-k Dielectrics: Enhanced Performance at Reduced Gate LeakageGusev, E. P. / Cabral, C. / Linder, B. P. / Kim, Y. H. / Maitra, K. / Cartier, E. / Nayfeh, H. / Amos, R. / Biery, G. / Bojarczuk, N. et al. | 2004
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Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakageGusev, E.P. / Cabral, C. / Under, B.P. / Kim, Y.H. / Maitra, K. / Carrier, E. / Nayfeh, H. / Amos, R. / Biery, G. / Bojarczuk, N. et al. | 2004
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4.2 Partial Silicides Technology for Tunable Work Function Electrodes on High-k Gate Dielectrics-Fermi Level Pinning Controlled PtSi~x for HFO~x (N) pMOSFETNabatame, T. / Kadoshima, M. / Iwamoto, K. / Mise, N. / Migita, S. / Ohno, M. / Ota, H. / Yasuda, N. / Ogawa, A. / Tominaga, K. et al. | 2004
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Partial silicides technology for tunable work function electrodes on high-k gate dielectrics - Fermi level pinning controlled PtSi/sub x/ for HfO/sub x/ (N) pMOSFETNabatame, T. / Kadoshima, M. / Iwamoto, K. / Mise, N. / Migita, S. / Ohno, M. / Ota, H. / Yasuda, N. / Ogawa, A. / Tominaga, K. et al. | 2004
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Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOSAime, D. / Froment, B. / Cacho, F. / Carron, V. / Descombes, S. / Morand, Y. / Emonet, N. / Wacquant, F. / Farjot, T. / Jullian, S. et al. | 2004
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4.3 Work Function Tuning Through Dopant Scanning and Related Effects Ni Fully Silicided Gate for Sub-45nm Nodes CMOSAime, D. / Froment, B. / Cacho, F. / Carron, V. / Descombes, S. / Morand, Y. / Emonet, N. / Wacquant, F. / Farjot, T. / Jullian, S. et al. | 2004
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Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devicesTakahashi, K. / Manabe, K. / Ikarashi, T. / Ikarashi, N. / Hase, T. / Yoshihara, T. / Watanabe, H. / Tatsumi, T. / Mochizuki, Y. et al. | 2004
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4.4 Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP DevicesTakahashi, K. / Manabe, K. / Ikarashi, T. / Ikarashi, N. / Hase, T. / Yoshihara, T. / Watanabe, H. / Tatsumi, T. / Mochizuki, Y. / IEEE et al. | 2004
- 95
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Proposal of new HfSiON CMOS fabrication process (HAMDAMA) for low standby power deviceAoyama, T. / Maeda, T. / Torii, K. / Yamashita, K. / Kobayashi, Y. / Kamiyama, S. / Miura, T. / Kitajima, H. / Arikado, T. et al. | 2004
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4.5 Proposal of New HfSiON CMOS Fabrication Process (HAMDAMA) for Low Standby Power DeviceAoyama, T. / Maeda, T. / Torii, K. / Yamashita, K. / Kobayashi, Y. / Kamiyama, S. / Miura, T. / Kitajima, H. / Arikado, T. / IEEE et al. | 2004
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4.6 Diffusion-less Junctions and Super Halo Profiles for PMOS Transistors Formed by SPER and FUSI Gate in 45 nm Physical Gate Length DevicesSeveri, S. / Anil, K. G. / Pawlak, J. B. / Duffy, R. / Henson, K. / Lindsay, R. / Lauwers, A. / Veloso, A. / de Marneffe, J.-F. / Ramos, J. et al. | 2004
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Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devicesSeveri, S. / Anil, K.G. / Henson, K. / Lauwers, A. / Veloso, A. / de Marneffe, J.F. / Ramos, J. / Eyben, P. / Vandervost, W. / Jurczak, M. et al. | 2004
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Session 5 - CIVIOS and Interconnect Reliability - NBTI Effect in Conventional and High-K Dielectrics| 2004
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Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogenMahapatra, S. / Bharath Kumar, P. / Dalei, T.R. / Sana, D. / Alam, M.A. et al. | 2004
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5.1 Mechanism of Negative Bias Temperature Instability in CMOS Devices: Degradation, Recovery and Impact of Nitrogen (Invited)Mahapatra, S. / Alam, M. A. / Kumar, P. B. / Dalei, T. R. / Saha, D. / IEEE et al. | 2004
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On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET'sDenais, M. / Parthasarathy, C. / Ribes, G. / Rey-Tauriac, Y. / Revil, N. / Bravaix, A. / Huard, V. / Perrier, F. et al. | 2004
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5.2 "On-the-fly" Characterization of NBTI in Ultra-Thin Gate-Oxide PMOSFETsDenais, M. / Bravaix, A. / Huard, V. / Parthasarathy, C. / Ribes, G. / Perrier, F. / Rey-Tauriac, Y. / Revil, N. / IEEE et al. | 2004
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A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETsKufluoglu, H. / Ashraful Alam, M. et al. | 2004
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5.3 A Geometrical Unification of the Theories of MBTI and HCI Time-Exponents and Its Implications for Ultra-Scaled Planar and Surround Gate MOSFETsKufluoglu, H. / Alam, M. / IEEE et al. | 2004
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Influence of nitrogen in ultra-thin SiON on negative bias temperature instability under AC stressMitani, Y. et al. | 2004
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5.4 Influence of Nitrogen in Ultra-thin SiON on Negative Bias Temperature Instability under AC StressMitani, Y. / IEEE et al. | 2004
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5.5 Negative Bias Temperature Instabilities in HfSiON/TaN-Based pMOSFETsHoussa, M. / Aoulaiche, M. / Van Elshocht, S. / De Gendt, S. / Groeseneken, G. / Heyns, M. / IEEE et al. | 2004
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Negative bias temperature instabilities in HfSiON/TaN-based pMOSFETsHoussa, M. / Aoulaiche, M. / Van Elshocht, S. / De Gendt, S. / Groeseneken, G. / Heyns, M.M. et al. | 2004
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5.6 HCI and BTI Characteristics of ALD HfSiO(N) Gate Dielectrics as the Compositions and the Post Treatment ConditionsKim, J. P. / Kim, Y.-S. / Lim, H. J. / Lee, J. H. / Doh, S. J. / Jung, H.-S. / Han, S.-K. / Kim, M.-J. / Lee, J.-H. / Lee, N.-I. et al. | 2004
- 125
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HCI and BTI characteristics of ALD HfSiO(N) gate dielectrics as the compositions and the post treatment conditionsJong Pyo Kim, / Yun-Seok Kim, / Ha Jin Lim, / Jung Hyoung Lee, / Seok Joo Doh, / Hyung-Suk Jung, / Sung-Kee Han, / Min-Joo Kim, / Jong-Ho Lee, / Nae-In Lee, et al. | 2004
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Physical model of BTI, TDDB and SILC in HfO/sub 2/-based high-k gate dielectricsTorii, K. / Kitajima, H. / Arikado, T. / Shiraishi, K. / Miyazaki, S. / Yamabe, K. / Boero, M. / Chikyow, T. / Yamada, K. et al. | 2004
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5.7 Physical Model of BTI, TDDB and SILC in HfO~2-Based High-k Gate DielectricsTorii, K. / Shiraishi, K. / Miyazaki, S. / Yamabe, K. / Boero, M. / Chikyow, T. / Yamada, K. / Kitajima, H. / Arikado, T. / IEEE et al. | 2004
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Session 6 - Modeling and Simulation Transport in Nanoscale Silicon-Based FETs - I| 2004
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6.1 Simulation Study of Ge n-channel 7.5 nm DGFETs of Arbitrary Crystallographic AlignmentLaux, S. E. / IEEE et al. | 2004
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Simulation study of Ge n-channel 7.5 nm DGFETs of arbitrary crystallographic alignmentLaux, S.E. et al. | 2004
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Bandstructure effects in ballistic nanoscale MOSFETsRahman, A. / Klimeck, G. / Boykin, T.B. / Lundstrom, M. et al. | 2004
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6.2 Bandstructure Effects in Ballistic Nanoscale MOSFETsRahman, A. / Klimeck, G. / Boykin, T. / Lundstrom, M. / IEEE et al. | 2004
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6.3 Relevance of Remote Scattering in Gate to Channel Mobility of Thin-Oxide CMOS DevicesSolomon, P. M. / Yang, M. / IEEE et al. | 2004
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Relevance of remote scattering in gate to channel mobility of thin-oxide CMOS devicesSolomon, P.M. / Min Yang, et al. | 2004
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6.4 Quantum Mechanical Calculation of Hole Mobility in Silicon Inversion Layers Under Arbitrary StressWang, E. / Matagne, P. / Shifren, L. / Obradovic, B. / Kotlyar, R. / Cea, S. / He, J. / Ma, Z. / Nagisetty, R. / Tyagi, S. et al. | 2004
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Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stressWang, E. / Matagne, P. / Shifren, L. / Obradovic, B. / Kotlyar, R. / Cea, S. / He, J. / Ma, Z. / Nagisetty, R. / Tyagi, S. et al. | 2004
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6.5 Impact of Surface Roughness on Silicon and Germanium Ultra-Thin-Body MOSFETsLow, T. / Li, M. F. / Fan, W. J. / Ng, S. T. / Yeo, Y.-C. / Zhu, C. / Chin, A. / Chan, L. / Kwong, D. L. / IEEE et al. | 2004
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Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETsLow, T. / Li, M.F. / Fan, W.J. / Ng, S.T. / Yeo, Y.-C. / Zhu, C. / Chin, A. / Chan, L. / Kwong, D.L. et al. | 2004
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Session 7 - CMOS Devices - Strained Silicon I| 2004
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7.1 Selectively Formed High Mobility Strained Ge PMOSFETs for High Performance CMOSShang, H. / Chu, J. / Bedell, S. / Gusev, E. P. / Jamison, P. / Zhang, Y. / Ott, J. / Copel, M. / Sadana, D. / Guarini, K. et al. | 2004
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Selectively formed high mobility strained Ge PMOSFETs for high performance CMOSHuiling Shang, / Chu, J.O. / Bedell, S. / Gusev, E.P. / Jamison, P. / Ying Zhang, / Ott, J.A. / Copel, M. / Sadana, D. / Guarini, K.W. et al. | 2004
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7.2 Low Power Device Technology with SiGe Channel, HfSiON, and Poly-Si GateWang, H. C.-H. / Chen, S.-J. / Wang, M.-F. / Tsai, P.-Y. / Tsai, C.-W. / Wang, T.-W. / Ting, S. M. / Hou, T.-H. / Lim, P.-S. / Lin, H.-J. et al. | 2004
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Low power device technology with SiGe channel, HfSiON, and poly-Si gateWang, H.C.-H. / Shang-Jr Chen, / Ming-Fang Wang, / Pang-Yen Tsai, / Ching-Wei Tsai, / Ta-Wei Wang, / Ting, S.M. / Tuo-Hung Hou, / Peng-Soon Lim, / Huan-Just Lin, et al. | 2004
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7.3 Performance Comparison and Channel Length Scaling of Strained Si FETs on SiGe-on-Insulator (SGOI)Cai, J. / Rim, K. / Bryant, A. / Jenkins, K. / Ouyang, C. / Singh, D. / Ren, Z. / Lee, K. / Yin, H. / Hergenrother, J. et al. | 2004
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Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)Cai, J. / Rim, K. / Bryant, A. / Jenkins, K. / Ouyang, C. / Singh, D. / Ren, Z. / Lee, K. / Yin, H. / Hergenrother, J. et al. | 2004
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Impact of parasitic resistance and silicon layer thickness scaling for strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrateKawasaki, H. / Ohuchi, K. / Oishi, A. / Fujii, O. / Tsujii, H. / Ishida, T. / Kasai, K. / Okayama, Y. / Kojima, K. / Adachi, K. et al. | 2004
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7.4 Impact of Parasitic Resistance and Silicon Layer Thickness Scaling for Strained-Silicon MOSFETs on Relaxed Si~1~-~xGe~x Virtual SubstrateKawasaki, H. / Ohuchi, K. / Oishi, A. / Fujii, O. / Tsujii, H. / Ishida, T. / Kasai, K. / Okayama, Y. / Kojima, K. / Adachi, K. et al. | 2004
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High electron and hole mobility enhancements in thin-body strained Si/strained SiGe/strained Si heterostructures on insulatorAberg, I. / Ni Chleirigh, C. / Olubuyide, O.O. / Duan, X. / Hoyt, J.L. et al. | 2004
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7.5 High Electron and Hole Mobility Enhancements in Thin-Body Strained Si/Strained SiGe/Strained Si Heterostructures on InsulatorAberg, I. / Chleirigh, C. N. / Olubuyide, O. / Duan, X. / Hoyt, J. / IEEE et al. | 2004
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7.6 Performance Enhancement of Partially- and Fully-Depleted Strained-SOI MOSFETs and Characterization of Strained-Si Device ParametersNumata, T. / Irisawa, T. / Tezuka, T. / Koga, J. / Hirashita, N. / Usuda, K. / Toyoda, E. / Miyamura, Y. / Tanabe, A. / Sugiyama, N. et al. | 2004
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Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parametersNumata, T. / Irisawa, T. / Tezuka, T. / Koga, J. / Hirashita, N. / Usuda, K. / Toyoda, E. / Miyamura, Y. / Sugiyama, N. / Shin-ichi Takagi, et al. | 2004
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7.7 3D GOI CMOSFETs with Novel IrO~2(Hf) Dual Gates and High-k Dielectric on 1P6M-0.18mum-CMOSYu, D. S. / Chin, A. / Laio, C. C. / Lee, C. F. / Cheng, C. F. / Chen, W. J. / Zhu, C. / Li, M.-F. / Yoo, W. J. / McAlister, S. P. et al. | 2004
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3D GOI CMOSFETs with novel IrO/sub 2/(Hf) dual gates and high-k dielectric on 1P6M-0.18 /spl mu/m-CMOSYu, D.S. / Chin, A. / Laio, C.C. / Lee, C.F. / Cheng, C.F. / Chen, W.J. / Zhu, C. / Li, M.-F. / Yoo, W.J. / McAlister, S.P. et al. | 2004
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Session 8 - Solid State Devices - Room Temperature Single Electronics and Tunneling Devices| 2004
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Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matchingSaitoh, M. / Harata, H. / Hiramoto, T. et al. | 2004
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8.1 Room-Temperature Demonstration of Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern MatchingSaitoh, M. / Harata, H. / Hiramoto, T. / IEEE et al. | 2004
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8.2 Transistor in a Test Tube - Harnessing Molecular Biology to the Self-Assembly of Molecular Scale Electronics (Invited)Sivan, U. / Keren, K. / Braun, E. / Berman, R. / Buchstab, E. / IEEE et al. | 2004
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2004Transistor in a test tube - harnessing molecular biology to the self-assembly of molecular scale electronicsSivan, U. / Keren, K. / Braun, E. / Berman, R. / Buchstab, E. et al. | 2004
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The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processesNirschl, Th. / Wang, P.-F. / Weber, C. / Sedlmeir, J. / Heinrich, R. / Kakoschke, R. / Schrufer, K. / Holz, J. / Pacha, C. / Schulz, T. et al. | 2004
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8.3 The Tunneling Field Effect Transistor (TFET) as an Add-on for Ultra-Low-Voltage Analog and Digital ProcessesNirschl, T. / Wang, P.-F. / Weber, C. / Sedlmeir, J. / Heinrich, R. / Kakoschke, R. / Schrufer, K. / Holz, J. / Pacha, C. / Schulz, T. et al. | 2004
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Room-temperature single-electron transfer and detection with silicon nanodevicesNishiguchi, K. / Fujiwara, A. / Ono, Y. / Inokawa, H. / Takahashi, Y. et al. | 2004
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8.4 Room-Temperature Single-Electron Transfer and Detection with Silicon NanodevicesNishiguchi, K. / Fujiwara, A. / Ono, Y. / Inokawa, H. / Takahashi, Y. / IEEE et al. | 2004
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8.5 80nm Self-Aligned Complementary I-MOS Using Double Sidewall Spacer and Elevated Drain Structure and Its Applicability to Amplifiers with High LinearityChoi, W. Y. / Song, J. Y. / Choi, B. Y. / Lee, J. D. / Park, Y. J. / Park, B.-G. / IEEE et al. | 2004
- 203
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80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearityWoo Young Choi, / Jae Young Song, / Byung Yong Choi, / Jong Duk Lee, / Young June Park, / Byung-Gook Park, et al. | 2004
- 207
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Session 9 - CMOS Devices - Strained Silicon - II| 2004
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9.1 Technology Booster Using Strain-Enhancing Laminated SIN (SELS) for 65nm Node HP MPUsGoto, K. / Satoh, S. / Ohta, H. / Fukuda, S. / Yamamoto, T. / Mori, T. / Tagawa, Y. / Sakuma, T. / Saiki, T. / Shimamure, Y. et al. | 2004
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Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUsGoto, K. / Satoh, S. / Ohta, H. / Fukuta, S. / Yamamoto, T. / Mori, T. / Tagawa, Y. / Sakuma, T. / Saiki, T. / Shimamune, Y. et al. | 2004
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A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride filmsPidin, S. / Mori, T. / Inoue, K. / Fukuta, S. / Itoh, N. / Mutoh, E. / Ohkoshi, K. / Nakamura, R. / Kobayashi, K. / Kawamura, K. et al. | 2004
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9.2 A Novel Strain Enhanced CMOS Architecture Using Selectively Deposited High Tensile And High Compressive Silicon Nitride FilmsPidin, S. / Mori, T. / Inoue, K. / Fukuta, S. / Itoh, N. / Mutoh, E. / Ohkoshi, K. / Nakamura, R. / Kobayashi, K. / Kawamura, K. et al. | 2004
- 217
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Mobility improvement for 45nm node by combination of optimized stress and channel orientation designKomoda, T. / Oishi, A. / Sanuki, T. / Kasai, K. / Yoshimura, H. / Ohno, K. / Iwai, A. / Saito, M. / Matsuoka, F. / Nagashima, N. et al. | 2004
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9.3 Mobility Improvement for 45nm Node by Combination of Optimized Stress Control and Channel Orientation DesignKomoda, T. / Oishi, A. / Sanuki, T. / Kasai, K. / Yoshimura, H. / Ohno, K. / Iwai, M. / Saito, M. / Matsuoka, F. / Nagashima, N. et al. | 2004
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Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETsThompson, S. / Sun, G. / Wu, K. / Lim, J. / Nishida, T. et al. | 2004
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9.4 Key Differences for Process-Induced Uniaxial vs. Substrate-Induced Biaxial Stressed Si and Ge Channel MOSFETsThompson, S. E. / Sum, G. / Wu, K. / Lim, J. / Nishida, T. / IEEE et al. | 2004
- 225
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9.5 In-Plane Mobility Anisotropy and Universality Under Uni-Axial Strains in n- and p-MOS Inversion Layers on (100), (110), and (111) SiIrie, H. / Kita, K. / Kyuno, K. / Toriumi, A. / IEEE et al. | 2004
- 225
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In-plane mobility anisotropy and universality under uni-axial strains in nand p-MOS inversion layers on (100), [110], and (111) SiIrie, H. / Kita, K. / Kyuno, K. / Toriumi, A. et al. | 2004
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9.6 Experimental Study of Biaxial and Uniaxial Strain Effects on Carrier Mobility in Bulk and Ultrathin-body SOI MOSFETsUchida, K. / Zednik, R. / Lu, C.-H. / Jagannathan, H. / McVittie, J. / McIntyre, P. C. / Nishi, Y. / IEEE et al. | 2004
- 229
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Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETsUchida, K. / Zednik, R. / Ching-Huang Lu, / Jagannathan, H. / McVittie, J. / McIntyre, P.C. / Nishi, Y. et al. | 2004
- 233
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9.7 Package-Strain-Enhanced Device and Circuit PerformanceMaikap, S. / Liao, M. H. / Yuan, F. / Lee, M. H. / Huang, C.-F. / Chang, S. T. / Liu, C. W. / IEEE et al. | 2004
- 233
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Package-strain-enhanced device and circuit performanceMaikap, S. / Liao, M.H. / Yuan, F. / Lee, M.H. / Huang, C.F. / Chang, S.T. / Liu, C.W. et al. | 2004
- 237
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Session 10 - Solid State Devices - SiGe HBTs| 2004
- 239
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Integration of high-performance SiGe:C HBTs with thin-film SOI CMOSRucker, H. / Heinemann, B. / Barth, R. / Bolze, D. / Drews, J. / Fursenko, O. / Grabolla, T. / Haak, U. / Hoppner, W. / Knoll, D. et al. | 2004
- 239
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10.1 Integration of High-Performance SiGe:C HBTs with Thin-Film SOI CMOSRucker, H. / Heinemann, B. / Barth, R. / Bolze, D. / Drews, J. / Fursenko, O. / Grabolla, T. / Haak, U. / Hoppner, W. / Knoll, D. et al. | 2004
- 243
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10.2 Metal Emitter SiGe:C HBTsDonkers, J. J. T. M. / Vanhoucke, T. / Agarwal, P. / Hueting, R. J. E. / Meunier-Beillard, P. / Vijayaraghavan, M. N. / Magnee, P. H. C. / Verheijen, M. A. / de Kort, R. / Slotboom, J. W. et al. | 2004
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Metal emitter SiGe:C HBTsDonkers, J.J.T.M. / Vanhoucke, T. / Agarwal, P. / Hueting, R.J.E. / Meunier-Beillard, P. / Vijayaraghavan, M.N. / Magnee, P.H.C. / Verheijen, M.A. / de Kort, R. / Slotboom, J.W. et al. | 2004
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10.3 SiGe HBT Technology with f~m~a~x/f~T Gate Delay Below 3.3 psKhater, M. / Rieh, J.-S. / Adam, T. / Chinthakindi, A. / Johnson, J. / Krishnasamy, R. / Meghelli, M. / Pagette, F. / Sanderson, D. / Schnabel, C. et al. | 2004
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SiGe HBT technology with f/sub max//f/sub T/=350/300 GHz and gate delay below 3.3 psKhater, M. / Rieh, J.-S. / Adam, T. / Chinthakindi, A. / Johnson, J. / Krishnasamy, R. / Meghelli, M. / Pagette, F. / Sanderson, D. / Schnabel, C. et al. | 2004
- 251
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10.4 A Low-Parasitic Collector Construction for High-Speed SiGe:C HBTsHeinemann, B. / Barth, R. / Bolze, D. / Drews, J. / Formanek, P. / Grabolla, T. / Haak, U. / Hoppner, W. / Knoll, D. / Kopke, K. et al. | 2004
- 251
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A low-parasitic collector construction for high-speed SiGe:C HBTsHeinemann, B. / Barth, R. / Bolze, D. / Drews, J. / Formanek, P. / Grabolla, T. / Haak, U. / Hoppner, W. / Kopke, D.K. / Kuck, B. et al. | 2004
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3.3 ps SiGe bipolar technologyBock, J. / Schafer, H. / Knapp, H. / Aufinger, K. / Wurzer, M. / Boguth, S. / Bottner, T. / Stengl, R. / Perndl, W. / Meister, T.F. et al. | 2004
- 255
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10.5 3.3 ps SiGe Bipolar TechnologyBock, J. / Schafer, H. / Knapp, H. / Aufinger, K. / Wurzer, M. / Boguth, S. / Bottner, T. / Stengl, R. / Perndl, W. / Meister, T. F. et al. | 2004
- 259
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Session 11- Integrated Circuits and Manufacturing - SRAM and SOI-Based Memories| 2004
- 261
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Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyondFried, D.M. / Hergenrother, J.M. / Topol, A.W. / Chang, L. / Sekaric, L. / Sleight, J.W. / McNab, S.J. / Newbury, J. / Steen, S.E. / Gibson, G. et al. | 2004
- 261
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11.1 Aggressively Scaled (0.143mum^2) 6T-SRAM Cell for the 32 nm Node and BeyondFried, D. M. / Hergenrother, J. M. / Topol, A. W. / Chang, L. / Sekaric, L. / Sleight, J. W. / McNab, S. / Newbury, J. / Steen, S. / Gibson, G. et al. | 2004
- 265
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Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAMSoon-Moon Jung, / Hoon Lim, / Wonseok Cho, / Hoosung Cho, / Chadong Yeo, / Yongha Kang, / Daegi Bae, / Jonghoon Na, / Kunho Kwak, / Bonghyun Choi, et al. | 2004
- 265
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11.2 Highly Area Efficient and Cost Effective Double Stacked S^3(Stacked Single-crystal SI) Peripheral CMOS SSTFT and SRAM Cell Technology for 512M Bit Density SRAMJung, S.-M. / Lim, H. / Cho, W. / Cho, H. / Yeo, C. / Kang, Y. / Bae, D. / Na, J. / Kwak, K. / Choi, B. et al. | 2004
- 269
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11.3 A 0.314mum^2 6T-SRAM Cell Build With Tall Triple-Gate Devices for 45nm Node Applications Using 0.75NA 193nm LithographyNackaerts, A. / Ercken, M. / Demunck, S. / Lauwers, A. / Baerts, C. / Bender, H. / Boulaert, W. / Collaert, N. / Degroote, B. / Delvaux, C. et al. | 2004
- 269
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A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithographyNackaerts, A. / Ercken, M. / Demuynck, S. / Lauwers, A. / Baerts, C. / Bender, H. / Boulaert, W. / Collaert, N. / Degroote, B. / Delvaux, C. et al. | 2004
- 273
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11.4 Fully Planar 0.562mum^2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High-Performance SRAMsNemati, F. / Cho, H.-J. / Robins, S. / Gupta, R. / Tarabbia, M. / Yang, K. / Hayes, D. / Gopalakrishnan, V. / IEEE et al. | 2004
- 273
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Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMsNemati, F. / Hyun-Jin Cho, / Robins, S. / Gupta, R. / Tarabbia, M. / Yang, K.J. / Hayes, D. / Gopalakrishnan, V. et al. | 2004
- 275
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11.5 A Capacitor-less DRAM Cell on 75nm Gate Length, 16nm Thin Fully Depleted SOI Device for High Density Embedded MemoriesRanica, R. / Villaret, A. / Fenouillet-Beranger, C. / Malinge, P. / Mazoyer, P. / Masson, P. / Delille, D. / Charbuillet, C. / Candelier, P. / Skotnicki, T. et al. | 2004
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A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memoriesRanica, R. / Villaret, A. / Fenouillet-Beranger, C. / Malinge, P. / Mazoyer, P. / Masson, P. / Delille, D. / Charbuillet, C. / Candelier, P. / Skotnicki, T. et al. | 2004
- 281
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Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibilityShino, T. / Higashi, T. / Kusunoki, N. / Fujita, K. / Ohsawa, T. / Aoki, N. / Tanimoto, H. / Minami, Y. / Yamada, T. / Morikado, M. et al. | 2004
- 281
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11.6 Fully-Depleted FBC (Floating Body Cell) with Enlarged Signal Window and Excellent Logic Process CompatibilityShino, T. / Higashi, T. / Kusunoki, N. / Fujita, K. / Ohsawa, T. / Aoki, N. / Tanimoto, H. / Minami, Y. / Yamada, T. / Morikado, M. et al. | 2004
- 285
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Session 12 - Process Technology - Metal Gate Engineering and Integration| 2004
- 287
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12.1 Challenges for the Integration of Metal Gate Electrodes (Invited)Schaeffer, J. K. / Capasso, C. / Fonseca, L. R. C. / Samavedam, S. / Gilmer, D. C. / Liang, Y. / Kalpat, S. / Adetutu, B. / Tseng, H.-H. / Shiho, Y. et al. | 2004
- 287
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Challenges for the integration of metal gate electrodesSchaeffer, J.K. / Capasso, C. / Fonseca, L.R.C. / Samavedam, S. / Gilmer, D.C. / Liang, Y. / Kalpat, S. / Adetutu, B. / Tseng, H.-H. / Shiho, Y. et al. | 2004
- 291
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Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chipHarrison, S. / Coronel, P. / Cros, A. / Cerutti, R. / Leverd, F. / Beverina, A. / Wacquez, R. / Bustos, J. / Delille, D. / Tavel, B. et al. | 2004
- 291
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12.2 Poly-Gate REplacement Through Contact Hole (PRETCH): A New Method for High-K/Metal Gate and Multi-Oxide Implementation on ChipHarrison, S. / Coronel, P. / Cros, A. / Cerutti, R. / Leverd, F. / Beverina, A. / Wacquez, R. / Bustos, J. / Delille, D. / Tavel, B. et al. | 2004
- 295
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12.3 Evaluation of Fermi Level Pinning in Low, Midgap and High Work Function Metal Gate Electrodes on ALD and MOCVD HfO~2 Under High Temperature ExposureJha, R. / Lee, J. / Chen, B. / Lazar, H. / Gurganus, J. / Biswas, N. / Majhi, P. / Brown, G. / Misra, V. / IEEE et al. | 2004
- 295
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Evaluation of Fermi level pinning in low, midgap and high workfunction metal gate electrodes on ALD and MOCVD HfO/sub 2/ under high temperature exposureJha, R. / Jae Hoon Lee, / Chen, B. / Lazar, H. / Gurganus, J. / Biswas, N. / Majhi, P. / Brown, G. / Misra, V. et al. | 2004
- 299
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12.4 Substituted Aluminum Metal Gate on High-k Dielectric for Low Work-Function and Fermi-Level Pinning FreePark, C. S. / Cho, B. J. / Tang, L. J. / Wong, D.-L. / IEEE et al. | 2004
- 299
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Substituted aluminum metal gate on high-k dielectric for low work-function and Fermi-level pinning freeChang Seo Park, / Byung Jin Cho, / Lei Jun Tang, / Dim-Lee Kwong, et al. | 2004
- 303
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A novel methodology on tuning work function of metal gate using stacking bi-metal layersJeon, I.S. / Lee, J. / Zhao, P. / Sivasubramani, P. / Oh, T. / Kim, H.J. / Cha, D. / Huang, J. / Kim, M.J. / Gnade, B.E. et al. | 2004
- 303
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12.5 A Novel Methodology on Tuning Work Function of Metal Gate Using Stacking Bi-Metal LayersJeon, I. S. / Lee, J. / Zhao, P. / Sivasubramani, P. / Oh, T. / Kim, H. J. / Cha, D. K. / Huang, J. / Kim, M. J. / Gnade, B. E. et al. | 2004
- 307
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Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH/sub 3/ and thin AlN) and TaN/HfO/sub 2/ gate stackWhang, S.J. / Lee, S.J. / Fei Gao, / Nan Wu, / Zhu, C.X. / Ji Sheng Pan, / Lei Jun Tang, / Kwong, D.L. et al. | 2004
- 307
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12.6 Germanium p- & n-MOSFETs Fabricated with Novel Surface Passivation (plasma-PH~3 and thin AIN) and TaN/HfO~2 Gate StackWhang, S. J. / Lee, S. J. / Gao, F. / Wu, N. / Zhu, C. X. / Pan, J. S. / Tang, L. J. / Kwong, D. L. / IEEE et al. | 2004
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Session 13 - Process Technology - Advanced Interconnect Technologies| 2004
- 313
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13.1 Challenges in Cu/Low K Integration (Invited)Liang, M.-S. / IEEE et al. | 2004
- 313
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Challenges in Cu/low-k integrationMong-Song Liang, et al. | 2004
- 317
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Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology nodeHinsinger, O. / Fox, R. / Sabouret, E. / Goldberg, C. / Verove, C. / Besling, W. / Brun, P. / Josse, E. / Monget, C. / Belmont, O. et al. | 2004
- 317
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13.2 Demonstration of an Extendable and Industrial 300mm BEOL Integration for 65nm Technology NodeHinsinger, O. / Fox, R. / Sabouret, E. / Goldberg, C. / Verove, C. / Besling, W. / Brun, P. / Josse, E. / Monget, C. / Belmont, O. et al. | 2004
- 321
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Successful dual damascene integration of extreme low k materials (k < 2.0) using a novel gap fill based integration schemeNitta, S. / Purushothaman, S. / Smith, S. / Krishnan, M. / Canaperi, D. / Dalton, T. / Volksen, W. / Miller, R.D. / Herbst, B. / Hu, C.K. et al. | 2004
- 321
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13.3 Successful Dual Damascene Integration of Extreme Low k Materials (k < 2.0) Using a Novel Gap Fill Based Integration SchemeNitta, S. / Purushothaman, S. / Smith, S. / Krishnan, M. / Canaperi, D. / Dalton, T. / Volksen, W. / Miller, R. D. / Herbst, B. / Hu, C.-K. et al. | 2004
- 325
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Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effectBesling, W.F.A. / Arnal, V. / Guillaumond, J.R. / Guedj, C. / Broekaart, M. / Chapelon, L.L. / Farcy, A. / Arnaud, L. / Torres, J. et al. | 2004
- 325
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13.4 Integration of ALD TaN Barriers in Porous Low-k Interconnect for the 45nm Node and Beyond; Solution to Relax Electron Scattering EffectBesling, W. F. A. / Arnal, V. / Guillaumond, J. F. / Guedj, C. / Broekaart, M. / Chapelon, L. L. / Farcy, A. / Arnaud, L. / Torres, J. / IEEE et al. | 2004
- 329
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13.5 Challenge of Low-k Materials for 130, 90, 65 nm Node Interconnect Technology and Beyond (Invited)Miyajima, H. / Watanabe, K. / Fujita, K. / Ito, S. / Tabuchi, K. / Shimayama, T. / Akiyama, K. / Hachiya, T. / Higashi, K. / Nakamura, N. et al. | 2004
- 329
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Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyondMiyajima, H. / Watanabe, K. / Fujita, K. / Ito, S. / Tabuchi, K. / Shimayama, T. / Akiyama, K. / Hachiya, T. / Higashi, K. / Nakamura, N. et al. | 2004
- 333
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13.6 A Novel Solution for Porous Low-k Dual Damascene Post Etch Stripping/Clean with Supercritical CO2 Technology for 65nm and Beyond ApplicationsWang, C. Y. / Wu, W. J. / Yang, C. M. / Tseng, W. H. / Chen, H. C. / Bao, T. I. / Lo, H. / Wang, J. / Yu, C. H. / Liang, M. S. et al. | 2004
- 333
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A novel solution for porous low-k dual damascene post etch stripping/clean with supercritical CO/sub 2/ technology for 65nm and beyond applicationsWang, C.Y. / Wu, W.J. / Yang, C.M. / Tseng, W.H. / Chen, H.C. / Bao, T.I. / Lo, H. / Wang, J. / Yu, C.H. / Liang, M.S. et al. | 2004
- 337
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13.7 Direct Plating of Cu on ALD TaN for 45nm-Node Cu BEOL MetallizationShih, C. H. / Su, H. W. / Lin, C. J. / Ko, T. / Chen, C. H. / Huang, J. J. / Chou, S. W. / Peng, C. H. / Hsieh, C. H. / Tsai, M. H. et al. | 2004
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Direct plating of Cu on ALD TaN for 45nm node Cu BEOL metallizationShih, C.H. / Su, H.W. / Lin, C.J. / Ko, T. / Chen, C.H. / Huang, J.J. / Chou, S.W. / Peng, C.H. / Hsieh, C.H. / Tsai, M.H. et al. | 2004
- 341
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Session 14 - Quantum Electronics and Compound Semiconductors - The New Spectrum of Optoelectronic Devices| 2004
- 343
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{113} defect-engineered silicon light-emitting diodesPan, G.Z. / Ostroumov, R.P. / Lian, Y.G. / Tu, K.N. / Wang, K.L. et al. | 2004
- 343
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14.1 {113} Defect-Engineered Silicon Light-Emitting DiodesPan, G. Z. / Ostroumov, R. P. / Lian, Y. G. / Tu, K. N. / Wang, K. L. / IEEE et al. | 2004
- 347
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255 nm interconnected micro-pixel deep ultraviolet light emitting diodesAsif Khan, M. / Shuai Wu, / Wenhong Sun, / Chitnis, A. / Adivarahan, V. / Shatalov, M. / Yang, J. et al. | 2004
- 347
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14.2 255 nm Interconnected Micro-Pixel Deep Ultraviolet Light Emitting DiodesKhan, M. A. / Wu, S. / Sun, W.-H. / Chitnis, A. / Adivarahan, V. / Shatalov, M. / Yang, J. / IEEE et al. | 2004
- 351
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High-responsivity, high-speed, and high-saturation-power performances of evanescently coupled photodiodes with partially p-doped photo-absorption layerShi, J.W. / Wu, Y.S. / Huang, F.H. / Chan, Y.J. et al. | 2004
- 351
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14.3 High-Responsivity, High-Speed, and High-Saturation-Power Performances of Evanescently Coupled Photodiodes with Partially p-Doped Photo-Absorption LayerShi, J.-W. / Wu, Y.-S. / Huang, F.-H. / Chan, Y.-J. / IEEE et al. | 2004
- 355
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Novel infrared phototransistors for atmospheric CO/sub 2/ profiling at 2 /spl mu/m wavelengthRefaat, T.F. / Nurul Abedin, M. / Sulima, O.V. / Singh, U.N. / Ismail, S. et al. | 2004
- 355
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14.4 Novel Infrared Phototransistors for Atmospheric CO~2 profiling at 2 mum WavelengthRefaat, T. F. / Abedin, M. N. / Sulima, O. V. / Singh, U. N. / Ismail, S. / IEEE et al. | 2004
- 359
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Photonic crystals: fundamentals and applicationsLopez, C. et al. | 2004
- 359
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14.5 Photonic Crystals: Fundamentals and Applications (Invited)Lopez, C. / IEEE et al. | 2004
- 363
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Session 15 - Displays, Sensors and MEMS - Organic TFT's and Devices on Flexible Substrates| 2004
- 365
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A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodesSomeya, T. / Iba, S. / Kato, Y. / Sekitani, T. / Noguchi, Y. / Murase, Y. / Kawaguchi, H. / Sakurai, T. et al. | 2004
- 365
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15.1 A Large-Area, Flexible, and Lightweight Sheet Image Scanner Integrated with Organic Field-Effect Transistors and Organic PhotodiodesSomeya, T. / Iba, S. / Kato, Y. / Sekitani, T. / Noguchi, Y. / Murase, Y. / Kawaguchi, H. / Sakurai, T. / IEEE et al. | 2004
- 369
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15.2 Low-Voltage Flexible Organic Circuits with Molecular Gate DielectricsKlauk, H. / Halik, M. / Eder, F. / Schmid, G. / Dehm, C. / Zschieschang, U. / Rohde, D. / Brederlow, R. / Briole, S. / Maisch, S. et al. | 2004
- 369
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Low-voltage flexible organic circuits with molecular gate dielectricsKlauk, H. / Halik, M. / Eder, F. / Schmid, G. / Dehm, C. / Rohde, D. / Brederlow, R. / Briole, S. / Maisch, S. / Effenberger, F. et al. | 2004
- 373
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15.3 TES Anthradithiophene Solution-Processed OTFTs with 1 cm^2/V-s MobilityKuo, C.-C. / Payne, M. M. / Anthony, J. E. / Jackson, T. N. / IEEE et al. | 2004
- 373
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TES anthradithiophene solution-processed OTFTs with 1 cm/sup 2//V-s mobilityChung-Chen Kuo, / Payne, M.M. / Anthony, J.E. / Jackson, T.N. et al. | 2004
- 377
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15.4 An Organic Semiconductor Based Process for Photodetecting ApplicationsKymissis, I. / Sodini, C. G. / Akinwande, A. I. / Bulovic, V. / IEEE et al. | 2004
- 377
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An organic semiconductor based process for photodetecting applicationsKymissis, I. / Sodini, C.G. / Akinwande, A.I. / Bulovic, V. et al. | 2004
- 381
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15.5 Process Control of Threshold Voltage in Organic FETsWang, A. / Kymissis, I. / Bulovic, V. / Akinwande, A. I. / IEEE et al. | 2004
- 381
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Process control of threshold voltage in organic FETsWang, A. / Kymissis, I. / Bulovic, V. / Akinwande, A.I. et al. | 2004
- 385
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15.6 OLED Pixel Array on a DomeBhattacharya, R. / Wagner, S. / Tung, Y.-J. / Esler, J. / Hack, M. / IEEE et al. | 2004
- 385
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OLED pixel array on a domeBhattacharya, R. / Wagner, S. / Yeh-Jiun Tung, / Esler, J. / Hack, M. et al. | 2004
- 389
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Session 16 - Modeling and Simulation - Reliability| 2004
- 391
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16.1 Inversion Mobility and Gate Leakage in High-k/Metal Gate MOSFETsKotlyar, R. / Giles, M. D. / Matagne, P. / Obradovic, B. / Shifren, L. / Stettler, M. / Wang, E. / IEEE et al. | 2004
- 391
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Inversion mobility and gate leakage in high-k/metal gate MOSFETsKotlyar, R. / Giles, M.D. / Matagne, P. / Obradovic, B. / Shifren, L. / Stettler, M. / Wang, E. et al. | 2004
- 395
-
16.2 Analysis on Data Retention Time of Nano-Scale DRAM and its Prediction by Indirectly Probing the Tail Cell Leakage CurrentLee, W.-S. / Lee, S.-H. / Lee, C.-S. / Lee, K.-H. / Kim, H.-J. / Kim, J.-Y. / Yang, W. / Park, Y.-K. / Kong, J.-T. / Ryu, B.-I. et al. | 2004
- 395
-
Analysis on data retention time of nano-scale DRAM and its prediction by probing the tail cell leakage currentLee, W.-S. / Lee, S.-H. / Lee, C.-S. / Lee, K.-H. / Kim, H.-J. / Kim, J.-Y. / Yang, W. / Park, Y.-K. / Kong, J.-T. / Ryu, B.-I. et al. | 2004
- 399
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Modeling of retention time distribution of DRAM cell using a Monte-Carlo methodSeonghoon Jin, / Jeong-Hyong Yi, / Young June Park, / Hong Shick Min, / Jae Hoon Choi, / Dae Gwan Kang, et al. | 2004
- 399
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16.3 Modeling of Retention Time Distribution of DRAM Cell Using a Monte-Carlo MethodJin, S. / Yi, J.-H. / Choi, J. H. / Kang, D. G. / Park, Y. J. / Min, H. S. / IEEE et al. | 2004
- 403
-
A comprehensive trapped charge profiling technique for SONOS flash EEPROMsNair, P.R. / Kumar, B. / Sharma, R. / Mahapatra, S. / Kamohara, S. et al. | 2004
- 403
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16.4 A Comprehensive Trapped Charge Profiling Technique for SONOS Flash EEPROMsNair, P. R. / Kumar, P. B. / Sharma, R. / Kamohara, S. / Mahapatra, S. / IEEE et al. | 2004
- 407
-
16.5 Experimental Extraction of Electron Impact-Ionization Coefficient at Large Operating TemperaturesReggiani, S. / Gnani, E. / Rudan, M. / Baccarani, G. / Corvasce, C. / Barlini, D. / Ciappa, M. / Fichtner, W. / Denison, M. / Jensen, N. et al. | 2004
- 407
-
Experimental extraction of the electron impact-ionization coefficient at large operating temperaturesReggiani, S. / Gnani, E. / Rudan, M. / Baccarani, G. / Corvasce, C. / Barlini, D. / Ciappa, M. / Fichtner, W. / Denison, M. / Jensen, N. et al. | 2004
- 411
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16.6 Electro-Thermal Comparison and Performance Optimization of Thin-Body SOI and GOI MOSFETsPop, E. / Chui, C. O. / Sinha, S. / Dutton, R. / Goodson, K. / IEEE et al. | 2004
- 411
-
Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETsPop, E. / Chi On Chui, / Dutton, R. / Sinha, S. / Goodson, K. et al. | 2004
- 415
-
Power optimization of future transistors and a resulting global comparison standardKapur, P. / Shenoy, R.S. / Chao, A.K. / Nishi, Y. / Saraswat, K.C. et al. | 2004
- 415
-
16.7 Power Optimization of Future Transistors and a Resulting Global Comparison StandardKapur, P. / Shenoy, R. S. / Chao, A. K. / Nishi, Y. / Saraswat, K. C. / IEEE et al. | 2004
- 419
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Session 17 - CMOS Devices - Aggressively Scaled Planar MOSFETs| 2004
- 421
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Circuit techniques for subthreshold leakage avoidance, control and toleranceBorkar, S. et al. | 2004
- 421
-
17.1 Circuit Techniques for Subthreshold Leakage Avoidance, Control, and Tolerance (Invited)Borkar, S. / IEEE et al. | 2004
- 425
-
A conventional 45nm CMOS node low-cost platform for general purpose and low power applicationsBoeuf, F. / Arnaud, F. / Basso, M.T. / Sotta, D. / Wacquant, F. / Rosa, J. / Bicais-Lepinay, N. / Bernard, H. / Bustos, J. / Manakli, S. et al. | 2004
- 425
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17.2 A Conventional 45nm CMOS Node Low-Cost Platform for General Purpose and Low Power ApplicationsBoeuf, F. / Arnaud, F. / Tavel, B. / Duriez, B. / Bidaud, M. / Gouraud, P. / Chaton, C. / Morin, P. / Todeschini, J. / Jurdit, M. et al. | 2004
- 429
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17.3 Transport Properties of Sub-10-nm Planar-Bulk-CMOS DevicesWakabayashi, H. / Ezaki, T. / Hane, M. / Ikezawa, T. / Sakamoto, T. / Kawaura, H. / Yamagami, S. / Ikarashi, N. / Takeuchi, K. / Yamamoto, T. et al. | 2004
- 429
-
Transport properties of sub-10-nm planar-bulk-CMOS devicesWakabayashi, H. / Ezaki, T. / Hane, M. / Yamagami, S. / Ikarashi, N. / Takeuchi, K. / Yamamoto, T. / Mogami, T. / Ikezawa, T. / Sakamoto, T. et al. | 2004
- 433
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Direct evaluation of gate line edge roughness impact on extension profiles in sub-50nm N-MOSFETsFukutome, H. / Aoyama, T. / Momiyama, Y. / Kubo, T. / Tagawa, Y. / Arimoto, H. et al. | 2004
- 433
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17.4 Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50nm N-MOSFETsFukutome, H. / Momiyama, Y. / Kubo, T. / Tagawa, Y. / Aoyama, T. / Arimoto, H. / IEEE et al. | 2004
- 437
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Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performancesDucroquet, F. / Ernst, T. / Hartmann, J.-M. / Weber, O. / Andrieu, F. / Holliger, P. / Laugier, F. / Rivallin, P. / Guegan, G. / Lafond, D. et al. | 2004
- 437
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17.5 Double SiGe:C Diffusion Barrier Channel 40nm CMOS with Improved Short-Channel PerformancesDucroquet, F. / Ernst, T. / Hartmann, J.-M. / Weber, O. / Andrieu, F. / Holliger, P. / Laugier, F. / Rivallin, P. / Guegan, G. / LaFond, D. et al. | 2004
- 441
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17.6 Record RF Performance of Standard 90 nm CMOS TechnologyTiemeijer, L. F. / Havens, R. J. / de Kort, R. / Scholten, A. / van Langevelde, R. / Klaassen, D. B. M. / Sasse, G. T. / Bouttement, Y. / Petot, C. / Bardy, S. et al. | 2004
- 441
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Record RF performance of standard 90 nm CMOS technologyTiemeijer, L.F. / Havens, R.J. / de Kort, R. / Scholten, A.J. / van Langevelde, R. / Klaassen, D.B.M. / Sasse, G.T. / Bouttement, Y. / Petot, C. / Bardy, S. et al. | 2004
- 445
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Session 18 - Solid State Devices - Power, RF, and Passives Technology| 2004
- 447
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High-voltage extension(V/sub BR/ /spl ges/ 800 V) for smart-power SOI-technologiesRotter, T. / Stoisiek, M. et al. | 2004
- 447
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18.1 High-Voltage Extension (Vbr >or= 800 V) for Smart-Power SOI-TechnologiesRotter, T. / Stoisiek, M. / IEEE et al. | 2004
- 451
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18.2 Membrane High Voltage Devices "A Milestone Concept in Power ICs"Udrea, F. / Trajkovic, T. / Amaratunga, G. A. J. / IEEE et al. | 2004
- 451
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High voltage devices - a milestone concept in power ICsUdrea, F. / Trajkovic, T. / Amaratunga, G.A.J. et al. | 2004
- 455
-
RF power potential of 90 nm CMOS: device options, performance, and reliabilityScholvin, J. / Greenberg, D.R. / del Alamo, J.A. et al. | 2004
- 455
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18.3 RF Power Potential of 90 nm CMOS: Device Options, Performance, and ReliabilityScholvin, J. / Greenberg, D. R. / del Alamo, J. A. / IEEE et al. | 2004
- 459
-
18.4 Lateral IMPATT Diodes in Standard CMOS TechnologyAl-Attar, T. / Mulligan, M. D. / Lee, T. H. / IEEE et al. | 2004
- 459
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Lateral IMPATT diodes in standard CMOS technologyAl-Attar, T. / Mulligan, M.D. / Lee, T.H. et al. | 2004
- 463
-
New low-cost thermally stable process to reduce silicon substrate: a way to extreme frequencies for high volume Si technologiesDetcheverry, C. / van Noort, W.D. / Havens, R.J. et al. | 2004
- 463
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18.5 New Low-Cost Thermally Stable Process to Reduce Silicon Substrate Losses: A Way to Extreme Frequencies for High Volume Si TechnologiesDetcheverry, C. / van Noort, W. D. / Havens, R. J. / IEEE et al. | 2004
- 467
-
18.6 Novel Differential Inductor Design for High Self-Resonance FrequencyFindley, P. / Rezvani, G. A. / Tao, J. / IEEE et al. | 2004
- 467
-
Novel differential inductor design for high self-resonance frequencyFindley, P. / Ali Rezvani, G. / Tao, J. et al. | 2004
- 471
-
Session 19 - CMOS and Interconnect Reliability - Process Induced and Electrical Degradation in Flash Memories and CMOS Circuits| 2004
- 473
-
19.1 Ionizing Radiation Effects on MOSFET Thin and Ultra-Thin Gate Oxides (Invited)Paccagnella, A. / Cester, A. / Cellere, G. / IEEE et al. | 2004
- 473
-
Ionizing radiation effects on MOSFET thin and ultra-thin gate oxidesPaccagnella, A. / Cester, A. / Cellere, G. et al. | 2004
- 477
-
19.2 Low Leakage Reliability Characterization Methodology for Advanced CMOS with Gate Oxide in the 1nm Range (Invited)Chung, S. S. / Feng, H. J. / Hsieh, Y. S. / Liu, A. / Lin, W. M. / Chen, D. F. / Ho, J. H. / Huang, K. T. / Yang, C. K. / Cheng, O. et al. | 2004
- 477
-
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm rangeChung, S.S. / Feng, H.J. / Hsich, Y.S. / Liu, A. / Lin, W.M. / Chen, D.F. / Ho, J.H. / Huang, K.T. / Yang, C.L. / Cheng, O. et al. | 2004
- 481
-
Implant damage and gate-oxide-edge effects on product reliabilityYung-Huei Lee, / Nachman, R. / Sam Hu, / Mielke, N. / Liu, J. et al. | 2004
- 481
-
19.3 Implant Damage and Gate-Oxide-Edge Effects on Product ReliabilityLee, Y.-H. / Nachman, R. / Hu, S. / Mielke, N. / Liu, J. / IEEE et al. | 2004
- 485
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19.4 Charge Trapping Effects in HfSiON Dielectrics on the Ring Oscillator Circuit and the Single Stage Inverter OperationKang, C. Y. / Choi, R. / Sim, J. H. / Young, C. / Lee, B. H. / Bersuker, G. / Lee, J. C. / IEEE et al. | 2004
- 485
-
Charge trapping effects in HfSiON dielectrics on the ring oscillator circuit and the single stage inverter operationKang, C.Y. / Lee, J.C. / Choi, R. / Sim, J.H. / Young, C. / Lee, B.H. / Bersuker, G. et al. | 2004
- 489
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19.5 What We Have Learned On Flash Memory Reliability in the Last Ten Years (Invited)Cappelletti, P. / Bez, R. / Modelli, A. / Visconti, A. / IEEE et al. | 2004
- 489
-
What we have learned on flash memory reliability in the last ten yearsCappelletti, P. / Bez, R. / Modelli, A. / Visconti, A. et al. | 2004
- 493
-
High energy oxide traps and anomalous soft-programming in flash memoriesIelmini, D. / Spinelli, A.S. / Robustelli, M. / Lacaita, A.L. / Chiavarone, L. / Visconti, A. et al. | 2004
- 493
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19.6 High-Energy Oxide Traps and Anomalous Soft-Programming in Flash MemoriesIelmini, D. / Spinelli, A. S. / Lacaita, A. L. / Robustelli, M. / Chiavarone, L. / Visconti, A. / IEEE et al. | 2004
- 497
-
Session 20 - Process Technology High-k I: Hafnium-Silicate Dielectrics| 2004
- 499
-
20.1 Careful Examination on the Asymmetric Vfb Shift Problem for Poly-Si/HfSiON Gate Stack and its Solution by the Hf Concentration Control in the Dielectric Near the Poly-Si Interface With Small EOT ExpenseKoyama, M. / Kamimuta, Y. / Ino, T. / Kaneko, A. / Inumiya, S. / Eguchi, K. / Takayanagi, M. / Nishiyama, A. / IEEE et al. | 2004
- 499
-
Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expenseKoyama, M. / Kamimuta, Y. / Ino, T. / Nishiyama, A. / Kaneko, A. / Inumiya, S. / Eguchi, K. / Takayanagi, M. et al. | 2004
- 503
-
The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETsCho, H.-J. / Lee, H.L. / Park, S.G. / Park, H.B. / Jeon, T.S. / Jin, B.J. / Kang, S.B. / Lee, S.G. / Kim, Y.P. / Jung, I.S. et al. | 2004
- 503
-
20.2 The Effects of TaN Thickness and Strained Substrate on the Performance and PBTI Characteristics of Poly-Si/TaN/HfSiON MOSFETsCho, H.-J. / Lee, H. L. / Park, S. G. / Park, H. B. / Jeon, T. S. / Jin, B. J. / Kang, S. B. / Lee, S. G. / Kim, Y. P. / Jung, I. S. et al. | 2004
- 507
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20.3 Impact of Hf Concentration on Performance and Reliability for HfSiON-CMOSFETWatanabe, T. / Takayanagi, M. / Kojima, K. / Sekine, K. / Yamasaki, H. / Eguchi, K. / Ishimaru, K. / Ishiuchi, H. / IEEE et al. | 2004
- 507
-
Impact of Hf concentration on performance and reliability for HfSiON-CMOSFETWatanabe, T. / Takayanagi, M. / Kojima, K. / Ishimaru, K. / Ishiuchi, H. / Sekine, K. / Yamasaki, H. / Eguchi, K. et al. | 2004
- 511
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Characteristics of ALD HfSiO/sub x/ using new Si precursors for gate dielectric applicationsYun-Seok Kim, / Ha Jin Lim, / Hyung-Suk Jung, / Jong-Ho Lee, / Jae-Eun Park, / Sung Kee Han, / Jung Hyoung Lee, / Seok-Joo Doh, / Jong Pyo Kim, / Nae In Lee, et al. | 2004
- 511
-
20.4 Characteristics of ALD HfSiO~x Using New Si Precursors for Gate Dielectric ApplicationsKim, Y.-S. / Lim, H.-J. / Jung, H.-S. / Lee, J.-H. / Park, J.-E. / Han, S. K. / Lee, J. H. / Doh, S.-J. / Kim, J. P. / Lee, N. I. et al. | 2004
- 515
-
20.5 Implementation of HfSiON Gate Dielectric for Sub-60nm DRAM Dual Gate Oxide with Recess Channel Array Transistors (RCAT) and Tungsten GatePark, S. G. / Jin, B. J. / Lee, H. L. / Park, H. B. / Jeon, T. S. / Cho, H.-J. / Kim, S. Y. / Jang, S. I. / Kang, S. B. / Shin, Y. G. et al. | 2004
- 515
-
Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gateSeong Geon Park, / Beom Jun Jin, / Hye Lan Lee, / Hong Bae Park, / Taek Soo Jeon, / Hag-Ju Cho, / Sang Yong Kim, / Soo Ik Jang, / Sang Bom Kang, / Yu Gyun Shin, et al. | 2004
- 519
-
Session 21 - Emerging Technologies Nano-Computing Devices| 2004
- 521
-
21.1 Nanowires: Building Blocks for the Assembly of Integrated NanosystemsLieber, C. / IEEE et al. | 2004
- 521
-
Nanowires: building blocks for the assembly of integrated nanosystemsLieber, C.M. et al. | 2004
- 525
-
21.2 Carbon Nanotube Electronics and OptoelectronicsAvouris, P. / Afzali, A. / Appenzeller, J. / Chen, J. / Freitag, M. / Klinke, C. / Lin, Y.-M. / Tsang, J. C. / IEEE et al. | 2004
- 525
-
Carbon nanotube electronics and optoelectronicsAvouris, P. / Afzali, A. / Appenzeller, J. / Chen, J. / Freitag, M. / Klinke, C. / Lin, Y.-M. / Tsang, J.C. et al. | 2004
- 531
-
21.3 Self-Assembled Monolayer Molecular DevicesWang, W. / Lee, T. / Kretzschmar, I. / Routenberg, D. / Reed, M. / IEEE et al. | 2004
- 531
-
Self-assembled monolayer molecular devicesWenyong Wang, / Takhee Lee, / Kretzschmar, I. / Routenberg, D. / Reed, M.A. et al. | 2004
- 533
-
21.4 Electron Spin Qubits in Quantum DotsHanson, R. / Elzerman, J. M. / van Beveren, L. H. W. / Vandersypen, L. M. K. / Kouwenhoven, L. P. / IEEE et al. | 2004
- 533
-
Electron spin qubits in quantum dotsHanson, R. / Elzerman, J.M. / Willems van Beveren, L.H. / Vandersypen, L.M.K. / Kouwenhoven, L.P. et al. | 2004
- 537
-
Spintronics: semiconductors, molecules and quantum informationKato, Y. / Berezovsky, J. / Awschalom, D.D. et al. | 2004
- 537
-
21.5 Spintronics: Semiconductors, Molecules and Quantum InformationKato, Y. / Berezovsky, J. / Awschalom, D. / IEEE et al. | 2004
- 539
-
Mechanical compution, redux? [Nanoelectromechanical systems]Roukes, M.L. et al. | 2004
- 539
-
21.6 Mechanical Computation, Redux?Roukes, M. / IEEE et al. | 2004
- 543
-
Session 22 - Ouantum Electronics and Compound Semiconductors - Superscaled, Ultrafast HBTs| 2004
- 545
-
Polymer based technologies for microwave and millimeterwave applicationsGrenier, K. / Dubuc, D. / Mazenq, L. / Ducarouge, B. / Bouchriha, F. / Rennane, A. / Pons, P. / Plana, R. / Busquere, J.-P. / Lubecke, V. et al. | 2004
- 545
-
22.1 Polymer Based Technologies for Microwave and Millimeterwave Applications (Invited)Grenier, K. / Dubuc, D. / Mazenq, L. / Busquere, J.-P. / Ducarouge, B. / Bouchriha, F. / Rennane, A. / Lubecke, V. / Pons, P. / Ancey, P. et al. | 2004
- 549
-
22.2 0.25 mum Emitter InP SHBTs with f~T = 550 GHz and BV~c~e~o>2VHafez, W. / Feng, M. / IEEE et al. | 2004
- 549
-
0.25 /spl mu/m emitter InP SHBTs with f/sub T/ = 550 GHz and BV/sub CEO/ > 2VHafez, W. / Feng, M. et al. | 2004
- 553
-
22.3 First Demonstration of Sub-0.25mum-Width Emitter InP-DHBTs with >400GHz ft and >400GHz f~m~a~xHussain, T. / Royter, Y. / Hitko, D. / Montes, M. / Madhav, M. / Milosavljevic, I. / Rajavel, R. / Thomas, S. / Antcliffe, M. / Arthur, A. et al. | 2004
- 553
-
First demonstration of sub-0.25/spl mu/m-width emitter InP-DHBTs with > 400 GHz f/sub t/ and > 400 GHz f/sub max/Hussain, T. / Royter, Y. / Hitko, D. / Montes, M. / Madhav, M. / Milosavljevic, I. / Rajavel, R. / Thomas, S. / Antcliffe, M. / Arthur, A. et al. | 2004
- 557
-
22.4 Ultra High-Speed 0.25mum Emitter InP-InGaAs SHBTs withf~m~a~x of 687 GHzYu, D. / Choi, K. / Lee, K. / Kim, B. / Zhu, H. / Vargason, K. / Kuo, J. M. / Pinsukanjana, P. / Kao, Y. C. / IEEE et al. | 2004
- 557
-
Ultra high-speed 0.25-/spl mu/m emitter InP-InGaAs SHBTs with f/sub max/ of 687 GHzDaekyu Yu, / Kwangsik Choi, / Kyungho Lee, / Bumman Kim, / Zhu, H. / Vargason, K. / Kuo, J.M. / Pinsukanjana, P. / Kao, Y.C. et al. | 2004
- 561
-
Flip-chip mounted 26 V GaInP/GaAs power HBTsKurpas, P. / Maassdorf, A. / Neuner, M. / Heymann, P. / Janke, B. / Schnieder, F. / Bergunde, T. / Grasshoff, T. / Heinrich, W. / Wurfl, J. et al. | 2004
- 561
-
22.5 Flip-Chip Mounted 26 V GaInP/GaAs Power HBTsKurpas, P. / Maassdorf, A. / Neuner, M. / Doser, W. / Heymann, P. / Janke, B. / Schnieder, F. / Bergunde, T. / Grasshoff, T. / Blanck, H. et al. | 2004
- 565
-
Session 23 - Integrated Circuits and Manufacturing - Non-Volatile Memory Technology; MRAM, RRAM AND FERAM| 2004
- 567
-
23.1 Status and Outlook of Emerging Nonvolatile Memory Technologies (Invited)Muller, G. / Happ, T. / Kund, M. / Lee, G. Y. / Nagel, N. / Sezi, R. / IEEE et al. | 2004
- 567
-
Status and outlook of emerging nonvolatile memory technologiesMuller, G. / Happ, T. / Kund, M. / Gill Yong Lee, / Nagel, N. / Sezi, R. et al. | 2004
- 571
-
23.2 Design and Process Integration for High-Density, High-Speed, and Low-Power 6F^2 Cross Point MRAM CellAsao, Y. / Kajiyama, T. / Fukuzumi, Y. / Amano, M. / Aikawa, H. / Ueda, T. / Kishi, T. / Ikegawa, S. / Tsuchida, K. / Iwata, Y. et al. | 2004
- 571
-
Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cellAsao, Y. / Amano, M. / Aikawa, H. / Ueda, T. / Kishi, T. / Ikegawa, S. / Tsuchida, K. / Yoda, H. / Kajiyama, T. / Fukuzumi, Y. et al. | 2004
- 575
-
23.3 High Density and Low Power Design of MRAMHung, C. C. / Kao, M. J. / Chen, Y. H. / Wang, Y. H. / Hsu, H. H. / Chen, C. M. / Lee, Y. J. / Chen, W. C. / Lee, J. Y. / Chen, W. S. et al. | 2004
- 575
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High density and low power design of MRAMHung, C.C. / Kao, M.J. / Chen, Y.S. / Wang, Y.H. / Hsu, H.H. / Chen, C.M. / Lee, Y.J. / Chen, W.C. / Lee, J.Y. / Chen, W.S. et al. | 2004
- 579
-
A 0.13/spl mu/m MRAM with 0.26/spl times/0.44/spl mu/m/sup 2/ MTJ optimized on universal MR-RA relation for 1.2V high-speed operation beyond 143MHzUeno, S. / Eimori, T. / Kuroiwa, T. / Furuta, H. / Tsuchimoto, J. / Maejima, S. / Iida, S. / Ohshita, H. / Hasegawa, S. / Hirano, S. et al. | 2004
- 579
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23.4 A 0.13mum MRAM with 0.26x0.44mum^2 MTJ Optimized on Universal MR-RA Relation for 1.2V High-Speed Operation Beyond 143MHzUeno, S. / Eimori, T. / Kuroiwa, T. / Furuta, H. / Tsuchimoto, J. / Maejima, S. / Iida, S. / Ohshita, H. / Hasegawa, S. / Hirano, S. et al. | 2004
- 583
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23.5 Improvement of Robustness Against Write Disturbance by Novel Cell Design for High Density MRAMKai, T. / Yoshikawa, M. / Nakayama, M. / Fukuzumi, Y. / Nagase, T. / Kitagawa, E. / Ueda, T. / Kishi, T. / Ikegawa, S. / Asao, Y. et al. | 2004
- 583
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Improvement of robustness against write disturbance by novel cell design for high density MRAMKai, T. / Yoshikawa, M. / Nakayama, M. / Fukuzumi, Y. / Nagase, T. / Kitagawa, E. / Ueda, T. / Kishi, T. / Ikegawa, S. / Asao, Y. et al. | 2004
- 587
-
Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulsesBaek, I.G. / Lee, M.S. / Seo, S. / Lee, M.J. / Seo, D.H. / Suh, D.-S. / Park, J.C. / Park, S.O. / Kim, H.S. / Yoo, I.K. et al. | 2004
- 587
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23.6 Highly Scalable Non-volatile Resistive Memory Using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage PulsesBaek, I. G. / Lee, M. S. / Seo, S. / Lee, M. J. / Seo, D. H. / Suh, D.-S. / Park, J. C. / Park, S. O. / Kim, H. S. / Yoo, I. K. et al. | 2004
- 591
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Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technologyPark, J.H. / Joo, H.J. / Kang, S.K. / Kang, Y.M. / Rhie, H.S. / Koo, B.J. / Lee, S.Y. / Bae, B.J. / Lim, J.E. / Jeong, H.S. et al. | 2004
- 591
-
23.7 Fully Logic Compatible (1.6V Vcc, 2 Additional FRAM Masks) Highly Reliable Sub 10F^2 Embedded FRAM with Advanced Direct Via Technology and Robust 100nm Thick MOCVD PZT TechnologyPark, J. H. / Joo, H. J. / Kang, S. K. / Kang, Y. M. / Rhie, H. S. / Koo, B. J. / Lee, S. Y. / Bae, B. J. / Lim, J. E. / Jeong, H. S. et al. | 2004
- 595
-
Session 24 - Modeling and Simulation - Transport in Nanoscale Silicon-Based FETs-II| 2004
- 597
-
24.1 Scaling Study of Si and Strained Si n-MOSFETs with Different High-k Gate StacksYang, L. / Watling, J. R. / Adam-Lema, F. / Asenov, A. / Barker, J. R. / IEEE et al. | 2004
- 597
-
Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacksLianfeng Yang, / Watling, J.R. / Adam-Lema, F. / Asenov, A. / Barker, J.R. et al. | 2004
- 601
-
24.2 Exploring the Limit of Strain-Induced Performance Gain in p- and n-SSDOI-MOSFETs (Invited)Bufler, F. M. / IEEE et al. | 2004
- 601
-
Exploring the limit of strain-induced performance gain in p- and n-SSDOI-MOSFETsBufler, F.M. et al. | 2004
- 605
-
A Monte-Carlo study of the role of scattering in deca-nanometer MOSFETsPalestri, P. / Esseni, D. / Eminente, S. / Fiegna, C. / Sangiorgi, E. / Selmi, L. et al. | 2004
- 605
-
24.3 A Monte-Carlo Study of the Role of Scattering in Deca-nanometer MOSFETsPalestri, P. / Esseni, D. / Eminente, S. / Fiegna, C. / Sangiorgi, E. / Selmi, L. / IEEE et al. | 2004
- 609
-
Enhanced ballisticity in nano-MOSFETs along the ITRS roadmap: a Monte Carlo studyEminente, S. / Esseni, D. / Palestri, P. / Fiegna, C. / Selmi, L. / Sangiorgi, E. et al. | 2004
- 609
-
24.4 Enhanced Ballisticity in nano-MOSFETs Along the ITRS Roadmap: A Monte Carlo StudyEminente, S. / Esseni, D. / Palestri, P. / Fiegna, C. / Selmi, L. / Sangiorgi, E. / IEEE et al. | 2004
- 613
-
Pragmatic design of nanoscale multi-gate CMOSFossum, J.G. / Wang, L.Q. / Yang, J.W. / Kim, S.H. / Trivedi, V.P. et al. | 2004
- 613
-
24.5 Pragmatic Design of Nanoscale Multi-Gate CMOSFossum, J. G. / Wang, L.-Q. / Yang, J.-W. / Kim, S.-H. / Trivedi, V. P. / IEEE et al. | 2004
- 617
-
24.6 3D Quantum Modeling and Simulation of Multi-Gate Nanowire MOSFETsBescond, M. / Nehari, K. / Autran, J. L. / Cavassilas, N. / Munteanu, D. / Lannoo, M. / IEEE et al. | 2004
- 617
-
3D quantum modeling and simulation of multiple-gate nanowire MOSFETsBescond, M. / Nehari, K. / Autran, J.L. / Cavassilas, N. / Munteanu, D. / Lannoo, M. et al. | 2004
- 621
-
What will end CMOS scaling - money or physics?| 2004
- 623
-
Nanoelectronics - now or never?| 2004
- 625
-
Session 27 - CMOS Devices - Novel SOI and Multi-Channel MOSFETs| 2004
- 627
-
Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance applicationEun-Jung Yoon, / Sung-Young Lee, / Sung-Min Kim, / Min-Sang Kim, / Sung Hwan Kim, / Li Ming, / Sungdae Suk, / Kyounghawn Yeo, / Chang Woo Oh, / Jung-dong Choe, et al. | 2004
- 627
-
27.1 Sub 30 nm Multi-Bridge-Channel MOSFET (MBCFET) with Metal Gate Electrode for Ultra High Performance ApplicationYoon, E.-J. / Lee, S.-Y. / Kim, S.-M. / Kim, M.-S. / Kim, S. H. / Ming, L. / Suk, S. / Yeo, K. / Oh, C. / Choe, J.-D. et al. | 2004
- 631
-
27.2 Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias ControlTsuchiya, R. / Horiuchi, M. / Kimura, S. / Yamaoka, M. / Kawahara, T. / Maegawa, S. / Ipposhi, T. / Ohji, Y. / Matsuoka, H. / IEEE et al. | 2004
- 631
-
Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias controlTsuchiya, R. / Horiuchi, M. / Kimura, S. / Yamaoka, M. / Kawahara, T. / Maegawa, S. / Ipposhi, T. / Ohji, Y. / Matsuoka, H. et al. | 2004
- 635
-
SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cellsMonfray, S. / Chanemougame, D. / Borel, S. / Talbot, A. / Leverd, F. / Planes, N. / Delille, D. / Dutartre, D. / Palla, R. / Morand, Y. et al. | 2004
- 635
-
27.3 SON (Silicon-On-Nothing) Technological CMOS Platform: Highly Performant Devices and SRAM CellsMonfray, S. / Chanemougame, D. / Borel, S. / Talbot, A. / Leverd, F. / Planes, N. / Delille, D. / Dutartre, D. / Palla, R. / Morand, Y. et al. | 2004
- 639
-
27.4 A Novel Multi-channel Field Effect Transistor (McFET) on Bulk Si for High Performance Sub-80nm ApplicationKim, S. M. / Yoon, E. J. / Jo, H. J. / Li, M. / Oh, C. W. / Lee, S. Y. / Yeo, K. H. / Kim, M. S. / Kim, S. H. / Choe, D. U. et al. | 2004
- 639
-
A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm applicationSung Min Kim, / Eun Jung Yoon, / Hye Jin Jo, / Ming Li, / Chang Woo Oh, / Sung Young Lee, / Kyoung Hwan Yeo, / Min Sang Kim, / Sung Hwan Kim, / Dong Uk Choe, et al. | 2004
- 643
-
27.5 Molybdenum-Gate HfO~2 CMOS FinFET TechnologyHa, D. / Takeuchi, H. / Choi, Y.-K. / King, T.-J. / Bai, W. P. / Kwong, D.-L. / Agarwal, A. / Ameen, M. / IEEE et al. | 2004
- 643
-
Molybdenum gate HfO/sub 2/ CMOS FinFET technologyDaewon Ha, / Takeuchi, H. / Choi, Y.-K. / King, T.-J. / Bai, W.P. / Kwong, D.L. / Agarwal, A. / Ameen, M. et al. | 2004
- 647
-
Large scale integration and reliability consideration of triple gate transistorsChoi, J.A. / Kwon Lee, / You Seung Jin, / Yong Jun Lee, / Soo Yong Lee, / Geon Ung Lee, / Seung Hwan Lee, / Min Chul Sun, / Dong Chan Kim, / Young Mi Lee, et al. | 2004
- 647
-
27.6 Large Scale Integration and Reliability Consideration of Triple Gate TransistorsChoi, J. A. / Lee, K. / Jin, Y. S. / Lee, Y. J. / Lee, S. Y. / Lee, G. U. / Lee, S. H. / Sun, M. C. / Kim, D. C. / Lee, Y. M. et al. | 2004
- 651
-
Session 28 - Integrated Circuits and Manufacturing - Advanced Logic and Platform Technologies| 2004
- 653
-
SoC integration in deep submicron CMOSRickert, P. / Haroun, B. et al. | 2004
- 653
-
28.1 SoC Integration in Deep Submicron CMOS (Invited)Rickert, P. / Haroun, B. / IEEE et al. | 2004
- 657
-
28.2 A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 mum^2 SRAM CellBai, P. / Auth, C. / Balakrishnan, S. / Bost, M. / Brain, R. / Chikarmane, V. / Heussner, R. / Hussein, M. / Hwang, J. / Ingerly, D. et al. | 2004
- 657
-
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cellBai, P. / Auth, C. / Balakrishnan, S. / Bost, M. / Brain, R. / Chikarmane, V. / Heussner, R. / Hussein, M. / Hwang, J. / Ingerly, D. et al. | 2004
- 661
-
High performance and low power transistors integrated in 65nm bulk CMOS technologyLuo, Z. / Steegen, A. / Eller, M. / Mann, R. / Baiocco, C. / Nguyen, P. / Kim, L. / Hoinkis, M. / Ku, V. / Klee, V. et al. | 2004
- 661
-
28.3 High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS TechnologyLuo, Z. / Steegen, A. / Eller, M. / Mann, R. / Baiocco, C. / Nguyen, P. / Kim, L. / Hoinkis, M. / Ku, V. / Klee, V. et al. | 2004
- 665
-
28.4 A 65 nm CMOS Technology for Mobile and Digital Signal Processing ApplicationsChatterjee, A. / Yoon, J. / Zhao, S. / Tang, S. / Sadra, K. / Crank, S. / Mogul, H. / Aggarwal, R. / Chatterjee, B. / Lytle, S. et al. | 2004
- 665
-
A 65 nm CMOS technology for mobile and digital signal processing applicationsChatterjee, A. / Yoon, J. / Zhao, S. / Tang, S. / Sadra, K. / Crank, S. / Mogul, H. / Aggarwal, R. / Chatterjee, B. / Lytle, S. et al. | 2004
- 669
-
28.5 A Novel Low Cost 65nm CMOS Process Architecture With Self Aligned Isolation and W Cladded Source/DrainBlosse, A. / Ramkumar, K. / Gopalan, P. / Hsu, C. T. / Narayanan, S. / Narasimhan, G. / Gettle, R. / Kapre, R. / Sharifzadeh, S. / IEEE et al. | 2004
- 669
-
A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drainBlosse, A. / Ramkumar, K. / Gopalan, P. / Hsu, C.T. / Narayanan, S. / Narasimhan, G. / Gettle, R. / Kapre, R. / Sharifzadeh, S. et al. | 2004
- 673
-
Customer oriented technologies for innovative leading edge foundry manufacturingYang, S. / Chen, J. / Chen, S. / Chen, Z. / Fan, A. / He, B. / Jiang, Q. / Kuang, E. / Lin, Y.-F. / Liu, Y. et al. | 2004
- 673
-
28.6 Customer Oriented Technologies for Innovative Leading Edge Foundry Manufacturing (Invited)Yang, S. / Chen, J. / Chen, S. / Chen, Z. / Fan, A. / He, B. / Jiang, Q. / Kuang, E. / Lin, Y.-F. / Liu, Y. et al. | 2004
- 677
-
On-chip transmission line for long global interconnectsIto, H. / Inoue, J. / Gomi, S. / Sugita, H. / Okada, K. / Masu, K. et al. | 2004
- 677
-
28.7 On-Chip Transmission Line for Long Global InterconnectsIto, H. / Inoue, J. / Gomi, S. / Sugita, H. / Okada, K. / Masu, K. / IEEE et al. | 2004
- 681
-
Session 29 - Solid State Devices - Next Generation Devices| 2004
- 683
-
Carbon nanotubes for interconnect applicationsKreup, F. / Graham, A.P. / Liebau, M. / Duesberg, G.S. / Seidel, R. / Unger, E. et al. | 2004
- 683
-
29.1 Carbon Nanotubes for Interconnect Applications (Invited)Kreupl, F. / Graham, A. P. / Liebau, M. / Duesberg, G. S. / Seidel, R. / Unger, E. / IEEE et al. | 2004
- 687
-
29.2 Novel Carbon Nanotube FET Design with Tunable PolarityLin, Y.-M. / Appenzeller, J. / Avouris, P. / IEEE et al. | 2004
- 687
-
Novel carbon nanotube FET design with tunable polarityYu-Ming Lin, / Appenzeller, J. / Avouris, P. et al. | 2004
- 691
-
29.3 High Frequency S Parameters Characterization of Back-gate Carbon Nanotube Field-Effect TransistorsHuo, X. / Zhang, M. / Chan, P. C. H. / Liang, Q. / Tang, Z. K. / IEEE et al. | 2004
- 691
-
High frequency S parameters characterization of back-gate carbon nanotube field-effect transistorsHuo, X. / Zhang, M. / Chan, P.C.H. / Liang, Q. / Tang, Z.K. et al. | 2004
- 695
-
Self-aligned carbon nanotube transistors with novel chemical dopingChen, J. / Klinke, C. / Afzali, A.H. / Chan, K. / Avouris, P. et al. | 2004
- 695
-
29.4 Self-Aligned Carbon Nanotube Transistors with Novel Chemical DopingChen, J. / Klinke, C. / Afzali, A. / Chan, K. / Avouris, P. / IEEE et al. | 2004
- 699
-
Performance comparison between carbon nanotube and copper interconnects for GSINaeemi, A. / Sarvari, R. / Meindl, J.D. et al. | 2004
- 699
-
29.5 Performance Comparison Between Carbon Nanotube and Copper Interconnects for GSINaeemi, A. / Sarvari, R. / Meindl, J. D. / IEEE et al. | 2004
- 703
-
Performance analysis and design optimization of near ballistic carbon nanotube field-effect transistorsJing Guo, / Javey, A. / Hongjai Dai, / Lundstrom, M. et al. | 2004
- 703
-
29.6 Performance Analysis and Design Optimization of Near Ballistic Carbon Nanotube Field-Effect TransistorsGuo, J. / Javey, A. / Dai, H. / Lundstrom, M. / IEEE et al. | 2004
- 707
-
Modulation of drain current by redox-active molecules incorporated in Si MOSFETsGowda, S. / Mathur, G. / Li, Q. / Surthi, S. / Zhao, Q. / Lindsey, J.S. / Bocian, D.F. / Misra, V. et al. | 2004
- 707
-
29.7 Modulation of Drain Current by Redox-Active Molecules Incorporated in Si MOSFETsGowda, S. / Mathur, G. / Li, Q. / Surthi, S. / Zhao, Q. / Lindsey, J. / Bocian, D. F. / Misra, V. / IEEE et al. | 2004
- 711
-
Session 30 - CMOS and Interconnect Reliability - Gate Dielectric Reliability - Breakdown, and Device Degradation Mechanism| 2004
- 713
-
30.1 Implications of Progressive Wear-Out for Lifetime Extrapolation of Ultra-Thin (EOT∼nm) SiON FilmsKaczer, B. / Degraeve, R. / O Connor, R. / Roussel, P. / Groeseneken, G. / IEEE et al. | 2004
- 713
-
Implications of progressive wear-out for lifetime extrapolation of ultra-thin (EOT /spl sim/ 1 nm) SiON filmsKaczer, B. / Degraeve, R. / O'Connor, R. / Roussel, P. / Groeseneken, G. et al. | 2004
- 717
-
30.2 New Insight into Gate Dielectric Breakdown Induced MOSFET Degradation by Novel Percolation Path Resistance MeasurementsPey, K. L. / Lo, V. L. / Tung, C. H. / Chandra, W. / Tang, L. J. / Ang, D. S. / Ranjan, R. / IEEE et al. | 2004
- 717
-
New insight into gate dielectric breakdown induced MOSFET degradation by novel percolation path resistance measurementsPey, K.L. / Lo, V.L. / Tung, C.H. / Chandra, W. / Tang, L.J. / Ang, D.S. / Ranjan, R. et al. | 2004
- 721
-
30.3 Model for Dielectric Breakdown Mechanism of HfAlO~x/SiO~2 Stacked Gate Dielectrics Dominated by the Generated Subordinate Carrier InjectionOkada, K. / Mizubayashi, W. / Yasuda, N. / Satake, H. / Ota, H. / Kadoshima, M. / Tominaga, K. / Ogawa, A. / Iwamoto, K. / Horikawa, T. et al. | 2004
- 721
-
Model for dielectric breakdown mechanism of HfAlO/sub x//SiO/sub 2/ stacked gate dielectrics dominated by the generated subordinate carrier injectionOkada, K. / Mizubayashi, W. / Yasuda, N. / Satake, H. / Ota, H. / Kadoshima, M. / Tominaga, K. / Ogawa, A. / Iwamoto, K. / Horikawa, T. et al. | 2004
- 725
-
30.4 A Comprehensive Model for Breakdown Mechanism in HfO~2 High-k Gate StacksRanjan, R. / Pey, K. L. / Tung, C. H. / Tang, L. J. / Groeseneken, G. / Bera, L. K. / De Gendt, S. / IEEE et al. | 2004
- 725
-
A comprehensive model for breakdown mechanism in HfO/sub 2/ high-k gate stacksRanjan, R. / Pey, K.L. / Tung, C.H. / Tang, L.J. / Groeseneken, G. / Bera, L.K. / De Gendt, S. et al. | 2004
- 729
-
Charge trapping in aggressively scaled metal gate/high-k stacksGusev, E.P. / Narayanan, V. / Zafar, S. / Cabral, C. / Carrier, E. / Bojarczuk, N. / Callegari, A. / Carruthers, R. / Chudzik, M. / D'Emic, C. et al. | 2004
- 729
-
30.5 Charge Trapping in Aggressively Scaled Metal Gate/High-k StacksGusev, E. P. / Narayanan, V. / Zafar, S. / Cabral, C. / Cartier, E. / Bojarczuk, N. / Callegari, A. / Carruthers, R. / Chudzik, M. / D Emic, C. et al. | 2004
- 733
-
30.6 Negative U Traps in HfO~2 Gate Dielectrics and Frequency Dependence of Dynamic BTI in MOSFETsShen, C. / Li, M. F. / Wang, X. P. / Yu, H. Y. / Feng, Y. P. / Lim, A. T.-L. / Yeo, Y. C. / Chan, D. S. H. / Kwong, D. L. / IEEE et al. | 2004
- 733
-
Negative U traps in HfO/sub 2/ gate dielectrics and frequency dependence of dynamic BTI in MOSFETsShen, C. / Li, M.F. / Wang, X.P. / Yu, H.Y. / Feng, Y.P. / Lim, A.T.L. / Yeo, Y.C. / Chan, D.S.H. / Kwong, D.L. et al. | 2004
- 737
-
Characterization and modeling of hysteresis phenomena in high K dielectricsLeroux, C. / Mitard, J. / Ghibaudo, G. / Garros, X. / Reimbold, G. / Guillaumor, B. / Martin, F. et al. | 2004
- 737
-
30.7 Characterization and Modeling of Hysteresis Phenomena in High K DielectricsLeroux, C. / Mitard, J. / Ghibaudo, G. / Garros, X. / Reimbold, G. / Guillaumot, B. / Martin, F. / IEEE et al. | 2004
- 741
-
Session 31- Modeling and Simulation - Compact Modeling| 2004
- 743
-
31.1 A New Cell-Based Performance Metric for Novel CMOS Device ArchitecturesChristie, P. / Heringa, A. / Doornbos, G. / Kumar, A. / Nguyen, V. H. / Ng, R. K. M. / Garg, M. / IEEE et al. | 2004
- 743
-
A new cell-based performance metric for novel CMOS device architecturesChristie, P. / Heringa, A. / Doornbos, G. / Kumar, A. / Nguyen, V.H. / Ng, R.K.M. / Garg, M. et al. | 2004
- 747
-
31.2 Predictive Compact Modeling of NQS Effects and Thermal Noise in 90nm Mixed-Signal/RF CMOS TechnologyShih, W.-K. / Mudanai, S. / Rios, R. / Packan, P. / Becher, D. / Basco, R. / Hung, C. / Jalan, U. / IEEE et al. | 2004
- 747
-
Predictive compact modeling of NQS effects and thermal noise in 90nm mixed-signal/RF CMOS technologyWei-Kai Shih, / Mudanai, S. / Rios, R. / Packan, P. / Becher, D. / Basco, R. / Hung, C. / Jalan, U. et al. | 2004
- 751
-
Capacitance modeling of laterally non-uniform MOS devicesAarts, A.C.T. / van der Hout, R. / Paasschens, J.C.J. / Scholten, A.J. / Willemsen, M. / Klaassen, D.B.M. et al. | 2004
- 751
-
31.3 Capacitance Modeling of Laterally Non-Uniform MOS DevicesAarts, A. C. T. / van der Hout, R. / Paasschens, J. C. J. / Scholten, A. J. / Willemsen, M. / Klaassen, D. B. M. / IEEE et al. | 2004
- 755
-
31.4 An Efficient Surface Potential Solution Algorithm for Compact MOSFET ModelsRios, R. / Mudanai, S. / Shih, W.-K. / Packan, P. / IEEE et al. | 2004
- 755
-
An efficient surface potential solution algorithm for compact MOSFET modelsRios, R. / Mudanai, S. / Wei-Kai Shih, / Packan, P. et al. | 2004
- 759
-
31.5 Modeling of RTS Noise in MOSFETs Under Steady-State and Large-Signal ExcitationKolhatkar, J. S. / Hoekstra, E. / Salm, C. / van der Wel, A. P. / Klumperink, E. A. M. / Schmitz, J. / Wallinga, H. / IEEE et al. | 2004
- 759
-
Modeling of RTS noise in MOSFETs under steady-state and large-signal excitationKolhatkar, J.S. / Hoekstra, E. / Salm, C. / van der Wel, A.P. / Klumperink, E.A.M. / Schmitz, J. / Wallinga, H. et al. | 2004
- 763
-
A compact QM-based mobility model for nanoscale ultra-thin-body CMOS devicesTrivedi, V.P. / Fossum, J.G. / Gamiz, F. et al. | 2004
- 763
-
31.6 A Compact QM-Based Mobility Model for Nanoscale Ultra-Thin-Body CMOS DevicesTrivedi, V. P. / Fossum, J. G. / Gamiz, F. / IEEE et al. | 2004
- 767
-
Session 32 - Displays, Sensors and MEMS - Thin Film Transistors| 2004
- 769
-
A novel transparent air-stable printable n-type semiconductor technology using ZnO nanoparticlesVolkman, S.K. / Mattis, B.A. / Molesa, S.E. / Lee, J.B. / de la Fuente Vornbrock, A. / Bakhishev, T. / Subramanian, V. et al. | 2004
- 769
-
32.1 A Novel Transparent Air-Stable Printable n-Type Semiconductor Technology Using ZnO NanoparticlesVolkman, S. K. / Molesa, S. E. / Lee, J. B. / Mattis, B. A. / de la Fuente Vornbrock, A. / Bakhishev, T. / Subramanian, V. / IEEE et al. | 2004
- 773
-
Single-grain TFTs on location-controlled crystal grains formed by excimer laser crystallization of Si thin filmsKumomi, H. / Shin, C. / Nakagawa, G. / Asano, T. et al. | 2004
- 773
-
32.2 Single-Grain TFTs on Location-Controlled Crystal Grains Formed by Excimer Laser Crystallization of Si Thin FilmsKumomi, H. / Shin, C. / Nakagawa, G. / Asano, T. / IEEE et al. | 2004
- 777
-
High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channelsYung-Chun Wu, / Chun-Yen Chang, / Ting-Chang Chang, / Po-Tsun Liu, / Chi-Shen Chen, / Chun-Hao Tu, / Hsiao-Wen Zan, / Ya-Hsiane Tai, / Simon Min Sze, et al. | 2004
- 777
-
32.3 High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire ChannelWu, Y.-C. / Chang, C.-Y. / Chang, T.-C. / Liu, P.-T. / Chen, C.-S. / Tu, C.-H. / Zan, H.-W. / Tai, Y.-H. / Sze, S. M. / IEEE et al. | 2004
- 781
-
A novel methodology for extracting effective density-of-states in poly-Si thin-film transistorsLin, H.-C. / Yeh, K.-L. / Lee, M.-H. / Su, Y.-C. / Huang, T.-Y. / Shen, S.-W. / Lin, H.-Y. et al. | 2004
- 781
-
32.4 A Novel Methodology for Extracting Effective Density-of-States in Poly-Si Thin-Film TransistorsLin, H.-C. / Yeh, K.-L. / Lee, M.-H. / Su, Y.-C. / Huang, T.-Y. / Shen, S.-W. / Lin, H.-Y. / IEEE et al. | 2004
- 785
-
32.5 Analytical Photo Leak Current Model of Low Temperature CW Laser Lateral Crystallization (CLC) Poly-Si TFTsSuzuki, K. / Takeuchi, F. / Ebiko, Y. / Chida, M. / Sasaki, N. / IEEE et al. | 2004
- 785
-
Analytical photo leak current model of low-temperature CW laser lateral crystallization (CLC) poly-Si TFTsSuzuki, K. / Takeuchi, F. / Ebiko, Y. / Chida, M. / Sasaki, N. et al. | 2004
- 789
-
Impact of transistor-to-grain size statistics on large-grain polysilicon TFT characteristicsCheng, C.F. / Poon, M.C. / Kok, C.W. / Mansun Chan, et al. | 2004
- 789
-
32.6 Impact of Transistor-to-Grain Size Statistics on Large-Grain Polysilicon TFT CharacteristicsCheng, C. F. / Poon, M. C. / Kok, C. W. / Chan, M. / IEEE et al. | 2004
- 793
-
Session 33 - Quantum Electronics and Compound Semiconductors - GaN-based Power Devices| 2004
- 795
-
Recent advances in III-V nitride electronic devicesPavlidis, D. et al. | 2004
- 795
-
33.1 Recent Advances in III-V Nitride Electronic Devices (Invited)Pavlidis, D. / IEEE et al. | 2004
- 799
-
A 100-W high-gain AlGaN/GaN HEMT power amplifier on a conductive n-SiC substrate for wireless base station applicationsKanamura, M. / Kikkawa, T. / Joshin, K. et al. | 2004
- 799
-
33.2 A 100W High-Gain AlGaN/GaN HEMT Power Amplifier on a Conductive N-SiC Substrate for Wireless Base Station ApplicationsKanamura, M. / Kikkawa, T. / Joshin, K. / IEEE et al. | 2004
- 803
-
350V/150A AlGaN/GaN power HFET on silicon substrate with source-via grounding (SVG) structureHikita, M. / Yanagihara, M. / Nakazawa, K. / Ueno, H. / Hirose, Y. / Ueda, T. / Uemoto, Y. / Tanaka, T. / Ueda, D. / Egawa, T. et al. | 2004
- 803
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33.3 350V/150A AlGaN/GaN Power HFET on Silicon Substrate with Source-via Grounding (SVG) StructureHikita, M. / Yanagihara, M. / Nakazawa, K. / Ueno, H. / Hirose, Y. / Ueda, T. / Uemoto, Y. / Tanaka, T. / Ueda, D. / Egawa, T. et al. | 2004
- 807
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33.4 GaN Double Heterojunction Field Effect Transistor For Microwave and Millimeterwave Power ApplicationsMicovic, M. / Hashimoto, P. / Hu, M. / Milosavljevic, I. / Duvall, J. / Willadsen, P. J. / Wong, W.-S. / Conway, A. M. / Kurdoghlian, A. / Deelman, P. W. et al. | 2004
- 807
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GaN double heterojunction field effect transistor for microwave and millimeterwave power applicationsMicovic, M. / Hashimoto, P. / Ming Hu, / Milosavljevic, I. / Duvall, J. / Willadsen, P.J. / Wong, W.-S. / Conway, A.M. / Kurdoghlian, A. / Deelman, P.W. et al. | 2004
- 811
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Al/sub 0.3/Ga/sub 0.7/N/Al/sub 0.05/Ga/sub 0.95/N/GaN composite-channel HEMTs with enhanced linearityJie Liu, / Yugang Zhou, / Rongming Chu, / Yong Cai, / Chen, K.J. / Kei May Lau, et al. | 2004
- 811
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33.5 Al~0~.~3Ga~0~.~7N/Al~0~.~0~5Ga~0~.~9~5N/GaN Composite-Channel HEMTs with Enhanced LinearityLiu, J. / Zhou, Y. / Chu, R. / Cai, Y. / Chen, K. J. / Lau, K. M. / IEEE et al. | 2004
- 815
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Edge trapping mechanism of current collapse in III-N FETsBraga, N. / Mickevicius, R. / Gaska, R. / Shur, M.S. / Asif Khan, M. / Simin, G. et al. | 2004
- 815
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33.6 Edge Trapping Mechanism of Current Collapse in III-N FETsBraga, N. / Mickevicius, R. / Gaska, R. / Shur, M. S. / Khan, M. A. / Simin, G. / IEEE et al. | 2004
- 819
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Session 34 - Process Technology - High-k II: Interfaces and Materials Properties| 2004
- 821
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Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stackTseng, H.-H. / Capasso, C.C. / Schaeffer, J.K. / Hebert, E.A. / Tobin, P.J. / Gilmer, D.C. / Triyoso, D. / Ramon, M.E. / Kalpat, S. / Luckowski, E. et al. | 2004
- 821
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34.1 Improved Short Channel Device Characteristics with Stress Relieved Pre-Oxide (SRPO) And a Novel Tantalum Carbon Alloy Metal Gate/HfO~2 StackTseng, H.-H. / Capasso, C. C. / Schaeffer, J. K. / Hebert, E. A. / Tobin, P. J. / Gilmer, D. C. / Triyoso, D. / Ramon, M. E. / Kalpat, S. / Luckowski, E. et al. | 2004
- 825
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34.2 Interface Engineering for Enhanced Electron Mobilities in W/HfO~2 Gate StacksCallegari, A. / Cartier, E. / Jamison, P. / Zafar, S. / Gusev, E. / Narayanan, V. / D Emic, C. / Lacey, D. / McFeely, F. / Jammy, R. et al. | 2004
- 825
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Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacksCallegari, A. / Jamison, P. / Carrier, E. / Zafar, S. / Gusev, E. / Narayanan, V. / D'Emic, C. / Lacey, D. / Feely, F.M. / Jammy, R. et al. | 2004
- 829
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34.3 Impact of Oxygen Vacancies on High-k Gate Stack EngineeringTakeuchi, H. / Wong, H. Y. / Ha, D. / King, T.-J. / IEEE et al. | 2004
- 829
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Impact of oxygen vacancies on high-/spl kappa/ gate stack engineeringTakeuchi, H. / Hiu Yung Wong, / Daewon Ha, / Tsu-Jae King, et al. | 2004
- 833
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Depletion-free poly-Si gate high-k CMOSFETsKim, W.S. / Kamiyama, S. / Aoyama, T. / Itoh, H. / Maeda, T. / Kawahara, T. / Torii, K. / Kitajima, H. / Arikado, T. et al. | 2004
- 833
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34.4 Depletion-Free Poly-Si Gate High-k CMOSFETsKim, W. S. / Kamiyama, S. / Aoyama, T. / Itoh, H. / Maeda, T. / Kawahara, T. / Torii, K. / Kitajima, H. / Arikado, T. / IEEE et al. | 2004
- 837
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Improved electrical and material characteristics of hafnium titanate multi-metal oxide n-MOSFETs with ultra-thin EOT (/spl sim/8 /spl Aring/) gate dielectric applicationSe Jong Rhee, / Chang Seok Kang, / Chang Hwan Choi, / Chang Yong Kang, / Siddarth Krishnan, / Manhong Zhang, / Akbar, M.S. / Lee, J.C. et al. | 2004
- 837
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34.5 Improved Electrical and Material Characteristics of Hafnium Titanate Multi-metal Oxide n-MOSFETs with Ultra-thin EOT (∼8A) Gate Dielectric ApplicationRhee, S. J. / Kang, C. S. / Choi, C. H. / Kang, C. Y. / Krishnan, S. / Zhang, M. / Akbar, M. S. / Lee, J. C. / IEEE et al. | 2004
- 841
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34.6 A Robust Alternative for the DRAM Capacitor of 50nm GenerationLee, K. H. / Chung, S.-J. / Kim, J. Y. / Kim, K.-C. / Lim, J.-S. / Cho, K. / Lee, J. / Chung, J.-H. / Lim, H. J. / Choi, K. et al. | 2004
- 841
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A robust alternative for the DRAM capacitor of 50 nm generationKwang Hee Lee, / Suk-Jin Chung, / Jin Yong Kim, / Ki-Chul Kim, / Jae-Soon Lim, / Kyuho Cho, / Jinil Lee, / Jeong-Hee Chung, / HanJin Lim, / KyungIn Choi, et al. | 2004
- 845
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Session 35 - CMOS Devices Advanced - Gate-Stack Devices| 2004
- 847
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Gate stack optimization for 65 nm CMOS low power and high performance platformDuriez, B. / Tavel, B. / Boeuf, R. / Basso, M.T. / Laplanche, Y. / Ortolland, C. / Reber, D. / Wacquant, R. / Morin, P. / Lenoble, D. et al. | 2004
- 847
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35.1 Gate Stack Optimization for 65nm CMOS Low Power and High Performance PlatformDuriez, B. / Tavel, B. / Boeuf, F. / Basso, M. T. / Laplanche, Y. / Ortolland, C. / Reber, D. / Wacquant, F. / Morin, P. / Lenoble, D. et al. | 2004
- 851
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35.2 45nm nMOSFET with Metal Gate on Thin SiON Driving 1150muA/mum and Off-state of 10nA/mumHenson, K. / Lander, R. J. P. / Demand, M. / Dachs, C. J. J. / Kaczer, B. / Deweerd, W. / Schram, T. / Tokei, Z. / Hooker, J. C. / Cubaynes, F. N. et al. | 2004
- 851
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45 nm nMOSFET with metal gate on thin SiON driving 1150 /spl mu/A//spl mu/m and off-state of 10nA//spl mu/mHenson, K. / Lander, R.J.P. / Demand, M. / Dachs, C.J.J. / Kaczer, B. / Deweerd, W. / Schram, T. / Tokei, Z. / Hooker, J.C. / Cubaynes, F.N. et al. | 2004
- 855
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35.3 Work Function Engineering by FUSI and Its Impact on the Performance and Reliability of Oxynitride and Hf-silicate Based MOSFETsVeloso, A. / Anil, K. G. / Witters, L. / Brus, S. / Kubicek, S. / de Marneffe, J.-F. / Sijmus, B. / Devriendt, K. / Lauwers, A. / Kauerauf, T. et al. | 2004
- 855
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Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETsVeloso, A. / Anil, K.G. / Witters, L. / Brus, S. / Kubicek, S. / de Marneffe, J.-F. / Sijmus, B. / Devriendt, K. / Lauwers, A. / Kauerauf, T. et al. | 2004
- 859
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Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)Lee, B.H. / Young, C.D. / Choi, R. / Sim, J.H. / Bersuker, G. / Kang, C.Y. / Harris, R. / Brown, G.A. / Matthews, K. / Song, S.C. et al. | 2004
- 859
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35.4 Intrinsic Characteristics of High-k Devices and Implications of Fast Transient Charging Effects (FTCE) (Invited)Lee, B. H. / Young, C. D. / Choi, R. / Sim, J. H. / Bersuker, G. / Kang, C. Y. / Harris, R. / Brown, G. A. / Matthews, K. / Song, S. C. et al. | 2004
- 863
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Ultra-fast measurements of the inversion charge in MOSFETs and impact on measured mobility in high-k MOSFETsSingh, D.V. / Solomon, P. / Gusev, E.P. / Singco, G. / Ren, Z. et al. | 2004
- 863
-
35.5 Ultra-fast Measurements of the Inversion Charge in MOSFETs and Impact on Measured Mobility in High-k MOSFETsSingh, D. V. / Solomon, P. / Gusev, E. P. / Singco, G. / Ren, Z. / IEEE et al. | 2004
- 867
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35.6 Experimental Determination of Mobility Scattering Mechanisms in Si/HfO~2/TiN and SiGe:C/HfO~2/TiN Surface Channel n- and p-MOSFETsWeber, O. / Andrieu, F. / Cassa, M. / Ernst, T. / Mitard, J. / Ducroquet, F. / Damlencourt, J.-F. / Hartmann, J.-M. / Lafond, D. / Papon, A.-M. et al. | 2004
- 867
-
Experimental determination of mobility scattering mechanisms in Si/HfO/sub 2//TiN and SiGe:C/HfO/sub 2//TiN surface channel n- and p-MOSFETsWeber, O. / Andrieu, F. / Casse, M. / Ernst, T. / Mitard, J. / Ducroquet, F. / Damlencourt, J.-F. / Hartmann, J.-M. / Lafond, D. / Papon, A.-M. et al. | 2004
- 871
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Session 36 - Integrated Circuits and Manufacturing - Floating-Gate and Discrete Trap Non-Volatile Memory| 2004
- 873
-
8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technologyJong-Ho Park, / Sung-Hoi Hur, / Joon-Hee Leex, / Jin-Taek Park, / Jong-Sun Sel, / Jong-Won Kim, / Sang-Bin Song, / Jung-Young Lee, / Ji-Hwon Lee, / Suk-Joon Son, et al. | 2004
- 873
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36.1 8Gb MLC (Multi-Level Cell) NAND Flash Memory Using 63nm Process TechnologyPark, J.-H. / Hur, S.-H. / Lee, J.-H. / Park, J.-T. / Sel, J.-S. / Kim, J.-W. / Song, S.-B. / Lee, J.-Y. / Son, S.-J. / IEEE et al. | 2004
- 877
-
Impact of few electron phenomena on floating-gate memory reliabilityMolas, G. / Deleruyelle, D. / De Salvo, B. / Ghibaudo, G. / Gely, M. / Jacob, S. / Lafond, D. / Deleonibus, S. et al. | 2004
- 877
-
36.2 Impact of Few Electron Phenomena on Floating-Gate Memory ReliabilityMolas, G. / Deleruyelle, D. / De Salvo, B. / Ghibaudo, G. / Gely, M. / Jacob, S. / Lafond, D. / Deleonibus, S. / IEEE et al. | 2004
- 881
-
A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle enduranceYen-Hao Shih, / Hang-Ting Lue, / Kuang-Yeu Hsieh, / Rich Liu, / Chih-Yuan Lu, et al. | 2004
- 881
-
36.3 A Novel 2-bits/cell Nitride Storage Flash Memory with Greater than 1M P/E-Cycle EnduranceShih, Y.-H. / Lue, H.-T. / Hsieh, K. Y. / Liu, R. / Lu, C.-Y. / IEEE et al. | 2004
- 885
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36.4 Impact of SiON on Embedded Nonvolatile MNOS MemoryIshimaru, T. / Matsuzaki, N. / Okuyama, Y. / Mine, T. / Watanabe, K. / Yugami, J. / Kume, H. / Ito, F. / Kawashima, Y. / Sakai, T. et al. | 2004
- 885
-
Impact of SiON on embedded nonvolatile MNOS memoryIshimaru, T. / Matsuzaki, N. / Okuyama, Y. / Mine, T. / Watanabe, K. / Yugami, J. / Kume, H. / Ito, F. / Kawashima, Y. / Sakai, T. et al. | 2004
- 889
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36.5 High-K HfAlO Charge Trapping Layer in SONOS-type Nonvolatile Memory Device for High Speed OperationTan, Y. N. / Chim, W. K. / Choi, W. K. / Joo, M. S. / Ng, T. H. / Cho, B. J. / IEEE et al. | 2004
- 889
-
High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operationYan Ny Tan, / Wai Kin Chim, / Wee Kiong Choi, / Moon Sig Joo, / Tsu Hau Ng, / Byung Jin Cho, et al. | 2004
- 893
-
Damascene gate FinFET SONOS memory implemented on bulk silicon waferChang Woo Oh, / Sung Dae Suk, / Yong Kyu Lee, / Suk Kang Sung, / Jung-Dong Choe, / Sung-Young Lee, / Dong Uk Choi, / Kyoung Hwan Yeo, / Min Sang Kim, / Sung-Min Kim, et al. | 2004
- 893
-
36.6 Damascene Gate FinFET SONOS Memory Implemented on Bulk Silicon WaferOh, C. W. / Suk, S. D. / Lee, Y. K. / Sung, S. K. / Choe, J. D. / Lee, S. Y. / Choi, D. U. / Yeo, K. H. / Kim, M. S. / Kim, S. M. et al. | 2004
- 897
-
36.7 Impact of Stoichiometry Control in Double Junction Memory on Future ScalingOhba, R. / Mitani, Y. / Sugiyama, N. / Fujita, S. / IEEE et al. | 2004
- 897
-
Impact of stoichiometry control in double junction memory on future scalingOhba, R. / Mitani, Y. / Sugiyama, N. / Fujita, S. et al. | 2004
- 901
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Session 37 - Solid State Devices Emerging Memories| 2004