Delay partitioning helps reducing variability in 3DVLSI (Englisch)
- Neue Suche nach: Ayres, A.
- Neue Suche nach: Rozeau, O.
- Neue Suche nach: Borot, B.
- Neue Suche nach: Fesquet, L.
- Neue Suche nach: Vinet, M.
- Neue Suche nach: Ayres, A.
- Neue Suche nach: Rozeau, O.
- Neue Suche nach: Borot, B.
- Neue Suche nach: Fesquet, L.
- Neue Suche nach: Vinet, M.
In:
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
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75-78
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2016
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ISBN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Delay partitioning helps reducing variability in 3DVLSI
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Beteiligte:Ayres, A. ( Autor:in ) / Rozeau, O. ( Autor:in ) / Borot, B. ( Autor:in ) / Fesquet, L. ( Autor:in ) / Vinet, M. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.09.2016
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Format / Umfang:3407505 byte
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Author index| 2016
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Table of contents| 2016
- 1
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At the core of system scalingYeric, Greg et al. | 2016
- 3
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Ultra-low energy systems: Analog to informationBahai, Ahmad et al. | 2016
- 7
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Neuromorophic vision sensing and processingDelbruckl, Tobi et al. | 2016
- 15
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Polymer Microwave Fibers: A blend of RF, copper and optical communicationReynaert, Patrick / Tytgat, Maarten / Volkaerts, Wouter / Standaert, Alexander / Zhang, Yang / De Wit, Maxime / Van Thienen, Niels et al. | 2016
- 21
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5G and the future of IoTFettweis, Gerhard P. et al. | 2016
- 25
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IoT: The era of LPWAN is starting nowBardyn, Jean-Paul / Melly, Thierry / Seller, Olivier / Sornin, Nicolas et al. | 2016
- 31
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WSN for Machine Area Network applicationsLu, Xiaolin / Kim, Il Han / Xhafa, Ariton / Zhou, Jianwei et al. | 2016
- 37
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30% static power improvement on ARM Cortex®-A53 using static biasing-anticipationAbouzeid, Fady / Bernicot, Christophe / Clerc, Sylvain / Daveau, Jean-Marc / Gasiot, Gilles / Noblet, Daniel / Soussan, Dimitri / Roche, Philippe et al. | 2016
- 41
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Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operationPons, Marc / Le, Thanh-Chau / Arm, Claude / Severac, Daniel / Nagel, Jean-Luc / Morgan, Marc / Emery, Stephane et al. | 2016
- 45
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A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logicPatel, Harsh N. / Roy, Abhishek / Yahya, Farah B. / Liu, Ningxi / Calhoun, Benton / Kumeno, Kazuyuki / Yasuda, Makoto / Harada, Akihiko / Ema, Taiji et al. | 2016
- 49
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Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approachPahwa, Girish / Dutta, Tapas / Agarwal, Amit / Chauhan, Yogesh Singh et al. | 2016
- 55
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Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspectiveAgarwal, Tarun / Radu, Iuliana / Raghavan, Praveen / Fiori, Gianluca / Thean, Aaron / Heyns, Marc / Dehaene, Wim et al. | 2016
- 59
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Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gatesAyala, Christopher L. / Bazigos, Antonios / Grogg, Daniel / Drechsler, Ute / Hagleitner, Christoph et al. | 2016
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A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic systemAamir, Syed Ahmed / Muller, Paul / Hartel, Andreas / Schemmel, Johannes / Meier, Karlheinz et al. | 2016
- 75
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Delay partitioning helps reducing variability in 3DVLSIAyres, A. / Rozeau, O. / Borot, B. / Fesquet, L. / Vinet, M. et al. | 2016
- 79
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History, present state-of-art and future of incremental ADCsChen, Chia-Hung / Zhang, Yi / Temes, Gabor C. et al. | 2016
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A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applicationsGuo, Wenjuan / Sun, Nan et al. | 2016
- 95
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Energy performance of nonvolatile power-gating SRAM using SOTB technologyShuto, Yusuke / Yamamoto, Shuu'ichirou / Sugahara, Satoshi et al. | 2016
- 99
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Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's diseaseMasu, Kazuya / Yamane, Daisuke / Machida, Katsuyuki / Sone, Masato / Miyake, Yoshihiro et al. | 2016
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A 0.9–1.2V supplied, 2.4GHz Bluetooth Low Energy 4.0/4.2 and 802.15.4 transceiver SoC optimized for battery lifeWang, Xiaoyan / Van den Heuvel, Johan / van Schaik, Gert-Jan / Lu, Chuang / He, Yuming / Ba, Ao / Busze, Benjamin / Ding, Ming / Liu, Yao-Hong / Winkel, Nick et al. | 2016
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A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cyclingThirunarayanan, Raghavasimhan / Ruffieux, David / Scolari, Nicola / Enz, Christian et al. | 2016
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An energy harvested ultra-low power transceiver for Internet of Medical ThingsRajavi, Yashar / Taghivand, Mazhareddin / Aggarwal, Kamal / Ma, Andrew / Poon, Ada S. Y. et al. | 2016
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A 433 MHz 54 µW OOK/FSK/PSK compatible wake-up receiver with 11 µW low-power mode based on injection-locked oscillatorChen, Shih-En / Cheng, Kuang-Wei et al. | 2016
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A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverterMiki, Takuji / Miura, Noriyuki / Mizuta, Kento / Dosho, Shiro / Nagata, Makoto et al. | 2016
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A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOISourikopoulos, Ilias / Frappe, Antoine / Cathelin, Andreia / Clavier, Laurent / Kaiser, Andreas et al. | 2016
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- 153
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A ΣΔ sense chain using chopped integrators for ultra-low-noise MEMS systemFraisse, Christian / Nagari, Angelo et al. | 2016
- 157
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A 82nW chaotic-map true random number generator based on sub-ranging SAR ADCKim, Minseo / Ha, Unsoo / Lee, Yongsu / Lee, Kyuho / Yoo, Hoi-Jun et al. | 2016
- 161
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Data converter reflections: 19 papers from the last ten years that deserve a second lookRobertson, David / Buchwald, Aaron / Flynn, Michael / Lee, Hae-Seung / Moon, Un-Ku / Murmann, Boris et al. | 2016
- 165
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A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBBKumar, Ashish / Debnath, Chandrajit / Singh, Pratap Narayan / Bhatia, Vivek / Chaudhary, Shivani / Jain, Vigyan / Le Tual, Stephane / Malik, Rakesh et al. | 2016
- 169
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A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reductionZhong, Jianyu / Zhu, Yan / Chan, Chi-Hang / Sin, Sai-Weng / U, Seng-Pan / Martins, R. P. et al. | 2016
- 173
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A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminatorGanta, Saikrishna / Tomasini, Alfredo / Taparia, Ajay / Cho, Taehee / Kulkarni, Mandar / Erdogan, Ozan et al. | 2016
- 177
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A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOIWulff, Carsten / Ytterdal, Trond et al. | 2016
- 181
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A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-useXiao, Xiao / Pratt, Amanda / Niknejad, Ali / Alon, Elad / Nikolic, Borivoje et al. | 2016
- 185
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A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receiversPopuri, Suchendranath / Pasupureddi, Vijaya Sankara Rao / Sturm, Johannes et al. | 2016
- 189
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A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOSSalem, Loai G. / Buckwalter, James F. / Mercier, Patrick P. et al. | 2016
- 193
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A 200–225 GHz SiGe Power Amplifier with peak Psat of 9.6 dBm using wideband power combinationSarmah, Neelanjan / Aufinger, Klaus / Lachner, Rudolf / Pfeiffer, Ullrich R. et al. | 2016
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An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dBYang, Dongsheng / Deng, Wei / Liu, Bangan / Siriburanon, Teerachot / Okada, Kenichi / Matsuzawa, Akira et al. | 2016
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A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOSGrollitsch, Werner / Nonis, Roberto et al. | 2016
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A 2 GHz 3.1 mW type-I digital ring-based PLLXu, Zule / Firdauzi, Anugerah / Miyahara, Masaya / Okada, Kenichi / Matsuzawa, Akira et al. | 2016
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A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noiseWu, Ying / Shahmohammadi, Mina / Chen, Yue / Lu, Ping / Staszewski, Robert Bogdan et al. | 2016
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Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOSHo, Cheng-Ru / Chen, Mike Shuo-Wei et al. | 2016
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An array of fully-integrated quadrature TX/RX NMR field probes for MRI trajectory mappingHandwerker, J. / Eder, M. / Tibiletti, M. / Rasche, V. / Scheffler, K. / Becker, J. / Ortmanns, M. / Anders, J. et al. | 2016
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A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniquesLe-Thai, Ha / Xhakoni, Adi / Gielen, Georges et al. | 2016
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An impedance-tracking battery-less arbitrary-waveform neurostimulator with load-adaptive 20V voltage complianceKassiri, Hossein / Dutta, Gairik / Soltani, Nima / Liu, Chang / Hu, Yu / Genov, Roman et al. | 2016
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A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOSPepin, Eric / Uehlin, John / Micheletti, Daniel / Perlmutter, Steve I. / Rudell, Jacques C. et al. | 2016
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Stimulation artifact rejection in closed-loop, distributed neural interfacesPeterson, Erik J. / Dinsmoor, David A. / Tyler, Dustin J. / Denison, Timothy J. et al. | 2016
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A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation toleranceNarasimman, Neelakantan / Kim, Tony T. et al. | 2016
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A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOSLi, Shaolan / Sun, Nan et al. | 2016
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A multi-mode SC audio ΣΔ Modulator for MEMS microphones with reconfigurable power consumption, noise-shaping order, and DRGrassi, M. / Conso, F. / Rocca, G. / Malcovati, P. / Baschirotto, A. et al. | 2016
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A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adderChen, Zhijie / Miyahara, Masaya / Matsuzawa, Akira et al. | 2016
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A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filterKaneko, Tohru / Kimura, Yuya / Hirose, Koji / Miyahara, Masaya / Matsuzawa, Akira et al. | 2016
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A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOSReyserhove, Hans / Dehaene, Wim et al. | 2016
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DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustmentConstantin, Jeremy / Bonetti, Andrea / Teman, Adam / Muller, Christoph / Schmid, Lorenz / Burg, Andreas et al. | 2016
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FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUsTakeuchi, Kan / Shimada, Masaki / Okagaki, Takeshi / Shibutani, Koji / Nii, Koji / Tsuchiya, Fumio et al. | 2016
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Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoCKeller, Ben / Cochet, Martin / Zimmer, Brian / Lee, Yunsup / Blagojevic, Milovan / Kwak, Jaehwa / Puggelli, Alberto / Bailey, Stevo / Chiu, Pi-Feng / Dabbelt, Palmer et al. | 2016
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A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technologyChae, Kwanyeob / Choi, Jongryun / Yi, Shinyoung / Lee, Won / Joo, Sanghoon / Kim, Hyunhyuck / Yi, Hyungkwon / Nam, Yoonjee / Choi, Jinho / Park, Sanghune et al. | 2016
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Approximate 32-bit floating-point unit design with 53% power-area product reductionCamus, Vincent / Schlachter, Jeremy / Enz, Christian / Gautschi, Michael / Gurkaynak, Frank K. et al. | 2016
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A 1 Tb/s/mm2 inductive-coupling side-by-side chip linkHasegawa, So / Kadomoto, Junichiro / Kosuge, Atsutake / Kuroda, Tadahiro et al. | 2016
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