Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost (Englisch)
- Neue Suche nach: Goel, A.
- Neue Suche nach: Ghosh, S.
- Neue Suche nach: Meterelliyoz, M.
- Neue Suche nach: Parkhurst, J.
- Neue Suche nach: Roy, K.
- Neue Suche nach: Goel, A.
- Neue Suche nach: Ghosh, S.
- Neue Suche nach: Meterelliyoz, M.
- Neue Suche nach: Parkhurst, J.
- Neue Suche nach: Roy, K.
In:
2011 Asian Test Symposium
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486-491
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2011
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ISSN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost
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Beteiligte:Goel, A. ( Autor:in ) / Ghosh, S. ( Autor:in ) / Meterelliyoz, M. ( Autor:in ) / Parkhurst, J. ( Autor:in ) / Roy, K. ( Autor:in )
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Erschienen in:2011 Asian Test Symposium ; 486-491
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.11.2011
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Format / Umfang:1196225 byte
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ISBN:
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ISSN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
- 1
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On Detecting Transition Faults in the Presence of Clock Delay FaultsHigami, Yoshinobu / Takahashi, H. / Kobayashi, S. / Saluja, K. K. et al. | 2011
- 7
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Testing of Clock-Domain Crossing Faults in Multi-core System-on-ChipKarimi, N. / Zhiqiu Kong, / Chakrabarty, K. / Gupta, P. / Patil, S. et al. | 2011
- 15
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On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing TestHyunjin Kim, / Abraham, J. A. et al. | 2011
- 21
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Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-samplingBhatta, D. / Wells, J. W. / Chatterjee, A. et al. | 2011
- 27
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Temperature Dependent Test Scheduling for Multi-core System-on-ChipChunhua Yao, / Saluja, K. K. / Ramanathan, P. et al. | 2011
- 33
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Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage IslandsKavousianos, X. / Chakrabarty, K. / Jain, A. / Parekhji, R. et al. | 2011
- 40
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Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test DataDong Xiang, / Zhen Chen, et al. | 2011
- 46
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Low Power Test-Compression for High Test-Quality and Low Test-Data VolumeTenentes, Vasileios / Kavousianos, X. et al. | 2011
- 54
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Multi-cycle Test with Partial Observation on Scan-Based BIST StructureSato, Y. / Yamaguchi, H. / Matsuzono, M. / Kajihara, S. et al. | 2011
- 60
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SSTKR: Secure and Testable Scan Design through Test Key RandomizationRazzaq, M. A. / Singh, V. / Singh, A. et al. | 2011
- 66
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An Innovative Methodology for Scan Chain Insertion and Analysis at RTLZaourar, L. / Kieffer, Y. / Aktouf, C. et al. | 2011
- 72
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Adaptation of Standard RT Level BIST Architectures for System Level Communication TestingNemati, N. / Navabi, Z. et al. | 2011
- 78
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Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift TestingSinanoglu, O. et al. | 2011
- 84
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Low Power Decompressor and PRPG with Constant Value BroadcastFilipek, M. / Fukui, Y. / Iwata, H. / Mrugalski, G. / Rajski, J. / Takakura, M. / Tyszer, J. et al. | 2011
- 90
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Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-FillingMiyase, K. / Uchinodan, Y. / Enokimoto, K. / Yamato, Y. / Wen, X. / Kajihara, S. / Wu, F. / Dilillo, L. / Bosio, A. / Girard, P. et al. | 2011
- 96
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Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression EnvironmentZhen Chen, / Jia Li, / Dong Xiang, / Yu Huang, et al. | 2011
- 102
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Test Pattern Selection for Defect-Aware TestHigami, Y. / Furutani, H. / Sakai, T. / Kameyama, S. / Takahashi, H. et al. | 2011
- 108
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Efficient SAT-Based Search for Longest Sensitisable PathsSauer, M. / Jie Jiang, / Czutro, A. / Polian, I. / Becker, B. et al. | 2011
- 114
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Mapping Transaction Level Faults to Stuck-At Faults in Communication HardwareJavaheri, F. / Namaki-Shoushtari, M. / Kamranfar, P. / Navabi, Z. et al. | 2011
- 120
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On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD CoverageFang Bao, / Ke Peng, / Chakrabarty, K. / Tehranipoor, M. et al. | 2011
- 126
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Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error RatesCha, J. C. / Gupta, S. K. et al. | 2011
- 136
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsTran, D. A. / Virazel, A. / Bosio, A. / Dilillo, L. / Girard, P. / Pravossoudovitch, S. / Wunderlich, H. et al. | 2011
- 142
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A New Architecture to Cross-Fertilize On-Line and Manufacturing TestingBernardi, P. / Reorda, M. S. et al. | 2011
- 148
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Online Test Macro Scheduling and Assignment in MPSoC DesignKhodabandeloo, B. / Hoseini, S. A. / Taheri, S. / Haghbayan, M. H. / Babaei, M. R. / Navabi, Z. et al. | 2011
- 154
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Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process VariationsNatarajan, J. / Wells, J. / Chatterjee, A. / Singh, A. et al. | 2011
- 161
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An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip MultiprocessorsRodrigues, R. / Kundu, S. et al. | 2011
- 167
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An Efficient 2-Phase Strategy to Achieve High Branch CoveragePrabhu, S. / Hsiao, M. S. / Krishnamoorthy, S. / Lingappan, L. / Gangaram, V. / Grundy, J. et al. | 2011
- 175
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Soft Error Recovery Technique for Multiprocessor SOPCLegat, U. / Biasizzo, A. / Novak, F. et al. | 2011
- 181
-
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoCYuanqing Cheng, / Lei Zhang, / Yinhe Han, / Jun Liu, / Xiaowei Li, et al. | 2011
- 187
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Identification of Defective TSVs in Pre-Bond Testing of 3D ICsNoia, B. / Chakrabarty, K. et al. | 2011
- 195
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A Unified Interconnects Testing Scheme for 3D Integrated CircuitsChih-Yun Pai, / Ruei-Ting Cu, / Bo-Chuan Cheng, / Liang-Bi Chen, / Li, K. S. et al. | 2011
- 201
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Cost-Effective TSV Grouping for Yield Improvement of 3D-ICsYi Zhao, / Khursheed, S. / Al-Hashimi, B. M. et al. | 2011
- 207
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Improved Fault Diagnosis for Reversible CircuitsHongyan Zhang, / Wille, R. / Drechsler, R. et al. | 2011
- 213
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Embedded Test for Highly Accurate Defect LocalizationMumtaz, A. / Imhof, M. E. / Holst, S. / Wunderlich, H-J et al. | 2011
- 219
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On Using Design Partitioning to Reduce Diagnosis Memory FootprintXiaoxin Fan, / Huaxing Tang, / Reddy, S. M. / Wu-Tung Cheng, / Benware, B. et al. | 2011
- 226
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Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty ModuleBhattacharya, G. / Maity, I. / Sikdar, B. K. / Das, B. et al. | 2011
- 232
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Post-Silicon Timing Validation Method Using Path Delay MeasurementsEun Jung Jang, / Jaeyong Chung, / Gattiker, A. / Nassif, S. / Abraham, Jacob A. et al. | 2011
- 238
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Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation TracesKomuravelli, A. / Mitra, S. / Banerjee, A. / Dasgupta, P. et al. | 2011
- 244
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Design of a Test Processor for Asynchronous Chip TestZeidler, S. / Wolf, C. / Krstic, M. / Vater, F. / Kraemer, R. et al. | 2011
- 251
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On Generating Vectors for Accurate Post-Silicon Delay CharacterizationDas, P. / Gupta, S. K. et al. | 2011
- 261
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Predicting Scan Compression IP Configurations for Better QoRSaikia, J. / Notiyath, P. / Kulkarni, S. / Anbalan, A. / Uppuluri, R. / Fernandes, T. / Bhattacharya, P. / Kapur, R. et al. | 2011
- 267
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Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-GatingMoghaddam, E. K. / Rajski, J. / Reddy, S. M. / Janicki, J. et al. | 2011
- 273
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Test Compression Based on Lossy Image EncodingIchihara, H. / Iwamoto, Y. / Yoshikawa, Y. / Inoue, T. et al. | 2011
- 279
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Multiscan-based Test Data Compression Using UBI Dictionary and BitmaskYang Yu, / Gang Xi, / Liyan Qiao, et al. | 2011
- 285
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Diagnostic Test of Robust CircuitsCook, A. / Hellebrand, S. / Indlekofer, T. / Wunderlich, H. et al. | 2011
- 291
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An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay DefectsPo-Juei Chen, / Wei-Li Hsu, / Li, James C.-M / Nan-Hsin Tseng, / Kuo-Yin Chen, / Wei-pin Changchien, / Liu, Charles C. C. et al. | 2011
- 297
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Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic DefectsZhen Chen, / Seth, S. / Dong Xiang, / Bhattacharya, B. B. et al. | 2011
- 303
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Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process VariationsXi Qian, / Singh, A. D. / Chatterjee, A. et al. | 2011
- 311
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A Process Monitor Based Speed Binning and Die Matching AlgorithmChakravarty, S. et al. | 2011
- 317
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Optimized Test Error Detection by Probabilistic Retest Recommendation ModelsKirmse, M. / Petersohn, U. / Paffrath, E. et al. | 2011
- 323
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Adaptive Test Framework for Achieving Target Test Quality at Minimal CostArslan, B. / Orailoglu, A. et al. | 2011
- 329
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A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video ApplicationsYuntan Fang, / Huawei Li, / Xiaowei Li, et al. | 2011
- 335
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Efficient Use of Unused Spare Columns to Improve Memory Error Correcting RateIshaq, U. / Jihun Jung, / Jaehoon Song, / Sungju Park, et al. | 2011
- 341
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New Fault Detection Algorithm for Multi-level Cell Flash MemroiesJaewon Cha, / Ilwoong Kim, / Sungho Kang, et al. | 2011
- 347
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A New Test Paradigm for Semiconductor Memories in the Nano-EraHamdioui, S. / Krishnaswami, V. / Irobi, I. S. / Al-Ars, Z. et al. | 2011
- 353
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On Defect Oriented Testing for Hybrid CMOS/Memristor MemoryHaron, N. Z. / Hamdioui, S. et al. | 2011
- 359
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Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAsBarragan, M. J. / Fiorelli, R. / Leger, G. / Rueda, A. / Huertas, J. L. et al. | 2011
- 365
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On Replacing an RF Test with an Alternative Measurement: Theory and a Case StudySpyronasios, A. / Abdallah, L. / Stratigopoulos, H. / Mir, S. et al. | 2011
- 371
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Test and Diagnosis of Analog Circuits Using Moment Generating FunctionsSindia, S. / Agrawal, V. D. / Singh, V. et al. | 2011
- 377
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Mixed-Signal Fault Equivalence: Search and EvaluationGuerreiro, N. / Santos, M. et al. | 2011
- 383
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Efficient BDD-based Fault Simulation in Presence of Unknown ValuesKochte, M. A. / Kundu, S. / Miyase, K. / Xiaoqing Wen, / Wunderlich, H. et al. | 2011
- 389
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Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process VariationZhong, S. / Khursheed, S. / Al-Hashimi, B. M. / Reddy, S. M. / Chakrabarty, K. et al. | 2011
- 395
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Automation of 3D-DfT InsertionDeutsch, S. / Chickermane, V. / Keller, B. / Mukherjee, S. / Konijnenburg, M. / Marinissen, E. J. / Goel, S. K. et al. | 2011
- 401
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MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data CachesCarlo, S. D. / Gambardella, G. / Indaco, M. / Rolfo, D. / Prinetto, P. et al. | 2011
- 407
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Testing for Parasitic Memory Effect in SRAMsIrobi, S. / Al-Ars, Z. / Hamdioui, S. / Thibeault, C. et al. | 2011
- 413
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Transient Noise Failures in SRAM Cells: Dynamic Noise Margin MetricVatajelu, E. I. / Gómez-Pau, A. / Renovell, M. / Figueras, J. et al. | 2011
- 419
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Fault Diagnosis in Memory BIST Environment with Non-march TestsMrugalski, G. / Pogiel, A. / Mukherjee, N. / Rajski, J. / Tyszer, J. / Urbanek, P. et al. | 2011
- 425
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Characterizing Pattern Dependent Delay Effects in DDR Memory InterfacesGupta, A. / Kumar, A. / Chhabra, M. et al. | 2011
- 432
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Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)Chandra, A. / Saikia, J. / Kapur, R. et al. | 2011
- 438
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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAsKeheng Huang, / Yu Hu, / Xiaowei Li, / Gengxin Hua, / Hongjin Liu, / Bo Liu, et al. | 2011
- 444
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A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA InterconnectsAlmurib, H. A. F. / Kumar, T. N. / Lombardi, F. et al. | 2011
- 451
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Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer BaseChun-Chuan Chi, / Marinissen, E. J. / Goel, S. K. / Cheng-Wen Wu, et al. | 2011
- 457
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Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCsDevanathan, V. R. / Bhavsar, S. / Mehrotra, R. et al. | 2011
- 459
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Failure Analysis and Test Solutions for Low-Power SRAMsZordan, L. B. / Bosio, A. / Dilillo, L. / Girard, P. / Pravossoudovitch, S. / Todri, A. / Virazel, A. / Badereddine, N. et al. | 2011
- 461
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A Robust Solution for Embedded Memory Test and RepairDarbinyan, K. / Harutyunyan, G. / Shoukourian, S. / Vardanian, V. / Zorian, Y. et al. | 2011
- 463
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Nand Flash Memory -- Product Trends, Technology Overview, and Technical Challengesd'Abreu, Manuel A. et al. | 2011
- 464
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High Level Verification and Its Use at Pos-Silicon Debugging and PatchingFujita, M. et al. | 2011
- 470
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3D Specific Systems: Design and CADFranzon, P. D. / Davis, W. R. / Thorolfsson, T. / Melamed, S. et al. | 2011
- 474
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Testing and Design-for-Testability Techniques for 3D Integrated CircuitsNoia, B. / Chakrabarty, K. et al. | 2011
- 480
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Yield Improvement and Test Cost Optimization for 3D Stacked ICsHamdioui, S. / Taouil, M. et al. | 2011
- 486
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Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test CostGoel, A. / Ghosh, S. / Meterelliyoz, M. / Parkhurst, J. / Roy, K. et al. | 2011
- 492
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Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform ProjectOnodera, H. et al. | 2011
- 496
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Reliability: A Cross-Disciplinary and Cross-Layer ApproachWehn, N. et al. | 2011
- 498
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Underdesigned and Opportunistic ComputingGupta, P. / Gupta, R. K. et al. | 2011
- 500
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Power Aware Shift and Capture ATPG Methodology for Low Power DesignsKhullar, S. / Bahl, S. et al. | 2011
- 506
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Power-Aware Test Pattern Generation for At-Speed LOS TestingBosio, A. / Dilillo, L. / Girard, P. / Todri, A. / Virazel, A. / Miyase, K. / Wen, X. et al. | 2011
- 511
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Power Aware Embedded TestXijiang Lin, / Moghaddam, E. / Mukherjee, N. / Nadeau-Dostie, B. / Rajski, J. / Tyszer, J. et al. | 2011
- 517
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Testability of Cryptographic Hardware and Detection of Hardware TrojansMukhopadhyay, D. / Chakraborty, R. S. et al. | 2011
- 525
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Test Scheduling in an IEEE P1687 Environment with Resource and Power ConstraintsZadegan, F. G. / Ingelsson, U. / Asani, G. / Carlsson, G. / Larsson, E. et al. | 2011
- 532
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Automatic SoC Level Test Path Synthesis Based on Partial Functional ModelsTsertov, A. / Ubar, R. / Jutman, A. / Devadze, S. et al. | 2011
- 539
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A Boundary Scan Circuit with Time-to-Digital Converter for Delay TestingYotsuyanagi, H. / Makimoto, H. / Hashizume, M. et al. | 2011
- 545
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Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network TestingGray, C. / Keezer, D. C. / Wang, H. / Bergman, K. et al. | 2011
- 552
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Author index| 2011
- 556
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[Publishers information]| 2011
- C1
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[Front cover]| 2011
- i
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[Title page i]| 2011
- iii
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[Title page iii]| 2011
- iv
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[Copyright notice]| 2011
- v
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Table of contents| 2011
- xix
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Steering Committee| 2011
- xvi
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Organizing Committee| 2011
- xvii
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Program Committee| 2011
- xx
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Reviewers| 2011