Advantages and challenges of high performance CMOS on SOI (Englisch)
- Neue Suche nach: Pelella, M.M.
- Neue Suche nach: Maszara, W.
- Neue Suche nach: Sundararajan, S.
- Neue Suche nach: Sinha, S.
- Neue Suche nach: Wei, A.
- Neue Suche nach: Ju, D.
- Neue Suche nach: En, W.
- Neue Suche nach: Krishnan, S.
- Neue Suche nach: Chan, D.
- Neue Suche nach: Chan, S.
- Neue Suche nach: Yeh, P.
- Neue Suche nach: Lee, M.
- Neue Suche nach: Wu, D.
- Neue Suche nach: Fuselier, M.
- Neue Suche nach: vanBentum, R.
- Neue Suche nach: Burbach, G.
- Neue Suche nach: Lee, C.
- Neue Suche nach: Hill, G.
- Neue Suche nach: Greenlaw, D.
- Neue Suche nach: Riccobenc, C.
- Neue Suche nach: Karlsson, O.
- Neue Suche nach: Wristers, D.
- Neue Suche nach: Kepler, N.
- Neue Suche nach: Pelella, M.M.
- Neue Suche nach: Maszara, W.
- Neue Suche nach: Sundararajan, S.
- Neue Suche nach: Sinha, S.
- Neue Suche nach: Wei, A.
- Neue Suche nach: Ju, D.
- Neue Suche nach: En, W.
- Neue Suche nach: Krishnan, S.
- Neue Suche nach: Chan, D.
- Neue Suche nach: Chan, S.
- Neue Suche nach: Yeh, P.
- Neue Suche nach: Lee, M.
- Neue Suche nach: Wu, D.
- Neue Suche nach: Fuselier, M.
- Neue Suche nach: vanBentum, R.
- Neue Suche nach: Burbach, G.
- Neue Suche nach: Lee, C.
- Neue Suche nach: Hill, G.
- Neue Suche nach: Greenlaw, D.
- Neue Suche nach: Riccobenc, C.
- Neue Suche nach: Karlsson, O.
- Neue Suche nach: Wristers, D.
- Neue Suche nach: Kepler, N.
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Advantages and challenges of high performance CMOS on SOI
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Beteiligte:Pelella, M.M. ( Autor:in ) / Maszara, W. ( Autor:in ) / Sundararajan, S. ( Autor:in ) / Sinha, S. ( Autor:in ) / Wei, A. ( Autor:in ) / Ju, D. ( Autor:in ) / En, W. ( Autor:in ) / Krishnan, S. ( Autor:in ) / Chan, D. ( Autor:in ) / Chan, S. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.2001
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Format / Umfang:515964 byte
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ISBN:
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ISSN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)| 2001
- 1
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Advantages and Challenges of High Performance Logic on SOIPelella, M. / Maszara, W. / Sundararajan, S. / Sinha, S. / Wei, A. / Ju, D. / En, W. / Krishnan, S. / Chan, D. / Chan, S. et al. | 2001
- 1
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Advantages and challenges of high performance CMOS on SOIPelella, M.M. / Maszara, W. / Sundararajan, S. / Sinha, S. / Wei, A. / Ju, D. / En, W. / Krishnan, S. / Chan, D. / Chan, S. et al. | 2001
- 5
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Technology and Status of SOI MaterialsAllen, L. / Skinner, W. / Cate, A. / IEEE et al. | 2001
- 5
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Status and technology of SOI substrate materialAllen, L.P. / Skinner, W. / Cate, A. et al. | 2001
- 8
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Nano-Scale Solicon MOSFET: Towards Non-Traditional and Quantum DevicesHiramoto, T. / IEEE et al. | 2001
- 8
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Nano-scale silicon MOSFET: towards non-traditional and quantum devicesHiramoto, T. et al. | 2001
- 11
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Atomic-layer Cleaving with Si~x Ge~y Strain Layers for Fabrication of Si and Ge-rich SOI Device LayersCurrent, M. I. / Farrens, S. N. / Fuerfanger, M. / Kang, S. / Kirk, H. R. / Malik, I. J. / Feng, L. / Henley, F. J. / IEEE et al. | 2001
- 11
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Atomic-layer cleaving with Si/sub x/Ge/sub y/ strain layers for fabrication of Si and Ge-rich SOI device layersCurrent, M.I. / Farrens, S.N. / Fuerfanger, M. / Sien Kang, / Kirk, H.R. / Malik, I.J. / Feng, L. / Henley, F.J. et al. | 2001
- 13
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SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluationZhi-Yuan Cheng, / Currie, M.T. / Leitz, C.W. / Taraschi, G. / Pitera, A. / Lee, M.L. / Langdo, T.A. / Hoyt, J.L. / Antoniadis, D.A. / Fitzgerald, E.A. et al. | 2001
- 15
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BOX layer formation by oxygen precipitation at implantation damage of light ionsOgura, A. et al. | 2001
- 17
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Application of laser scattering and optical defect detection methods to SIMOX-SOI wafersAlles, M. / Dunne, J. / Treadwell, C. / Fiordalice, B. / Nguyen, R. et al. | 2001
- 19
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Defect detection on SOI wafers using laser scattering toolsMaleville, C. / Neyret, E. / Ecarnot, L. / Barge, T. / Auberton, A.J. et al. | 2001
- 21
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Design analysis of thin-body silicide source/drain devicesKedzierski, J. / MeiKei Ieong, / Peiqi Xuan, / Bokor, J. / Tsu-Jae King, / Chenming Hu, et al. | 2001
- 23
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0.11 /spl mu/m fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible processKomatsu, H. / Nakayama, H. / Koyama, K. / Matsumoto, K. / Ohno, T. / Takeshita, K. et al. | 2001
- 23
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0.11 mum Fully-Depleted SOI CMOS Devices with 26nm Silicon Layer Fabricated by Bulk Compatible ProcessKomatsu, H. / Nakayama, H. / Koyama, K. / Matsumoto, K. / Ohno, T. / Takeshita, K. / IEEE et al. | 2001
- 25
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Explaining the reduced floating body effects in narrow channel SOI MOSFETsPretet, J. / Subba, N. / Ioannou, D. / Cristoloveanu, S. / Maszara, W. / Raynaud, C. et al. | 2001
- 27
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f/sub T/ variation caused by channel width effects in ladder gate structure for RF SOI MOSFETsHyeokjae Lee, / Jono-Ho Lee, / Young June Park, / Hong Shick Min, et al. | 2001
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f~T Variation Caused by Channel Width Effects in Ladder Gate Structure for RF SOI MOSFETsLee, H. / Lee, J.-H. / Park, Y. J. / Min, H. S. / IEEE et al. | 2001
- 29
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Exploitation of volume inversion in optimal DG MOSFET designGe, L. / Fossum, J.G. et al. | 2001
- 31
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Self-heating enhanced impact ionization in SOI MOSFETsSu, P. / Goto, K. / Sugii, T. / Hu, C. et al. | 2001
- 33
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Comparison of boron diffusion profiles in ultra thin SOI structuresUchida, H. / Ichimura, M. / Arai, E. et al. | 2001
- 35
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Gas cluster ion beam processing of SOI surfaces for improved gate oxide integrityAllen, L.P. / Hautala, J. / Santeufemio, C. / Brooks, W. / Fenner, D.B. / Lucking, T. / Liu, M. et al. | 2001
- 37
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Characterization of SOI wafers by temporal decay measurement of condensate luminescenceIbuka, S. / Tajima, M. et al. | 2001
- 39
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FTIR dosimetry mapping of as-implanted SIMOX wafersYakovlev, V.A. / Rosenthal, P.A. / Anc, M.J. et al. | 2001
- 41
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New implant equipment for the production of commercial SOI substratesWhite, N.R. / Sieradzki, M. / Bell, E.W. et al. | 2001
- 43
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Effect of implant dose and energy on formation of thin SOI structure in SIMOX using water plasmaJing Chen, / Meng Chen, / Xiang Wang, / Yemin Dong, / Zhihong Zheng, / Xi Wang, et al. | 2001
- 45
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Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applicationsvan Meer, H. / De Meyer, K. et al. | 2001
- 47
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Recessed multi-gate SOI MOSFET in deep decananometer regimeJvi-Tsong Lin, / Shih-chang Chang, / Kuo-ying Huang, / Yan-Youg Xu, / Ping-Shin Jue, et al. | 2001
- 47
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Recessed Multi-Gate SOI MOSFET in Deep Decanonometer RegimeLin, J.-T. / Chang, S.-C. / Huang, K.-Y. / Xu, Y.-Y. / Jue, P.-S. / IEEE et al. | 2001
- 49
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Simulations of ultrathin SOI with quantum transport modelsLyumkis, E. / Mickevicius, R. / Penzin, O. / Polsky, B. / El Sayed, K. / Wettstein, A. et al. | 2001
- 51
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Phenomenalistic reconsideration of Hooge parameter in buried-channel metal-oxide-semiconductor field-effect transistorsOmura, Y. et al. | 2001
- 53
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Threshold voltage fluctuation analysis in dynamic threshold MOSFET based on charge-sharingTerauchi, M. et al. | 2001
- 55
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80nm SOI CMOS parameter extraction for BSIMPDGoto, K. / Su, P. / Tagawa, Y. / Sugii, T. / Hu, C. et al. | 2001
- 57
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Measurement of history effect in PD/SOI single-ended CPL circuitJenkins, K.A. / Puri, R. / Chuang, C.T. / Pesavento, F.L. et al. | 2001
- 59
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Multiple output domino logic (MODL) in SOIKanj, R. / Rosenbaum, E. et al. | 2001
- 61
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Implementation of a multi-bit /spl utri//spl Sigma/ A/DC without a correction RAMChia-Ming Liu, / Soon Guan Lim, / Hutchens, C. / Lagnado, I. et al. | 2001
- 61
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Implementation of a Multi-Bit DeltaSigma A/DC Without a Correction RAMLiu, C.-M. / Lim, S. G. / Hutchens, C. / Lagnado, I. / IEEE et al. | 2001
- 63
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Novel 0.8 V true-single-phase-clocking (TSPC) latches using PD-SOI DTMOS techniques for low-voltage CMOS VLSI circuitsKuo, J.B. / Tai-Yi Chiang, et al. | 2001
- 65
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5+ GHz CMOS prescalerFleming Lam, / Wu, G. et al. | 2001
- 67
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High resistive ELTRAN/sup (R)/ SOI-Epi/sup TM/ wafers for RF applicationSato, N. / Nakayama, J. / Ohmi, K. / Yonehara, T. et al. | 2001
- 67
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High Resistive ELTRAN® SOI-Epi™ Wafers for RF ApplicationSato, N. / Nakayama, J. / Ohmi, K. / Yonehara, T. / IEEE et al. | 2001
- 69
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A parallel between silicon splitting kinetics study and IR absorption analysisLagahe, C. / Aspar, B. / Moriceau, H. / Soubie, A. / Barge, T. et al. | 2001
- 71
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Partial trench isolated body-tied (PTIBT) structure for SOI applicationsMin, B.W. / Dakshina-Murthy, S. / Mendicino, M. et al. | 2001
- 73
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Fabrication & characterization of Schottky junction transistorsWu, Z. / Spann, J. / Jaconelli, P.C. / Jinman Yang, / Thornton, T.J. et al. | 2001
- 75
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A Picosecond Photodetector on SOI Structures for 0.4mum BandOhsawa, J. / Misaki, T. / Ibaragi, T. / IEEE et al. | 2001
- 75
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A picosecond photodetector on SOI structures for 0.4 /spl mu/m bandOhsawa, J. / Misaki, T. / Ibaragi, T. et al. | 2001
- 77
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A novel five-channel NMOSFET using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)Haitao Liu, / Kumar, M. / Sin, J.K.O. / Wan Jun, / Wang, K.L. et al. | 2001
- 79
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300 Mbps level converters for 0.5 V system LSIs using FD/PD-SOI technologyFuse, T. / Tokumasu, M. / Ohta, M. / Fujii, H. / Kawanaka, S. / Kameyama, A. et al. | 2001
- 81
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Investigation of SOI sensitivity to SEU-Influence of the buried oxide coupling effectColladant, T. / Ferlet-Cavrois, V. / L'Hoir, A. / Baggio, J. / Faynot, O. et al. | 2001
- 83
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A novel shallow trench isolation technology using LPCVD MTO/SiN liner in SOI waferLee, T.J. / Park, D. / Roh, Y.H. / Kim, B.S. / Ahn, D.H. / Kim, E.H. / Jeon, C.H. / Kim, Y.W. / Lee, S.C. / Choi, C.S. et al. | 2001
- 85
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Reduction of STI/active Stress on 0.18mum SOI Devices Through Modifications of STI ProcessEn, W. G. / Ju, D.-H. / Chan, D. / Chan, S. / Karlsson, O. / IEEE et al. | 2001
- 85
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Reduction of STI/active stress on 0.18 /spl mu/m SOI devices through modification of STI processEn, W.G. / Dong-Hyuk Ju, / Darin Chan, / Chan, S. / Karlsson, O. et al. | 2001
- 85
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Reduction of STI/active stress on 0.18 mu m SOI devices through modification of STI processEn, W.G. / Ju, Dong-Hyuk / Chan, Darin / Chan, S. / Karlsson, O. et al. | 2001
- 87
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Characterization and simulation of STI isolation for 0.1 /spl mu/m partially-depleted SOI devicesFenouillet-Beranger, C. / Faynot, O. / Tabone, C. / Colladant, T. / Ferlet, V. / Jahan, C. / du Port de Pontcharra, J. / Lecarval, G. / Pelloie, J.L. et al. | 2001
- 87
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Characterization and Simulation of STI Isolation for 0.1mum Partially-Depleted SOI DevicesFenouillet-Beranger, C. / Faynot, O. / Tabone, C. / Colladant, T. / Ferlet, V. / Jahan, C. / de Pontcharra, J. d. / Lecarval, G. / Pelloie, J. L. / IEEE et al. | 2001
- 89
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Ar implantation effects in SOI NMOSFET's under low voltage operationShino, T. / Nii, H. / Kawanaka, S. / Inoh, K. / Katsumata, Y. / Yoshimi, M. / Ishiuchi, H. et al. | 2001
- 91
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Metal gates for advanced sub-80-nm SOI CMOS technologyCheng, B. / Maiti, B. / Samavedam, S. / Grant, J. / Taylor, B. / Tobin, P. / Mogab, J. et al. | 2001
- 93
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Double-gate SOI MOSFET fabrication from bulk silicon waferXinnan Lin, / Chuguang Feng, / Shengdong Zhang, / Wai-Hung Ho, / Mansun Chan, et al. | 2001
- 95
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A low-cell-stress SOI SRAM sensing techniqueKuang, J.B. / Assaderaghi, F. / Aipperspach, A.G. / Christensen, T.A. et al. | 2001
- 97
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0.15 /spl mu/m SOI DRAM technology incorporating sub-volt dynamic threshold devices for embedded mixed-signal & RF circuitsGoldman, D. / DeGregorio, K. / Kim, C.S. / Nielson, M. / Zahurak, J. / Parke, S. et al. | 2001
- 97
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0.15um SOI DRAM Technology Incorporating Sub-Volt Dynamic Threshold Devices for Embedded Mixed-Signal & RF CircuitsGoldman, D. / DeGregorio, K. / Kim, C. S. / Nielson, M. / Zahurak, J. / Parke, S. / IEEE et al. | 2001
- 99
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Novel circuits to improve SRAM performance in PD/SOI technologyJoshi, R.V. / Bhavnagarwala, A. / Hsu, L.L. / Chuang, C.T. / Hwang, W. et al. | 2001
- 101
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Assessing Circuit Level Impact of Self-Heating in 0.13mum SOI CMOSSinha, S. P. / Pelella, M. / Tretz, C. / Riccobene, C. / IEEE et al. | 2001
- 101
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Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOSSinha, S.P. / Pelella, M. / Tretz, C. / Riccobene, C. et al. | 2001
- 103
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Circuit Style Comparison Based on the Variable Voltage Transfer Characteristic and Floating beta Ratio Concept of Partially Depleted SOIDas, K. K. / Brown, R. / IEEE et al. | 2001
- 103
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Circuit style comparison based on the variable voltage transfer characteristic and floating /spl beta/ ratio concept of partially depleted SOIDas, K.K. / Brown, R.B. et al. | 2001
- 105
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Layout Optimization of Cascode RF SOI TransitorsMarenk, M. / Ristolainen, E. / IEEE et al. | 2001
- 105
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Layout optimization of cascode RF SOI transistorsMarenk, M. / Ristolainen, E. et al. | 2001
- 107
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New Substrate-Crosstalk Reduction Structure Using SOI SubstrateHiraoka, Y. / Matsumoto, S. / Sakai, T. / IEEE et al. | 2001
- 107
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New substrate-crosstalk reduction structure using SOI substrate [for one-chip transceiver IC]Hiraoka, Y. / Matsumoto, S. / Sakai, T. et al. | 2001
- 109
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Lateral gate-all-around (GAA) poly-Si transistorsKalavade, P. / Saraswat, K.C. et al. | 2001
- 109
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Lateral Gate-All-Around (GAA) poly-Se TransistorsKalavade, P. / Saraswat, K. C. / IEEE et al. | 2001
- 111
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Quasi-planar FinFETs with selectively grown germanium raised source/drainLindert, N. / Choi, Y.-K. / Chang, L. / Anderson, E. / Lee, W.-C. / King, T.-J. / Bokor, J. / Hu, C. et al. | 2001
- 113
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Characterization of fully depleted SOI transistors after removal of the silicon substrateBurns, J. / Warner, K. / Gouker, P. et al. | 2001
- 115
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Comparison of gate structures for short-channel SOI MOSFETsPark, J.-T. / Colinge, C.A. / Colinge, J.-P. et al. | 2001
- 117
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Multi-layers with buried structures (MLBS): an approach to three-dimensional integrationLei Xue, / Liu, C.C. / Tiwari, S. et al. | 2001
- 119
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Single-mode silicon optical switch with T-shape SiO/sub 2/ waveguide as a control gateIida, Y. / Omura, Y. / Kobayashi, H. et al. | 2001
- 119
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Single-Mode Silicon Optical Switch with T-shape SiO2 Waveguide as a ControlIida, Y. / Omura, Y. / Kobayashi, H. / IEEE et al. | 2001
- 121
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Worst case conditions for hot-carrier induced degradation of sub-100 nm partially depleted SOI MOSFET'sEugene-Xuejun Zhao, / Sinha, S.P. / Dong-Hyuk Ju, et al. | 2001
- 123
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The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETsDieudonne, F. / Jomaah, J. / Ioannou, D. / Raynaud, C. / Balestra, F. et al. | 2001
- 125
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Radiation induced degradation of SOI n-channel LDMOSFETsConley, J.F. / Vandooren, A. / Reiner, L. / Cristoloveanu, S. / Mojarradi, M. / Kolowa, E. et al. | 2001
- 127
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Modeling the gated-diode response of an irradiated SOI back-channel interfaceLawrence, R.K. / Salman, A.A. / Ioannou, D.E. / Jenkins, W.C. / Liu, S.T. et al. | 2001
- 129
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Study of relevance of the SIMOX defect type on yield of radiation-tolerant device test structuresAnc, M.J. / Allen, L.P. / Alles, M.L. / Dolan, R.P. / Liu, S.T. / Sullwold, J.G. / Gostein, M. / Banet, M. et al. | 2001
- 131
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Evaluating manufacturability of radiation-hardened SOI substratesAlles, M. / Dolan, B. / Hughes, H. / McMarr, P. / Gouker, P. / Liu, M. et al. | 2001
- 133
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Comparison of bulk vs SOI for low power low voltage CMOS imagerAfzalian, A. / Delatte, P. / Legat, J.-D. / Flandre, D. et al. | 2001
- 135
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A tri-state body charge modulated SOI sense amplifierKuang, J.B. / Chuang, C.T. et al. | 2001
- 137
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A novel CMOS SOI unbalanced Mach-Zehnder interferometer: from design and simulations to fabrication and characterizationDainesi, P. / Thevenaz, L. / Fluckiger, Ph. / Hibert, C. / Racine, G. / Robert, Ph. / Renaud, Ph. / Ionescu, A.M. / Declercq, M. et al. | 2001
- 139
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Design of a SOI fully integrated 1 V, 2.5 GHz front-end receiverTinella, C. / Fournier, J.M. et al. | 2001
- 141
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Characteristics of RF power amplifiers by 0.5 /spl mu/m SOS CMOS processSang Lam, / Wing-Hung Ki, / Mansun Chan, et al. | 2001
- 141
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Characteristics of RF Power Amplifiers by 0.5mum SOS CMOS ProcessLam, S. / Ki, W.-H. / Chan, M. / IEEE et al. | 2001
- 143
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A 0.5-1 V MTCMOS/SIMOX ROM macro with low-V/sub th/ memory cellsDouseki, T. / Shibata, N. / Yamada, J. et al. | 2001
- 143
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A 0.5-1V MTCMOS/SIMOX ROM Macro with Low-Vth Memory CellsDouseke, T. / Shibata, N. / Yamada, J. / IEEE et al. | 2001
- 145
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Reconsideration of off-leakage current estimation of sub-100-nm SOI MOSFETs and device selection for applicationsYnagi, S.-I. / Omura, Y. et al. | 2001
- 147
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Enhanced subthreshold leakage current due to impact ionization in deep sub-100nm N-channel double-gate MOSFETsJae-Kwan Park, / Deshpande, H.V. / Woo, J.C.S. et al. | 2001
- 147
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Enhanced Subthreshold Leakage Current due to Impact Ionization in Deep Sub-100mn N-Channel Double-Gate MOSFETsPark, J.-K. / Deshpande, H. / Woo, J. C. S. / IEEE et al. | 2001
- 149
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Double-gate SOI MOSFETs with asymmetrical configurationAllibert, F. / Zaslavsky, A. / Cristoloveanu, S. et al. | 2001
- 151
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Nanoscale SOI ballistic MOSFETs: an impending power crisisSverdlov, V. / Naveh, Y. / Likharev, K. et al. | 2001
- 153
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A SOI capacitor-less 1T-DRAM conceptOkhonin, S. / Nagoga, M. / Sallese, J.M. / Fazan, P. et al. | 2001
- 155
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Unibond SOI Wafers for ultra-thin films applicationsMaleville, C. / Neyret, E. / Ecarnot, L. / Arene, E. / Barge, T. / Auberton, A. J. / IEEE et al. | 2001
- 155
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Unibond(R) SOI wafers for ultra-thin films applicationsMaleville, C. / Neyret, E. / Ecarnot, L. / Arene, E. / Barge, T. / Auberton, A.J. et al. | 2001
- 157
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Author's index| 2001