Advanced modeling of faults in Reversible circuits (Englisch)
- Neue Suche nach: Polian, I
- Neue Suche nach: Hayes, J P
- Neue Suche nach: Polian, I
- Neue Suche nach: Hayes, J P
In:
2010 East-West Design&Test Symposium (EWDTS)
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376-381
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2010
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:Advanced modeling of faults in Reversible circuits
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Beteiligte:Polian, I ( Autor:in ) / Hayes, J P ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.09.2010
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Format / Umfang:842720 byte
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ISBN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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Contents| 2010
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[Copyright notice]| 2010
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[Title page]| 2010
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Authors index| 2010
- 13
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An approach for PSL assertion coverage analysis with high-level decision diagramsJenihhin, Maksim / Raik, Jaan / Ubar, Raimund / Shchenova, Tatjana et al. | 2010
- 17
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Secure communication protocol for wireless sensor networksRossi, D / Omaña, M / Giaffreda, D / Metra, C et al. | 2010
- 21
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Hardware reduction for FSM - Based control units using PAL technologyBarkalov, A / Titarenko, L / Chmielewski, S et al. | 2010
- 25
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SAT-based group method for verification of logical descriptions with functional indeterminacyCheremisinova, Liudmila / Novikov, Dmitry et al. | 2010
- 30
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A process variation detection methodMelikyan, V / Mirzoyan, D / Petrosyan, G et al. | 2010
- 34
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Architecture of queued-free crossbar for on-chip networksAbovyan, S / Petrosyan, G / Harutyunyan, T et al. | 2010
- 37
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Modeling on-chip variations in digital circuits using statistical timing analysisPetrosyan, G / Abovyan, S / Harutyunyan, T et al. | 2010
- 40
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Stable current and voltage generation under process variationMelikyan, V / Karapetyan, S / Mirzoyan, D / Babayan, E et al. | 2010
- 47
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Exploring modeling and testing of NAND flash memoriesDi Carlo, S / Fabiano, M / Piazza, R / Prinetto, P et al. | 2010
- 51
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Coverage method for FPGA fault logic blocks by sparesHahanov, V / Litvinova, E / Gharibi, W / Guz, O et al. | 2010
- 69
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Improving reliability for bit parallel finite field multipliers using Decimal HammingMavrogiannakis, N / Argyrides, C / Pradhan, D K et al. | 2010
- 73
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Microprogram control unit with code sharing and extended microinstruction formatBarkalov, Alexander / Titarenko, Larysa / Bieganowski, Jacek et al. | 2010
- 77
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Testing and verification of HDL-models for SoC componentsHahanov, V / Hahanova, I / Umerah, N C / Yves, T et al. | 2010
- 86
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Fault tolerance of decomposed PLAsKeren, O / Levin, I et al. | 2010
- 92
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Verification of FPGA electronic designs for nuclear reactor trip systems: test- and invariant-based methodsAndrashov, A / Kharchenko, V / Sklyar, V / Reva, L / Dovgopolyi, V / Golovir, V et al. | 2010
- 110
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Vector logic analysis of associative matricesHahanov, V / Gharibi, W / Chumachenko, S / Litvinova, E et al. | 2010
- 118
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Table data structures for cyber spaceHahanov, V / Litvinova, E / Priymak, A et al. | 2010
- 123
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Process models for analyzing associative data structuresHahanov, Vladimir / Guz, Olesya / Umerah, Ngene Christopher / Olhovoy, Vitaliy et al. | 2010
- 127
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A technique to accelerate the Vector Fitting algorithm for interconnect simulationGourary, M M / Rusakov, S G / Ulyanov, S L / Zharov, M M et al. | 2010
- 131
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Frequency domain techniques for simulation of oscillatorsGourary, M M / Rusakov, S G / Stempkovsky, A L / Ulyanov, S L / Zharov, M M et al. | 2010
- 141
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Generalized faulty block model for automatic test pattern generationPodyablonsky, F / Kascheev, N et al. | 2010
- 145
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A technique of optimal built-in self-test circuitries generationChebykina, N V / Mosin, S G et al. | 2010
- 152
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GA-based and design by contract approach to test generation for EFSMsZakonov, A / Stepanov, O / Shalyto, A et al. | 2010
- 156
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Implementation of a new paradigm in design of IIR digital filtersLesnikov, V A / Naumovich, T V / Chastikov, A V / Armishev, S V et al. | 2010
- 160
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PDFs testing of combinational circuits based on covering ROBDDsMatrosova, A / Nikolaeva, E et al. | 2010
- 164
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Path delay faults and ENFMatrosova, A / Lipsky, V / Melnikov, A / Singh, V et al. | 2010
- 179
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On-chip measurements of standard-cell propagation delayChurayev, S O / Matkarimov, B T / Paltashev, T T et al. | 2010
- 183
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FPGA FFT implementationChurayev, S O / Matkarimov, B T et al. | 2010
- 195
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Reconfiguration and hardware agents in testing and repair of distributed systemsMoiş, G / Ştefan, I / Enyedi, Sz / Miclea, L et al. | 2010
- 204
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Metrics of vector logic algebra for cyber spaceHahanov, V / Mishchenko, A / Varetsa, V et al. | 2010
- 208
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Cyber space evolutionHahanov, V / Hahanova, A / Zakaryan, V et al. | 2010
- 215
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Logical method for detecting faults by fault detection tableHahanov, V / Pobizhenko, I / Yves, T et al. | 2010
- 218
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EDACs and test integration strategies for NAND flash memoriesDi Carlo, Stefano / Fabiano, Michele / Piazza, Roberto / Prinetto, Paolo et al. | 2010
- 222
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Communication interface synthesis from TLM 2.0 to RTLHatami, Nadereh / Indaco, Marco / Prinetto, Paolo / Tiotto, Gabrielle et al. | 2010
- 226
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Sign Language synthesis using hand motion acquisitionHatami, N / Prinetto, P / Tiotto, G et al. | 2010
- 236
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Engineering-maintenance methods of the calculation xDSL-linesPanteleev, V V / Vakaruk, A I et al. | 2010
- 242
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Common-mode signal minimization in differential stageKrutchinsky, S G / Tsibin, M S / Titov, A E et al. | 2010
- 254
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Adaptive array based on “Multicore” DSP family and Linearly Constrained constant modulus IQRD RLS algorithmPletneva, I D / Djigan, V I et al. | 2010
- 264
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Internal structure of software application for controlling devices via JTAG 1149 interfaceIlyin, I / Grushvitsky, R et al. | 2010
- 267
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Straight edge extraction and localization on noisy imagesVolkov, V / Germer, R / Oneshko, A / Oralov, D et al. | 2010
- 274
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Quantization step dispersion of direct transformation ADCGritsutenko, S S / Panyukov, A G et al. | 2010
- 278
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Blind carrier frequency offset estimation for QAM signals based on weighted 4th power of signal samplesSergienko, A B / Petrov, A V et al. | 2010
- 282
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A new paradigm in design of IIR digital filtersLesnikov, Vladislav A / Naumovich, Tatiana V / Chastikov, Alexander V / Armishev, Sergey V et al. | 2010
- 289
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Two-criterial DSSS synchronization method efficiency researchKharchenko, H V / Tkalich, I O / Vdovychenko, Y I et al. | 2010
- 300
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Dynamic characteristics of different system design strategiesZemliak, A / Torres, M / Reyes, F / Vergara, S / Markina, T et al. | 2010
- 310
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An efficient March test for detection of all two-operation dynamic faults from subclass SavAvetisyan, H / Harutyunyan, G / Vardanian, V A / Zorian, Y et al. | 2010
- 315
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Component architecture with runtime type definitionGrinkrug, E M / Shakurov, A R et al. | 2010
- 319
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New method of multi-level optimizationAsadov, H H / Aliyeva, Y N / Bayramova, L A / Ismailov, K K et al. | 2010
- 322
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Utilization of variation optimization for location of emitter of random noise signalAsadov, H H / Abdullayev, N A / Kerimov, M J / Dadashov, E F et al. | 2010
- 326
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Optimization of information - Measuring systems of non-stationary operational regime in multiple measurements modeAsadov, H H / Abdullayev, N A / Agayev, I Kh / Nabiyev, N A / Rajabli, R T et al. | 2010
- 328
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On possibility of stabilizing results for multicriteria optimizing linear combination of concurrent functionalsAsadov, H H / Abdullayev, N A / Jalilov, S B / Nabiyev, N A / Javadov, N H et al. | 2010
- 330
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FREP: A soft error resilient pipelined RISC architectureKumar, V / Choudhary, R R / Singh, V et al. | 2010
- 339
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Cluster computing framework based on transparent parallelizing technologyPavlenko, Vitalij / Burdeinyi, Viktor et al. | 2010
- 343
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Thermal aware test scheduling for stacked multi-chip-modulesVinay, N S / Rawaty, I / Larssonz, E / Gaurx, M S / Singh, V et al. | 2010
- 350
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Fault grading using Instruction-Execution graphVinutha, K R / Singh, Virendra / Matrosova, Anzhela / Gaur, M S et al. | 2010
- 362
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Internet applications testing automation through probabilistic-network programmingBykau, A A / Piletsky, I I et al. | 2010
- 366
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Methodology of algorithms synthesis of storage devices test diagnosingAlmadi, M / Moamar, D / Ryabtsev, V et al. | 2010
- 371
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Building of the logic network of the information area of the corporationKhairova, N / Sharonova, N et al. | 2010
- 374
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Development of the data-driven readout ASIC for microstrip detectorsAtkin, E / Volkov, Yu / Klyuev, A / Shumihin, V et al. | 2010
- 376
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Advanced modeling of faults in Reversible circuitsPolian, I / Hayes, J P et al. | 2010
- 382
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Use of predicate categories for modelling of operation of the semantic analyzer of the linguistic processorKhairova, N / Sharonova, N et al. | 2010
- 386
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Increase in reliability of on-line testing methods using natural time redundancyDrozd, A / Antoshchuk, S / Martinuk, A / Drozd, J et al. | 2010
- 390
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Reduction in the number of PAL macrocells for Moore FSM implemented with CPLDBarkalov, A / Titarenko, L / Chmielewski, S et al. | 2010
- 395
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ESL design methodology for architecture explorationJavaheri, F / Navabi, Z et al. | 2010
- 402
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A TLM2.0 assertion library with centralized monitoring approachGhofrani, AmirAli / Abolma'ali, Sheis / Haghi, Zahra Najafi / Navabi, Zainalabedin et al. | 2010
- 407
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Schematic protection method from influence of total ionization dose effects on threshold voltage of MOS transistorsMelikyan, Vazgen / Hovsepyan, Aristakes / Harutyunyan, Tigran et al. | 2010
- 412
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Virtual tester development using HDL/PLIKamran, Arezoo / Nemati, Nastaran / Kohan, Somayeh Sadeghi / Navabi, Zainalabedin et al. | 2010
- 416
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Merit based directed random test generation (MDRTG) scheme for combinational circuitsKamran, Arezoo / Jahangiry, Mohammad Saeed / Navabi, Zainalabedin et al. | 2010
- 420
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Near optimal machine learning based random test generationShakeri, Niki / Nemati, Nastaran / Ahmadabadi, Majid Nili / Navabi, Z et al. | 2010
- 425
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Security risks in hardware: Implementation and detection problemAdamov, Alexander / Hahanov, Vladimir et al. | 2010
- 428
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Facilitating testability of TLM FIFO: SystemC implementationsAlemzadeh, H / Cimei, M / Prinetto, P / Navabi, Z et al. | 2010
- 431
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Code optimization for enhancing SystemC simulation timeAlemzadeh, H / Aminzadeh, S / Saberi, R / Navabi, Z et al. | 2010
- 434
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5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technologyMelikyan, V / Sahakyan, K / Nazaryan, A et al. | 2010
- 438
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Hardware description language based on message passing and implicit pipeliningBoulytchev, Dmitri / Medvedev, Oleg et al. | 2010
- 442
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Between standard cells and transistors: Layout templates for Regular FabricsTalalay, M / Trushin, K / Venger, O et al. | 2010
- 449
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The problem of Trojan inclusions in software and hardwareAdamov, A / Saprykin, A et al. | 2010
- 452
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Parameterized IP Infrastructures for fault-tolerant FPGA-based systems: Development, assessment, case-studyVitaliy, Kulanov / Vyacheslav, Kharchenko / Artem, Perepelitsyn et al. | 2010
- 456
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Generating test patterns for sequential circuits using random patterns by PLI functionsHaghbayan, M H / Yazdanpanah, A / Karamati, S / Saeedi, R / Navabi, Z et al. | 2010
- 461
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Low cost error tolerant motion estimation for H.264/AVC standardSargolzaie, M H / Semsarzadeh, M / Hashemi, M R / Navabi, Z et al. | 2010
- 468
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System in Package. Diagnosis and embedded repairHahanov, V / Sushanov, A / Stepanova, Y / Gorobets, A et al. | 2010
- 473
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Technology for faulty blocks coverage by sparesVladimir, H / Svetlana, C / Eugenia, L / Oleg, Z / Natalka, K et al. | 2010
- 479
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The Unicast Feedback models for real-time control protocolBabich, A V / Abbas, Murad Ali et al. | 2010
- 482
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Algebra-logical repair method for FPGA logic blocksHahanov, V / Galagan, S / Olchovoy, V / Priymak, A et al. | 2010
- 495
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IEEE 1500 compliant test wrapper generation tool for VHDL modelsMikhtonyuk, S / Davydov, M / Hwang, R / Shcherbin, D et al. | 2010
- 500
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Early detection of potentially non-synchronized CDC paths using structural analysis techniqueMelnik, D / Lukashenko, O / Zaychenko, S et al. | 2010
- 504
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Architecture design and technical methodology for bus testingHaghbayan, M H / Navabi, Z et al. | 2010
- 509
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Assertion based verification in TLMGhofrani, A / Javaheri, F / Navabi, Z et al. | 2010
- 514
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Advanced topics of FSM design using FPGA educational boards and web-based toolsSudnitson, A / Mihhailov, D / Kruus, M et al. | 2010
- 518
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A mixed HDL/PLI test packageNemati, Nastaran / Namaki-Shoushtari, Majid / Navabi, Zainalabedin et al. | 2010
- 530
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Extended complete switch as ideal system networkKaravay, M F / Podlazov, V S et al. | 2010
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Image compression: Comparative analysis of basic algorithmsSulema, Yevgeniya / Kahou, Samira Ebrahimi et al. | 2010
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COMPAS — Advanced test compressorJeniček, J / Novák, O et al. | 2010
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[Front cover]| 2010