0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology (Englisch)
- Neue Suche nach: Ohguro, T.
- Neue Suche nach: Naruse, H.
- Neue Suche nach: Sugaya, H.
- Neue Suche nach: Kimijima, H.
- Neue Suche nach: Morifuji, E.
- Neue Suche nach: Yoshitomi, T.
- Neue Suche nach: Morimoto, T.
- Neue Suche nach: Momose, H.S.
- Neue Suche nach: Katsumata, Y.
- Neue Suche nach: Iwai, H.
- Neue Suche nach: Ohguro, T.
- Neue Suche nach: Naruse, H.
- Neue Suche nach: Sugaya, H.
- Neue Suche nach: Kimijima, H.
- Neue Suche nach: Morifuji, E.
- Neue Suche nach: Yoshitomi, T.
- Neue Suche nach: Morimoto, T.
- Neue Suche nach: Momose, H.S.
- Neue Suche nach: Katsumata, Y.
- Neue Suche nach: Iwai, H.
In:
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)
;
927-930
;
1998
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ISBN:
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ISSN:
- Aufsatz (Konferenz) / Elektronische Ressource
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Titel:0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology
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Beteiligte:Ohguro, T. ( Autor:in ) / Naruse, H. ( Autor:in ) / Sugaya, H. ( Autor:in ) / Kimijima, H. ( Autor:in ) / Morifuji, E. ( Autor:in ) / Yoshitomi, T. ( Autor:in ) / Morimoto, T. ( Autor:in ) / Momose, H.S. ( Autor:in ) / Katsumata, Y. ( Autor:in ) / Iwai, H. ( Autor:in )
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Erschienen in:
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Verlag:
- Neue Suche nach: IEEE
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Erscheinungsdatum:01.01.1998
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Format / Umfang:404612 byte
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ISBN:
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ISSN:
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DOI:
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Medientyp:Aufsatz (Konferenz)
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Format:Elektronische Ressource
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Sprache:Englisch
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Datenquelle:
Inhaltsverzeichnis Konferenzband
Die Inhaltsverzeichnisse werden automatisch erzeugt und basieren auf den im Index des TIB-Portals verfügbaren Einzelnachweisen der enthaltenen Beiträge. Die Anzeige der Inhaltsverzeichnisse kann daher unvollständig oder lückenhaft sein.
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International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)| 1998
- 3
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Executing system on a chip: requirements for a successful SOC implementationDaeje Chin, et al. | 1998
- 9
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Intercontinental migration of dominant technologiesOtala, M. et al. | 1998
- 14
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Trends in semiconductor equipment, materials, and processing technologyPeercy, P.S. et al. | 1998
- 21
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Amorphous silicon TFT X-ray image sensorsWeisfield, R.L. et al. | 1998
- 21
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Amorphous Silicon TFT X-Ray Image Sensors (Invited)Weisfield, R. / IEEE; Electron Devices Society et al. | 1998
- 25
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Monolithic integration of light emitting diodes, detectors and optical fibers on a silicon wafer: a CMOS compatible optical sensorMisiakos, I. / Tsoi, E. / Kakabakos, S. et al. | 1998
- 29
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A novel p-i-n photodetector fabricated on SIMOX for 1 GHz 2 V CMOS OEICsYoshida, T. / Ohtomo, Y. / Shimaya, M. et al. | 1998
- 33
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640/spl times/480 back-illuminated CCD imager with improved blooming control for night visionBurke, B.E. / Reich, R.K. / Gregory, J.A. / McGonagle, W.H. / Waxman, A.M. / Savoye, E. / Kosicki, B.B. et al. | 1998
- 33
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640x480 Back-Illuminated CCD Imager with Improved Blooming Control for Night VisionBurke, B. / Reich, R. / Gregory, J. / McGonagle, W. / IEEE; Electron Devices Society et al. | 1998
- 37
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A 2/3" 2-M pixel progressive scan FT-CCD for digital still camera applicationsBosiers, J.T. / Kleimann, A.C. / Korthout, L. / Verbugt, D.W. / Peek, H.L. / Roks, E. / Heringa, A. / Vledder, F.F. / Opmeer, P. et al. | 1998
- 41
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Dynamic range improvement by narrow-channel effect suppression and smear reduction technologies in small pixel IT-CCD image sensorsTanabe, A. / Kudoh, Y. / Kawakami, Y. / Masubuchi, K. / Kawai, S. / Yamada, T. / Morimoto, M. / Arai, K. / Hatano, K. / Furumiya, M. et al. | 1998
- 45
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A snap-shot CMOS active pixel imager for low-noise, high-speed imagingGuang Yang, / Yadid-Pecht, O. / Wrigley, C. / Pain, B. et al. | 1998
- 51
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Wide Bandgap Semiconductor Power Electronics (Invited)Weitzel, C. / IEEE; Electron Devices Society et al. | 1998
- 51
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Wide bandgap semiconductor power electronicsWeitzel, C.E. et al. | 1998
- 55
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Direct measurement of gate depletion in high breakdown (405 V) AlGaN/GaN heterostructure field effect transistorsVetury, R. / Wu, Y.-F. / Fini, P.T. / Parish, G. / Keller, S. / DenBaars, S. / Mishra, U.K. et al. | 1998
- 59
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Novel high power AlGaAs/GaAs HFET with a field-modulating plate operated at 35 V drain voltageAsano, K. / Miyoshi, Y. / Ishikura, K. / Nashimoto, Y. / Kuzuhara, M. / Mizuta, M. et al. | 1998
- 63
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Low-distortion GaAs-based field effect transistors with InGaP channel layer for high-voltage operationHara, N. / Nakasha, Y. / Kikkawa, T. / Takahashi, H. / Joshin, K. / Watanabe, Y. / Tanaka, H. / Takikawa, M. et al. | 1998
- 67
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Depletion-mode GaAs MOSFETs with negligible drain current drift and hysteresisWang, Y.C. / Hong, M. / Kuo, J.M. / Mannaerts, J.P. / Kwo, J. / Tsai, H.S. / Krajewski, J.J. / Chen, Y.K. / Cho, A.Y. et al. | 1998
- 71
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Improvement of off-state breakdown voltage in power GaAs MESFETs based on an accurate simulation schemeKunihiro, K. / Takahashi, Y. / Ohno, Y. et al. | 1998
- 77
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Quasi 3-D Device Simulator for Microwave Noise Characterization of MOS DevicesLin, Y. / Wang, L. / Obrecht, M. / Manku, T. / IEEE; Electron Devices Society et al. | 1998
- 77
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Quasi-3D device simulation for microwave noise characterization of MOS devicesYi Lin, / Lan Wang, / Obrecht, R. / Manku, T. et al. | 1998
- 81
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Physics-based RF noise modeling of submicron MOSFETsDonati, S. / Alam, M.A. / Krisch, K.S. / Martin, S. / Pinto, M.R. / Vuong, H.H. / Bonani, F. / Ghione, G. et al. | 1998
- 85
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BSIM3 based RTS and 1/f noise models suitable for circuit simulatorsMartin, S. / Li, G.P. / Guan, H. / D'Souza, S. / Matloubian, M. / Claudius, G. / Compton, G. et al. | 1998
- 89
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A physically based model for low-frequency noise of poly-silicon resistorsBrederlow, R. / Weber, W. / Dahl, C. / Schmitt-Landsiedel, D. / Thewes, R. et al. | 1998
- 93
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Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuitsYonezawa, H. / Jingjun Fang, / Kawakami, Y. / Iwanishi, N. / Lifeng Wu, / Chen, A.I.-H. / Koike, N. / Chune-Sin Yeh, / Zhihong Liu, et al. | 1998
- 97
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ESD circuit synthesis and analysis using TCAD and SPICERodriguez, J. / Smayling, M.C. / Wilson, W.L. et al. | 1998
- 101
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A compact SOI-MOSFET model for high temperature circuit simulation with emphasis on process and layout dataPeters, H. / Seegebrecht, P. et al. | 1998
- 107
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Status of single-electron memoriesYano, K. / Ishii, T. / Sano, T. / Mine, T. / Murai, F. / Kure, T. / Seki, K. et al. | 1998
- 107
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Status of Single-Electron Memories (Invited)Yano, K. / Ishii, T. / Sano, T. / Mine, T. / IEEE; Electron Devices Society et al. | 1998
- 111
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Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectricsIlgweon Kim, / Sangyeon Han, / Hyungsik Kim, / Jongho Lee, / Bumho Choi, / Sungwoo Hwang, / Doyeol Ahn, / Hyungcheol Shin, et al. | 1998
- 115
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MOS Memory Using Germanium Nanocrystals Formed by Thermal Oxidation of Si~1~-~xGe~xKing, Y. / King, T. / Hu, C. / IEEE; Electron Devices Society et al. | 1998
- 115
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MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/Ya-Chin King, / Tsu-Jae King, / Chenming Hu, et al. | 1998
- 119
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Influence of quantum confinement effects on single electron and single hole transistorsIshikuro, H. / Hiramoto, T. et al. | 1998
- 123
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Fabrication method for IC-oriented Si twin island single electron transistorsOno, Y. / Takahashi, Y. / Yamazaki, M. / Nagase, M. / Namatsu, H. / Kurihara, K. / Murase, K. et al. | 1998
- 127
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A multi-gate single-electron transistor and its application to an exclusive-OR gateTakahashi, Y. / Fujiwara, A. / Yamazaki, K. / Namatsu, H. / Kurihara, K. / Murase, K. et al. | 1998
- 133
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Shallow trench isolation for advanced ULSI CMOS technologiesNandakumar, M. / Chatterjee, A. / Sridhar, S. / Joyner, K. / Rodder, M. / Chen, I.-C. et al. | 1998
- 133
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Shallow Trench Isolation for Advanced ULSI CMOS Technologies (Invited)Nandakumar, M. / Chatterjee, A. / Sridhar, S. / Joyner, K. / IEEE; Electron Devices Society et al. | 1998
- 137
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Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)Matsuda, S. / Sato, T. / Yoshimura, H. / Takegawa, Y. / Sudo, A. / Mizushima, I. / Tsunashima, Y. / Toyoshima, Y. et al. | 1998
- 141
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Stress analysis of shallow trench isolation for 256 M DRAM and beyondKuroi, T. / Uchida, T. / Horita, K. / Sakai, M. / Inoue, Y. / Nishimura, T. et al. | 1998
- 145
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Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyondTai-Kyung Kim, / Do-Hyung Kim, / Jae-Kwan Park, / Tai-Su Park, / Young-Kwan Park, / Hoong-Joo Lee, / Kang-Yoon Lee, / Jeong-Taek Kong, / Jong-Woo Park, et al. | 1998
- 149
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Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention timeSaino, K. / Okonogi, K. / Horiba, S. / Sakao, M. / Komuro, M. / Takaishi, Y. / Sakoh, T. / Yoshida, K. / Koyama, K. et al. | 1998
- 153
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Leakage current observation on irregular local PN junctions forming the tail distribution of DRAM retention characteristics, with new test structureUeno, T. / Yamashita, T. / Oda, H. / Komori, S. / Inoue, Y. / Nishimura, T. et al. | 1998
- 157
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Local-field-enhancement model of DRAM retention failureHiraiwa, A. / Ogasawara, M. / Natsuaki, N. / Itoh, Y. / Iwai, H. et al. | 1998
- 163
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Ultra-thin gate oxides-performance and reliabilityIwai, H. / Momose, H.S. et al. | 1998
- 163
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Ultra-Thin Gate Oxides - Performance and Reliability (Invited)Iwai, H. / Momose, H. S. / IEEE; Electron Devices Society et al. | 1998
- 167
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Reliability projection for ultra-thin oxides at low voltageStathis, J.H. / DiMaria, D.J. et al. | 1998
- 171
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Comparison of E and 1/E TDDB models for SiO/sub 2/ under long-term/low-field test conditionsMcPherson, J. / Reddy, V. / Banerjee, K. / Huy Le, et al. | 1998
- 171
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Comparison of E and 1/E TDDB Models for SiO~2 Under Long-Term/Low-Field Test ConditionsMcPherson, J. / Reddy, V. / Banerjee, K. / Le, H. / IEEE; Electron Devices Society et al. | 1998
- 175
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Influence of 1 nm-thick structural "strained-layer" near SiO/sub 2//Si interface on sub-4 nm-thick gate oxide reliabilityEriguchi, K. / Harada, Y. / Niwa, M. et al. | 1998
- 175
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Influence of 1nm-Thick Structural "Strained-Layer" near SiO~2/Si Interface on Sub-4nm-Thick Gate Oxide ReliabilityEriguchi, K. / Harada, Y. / Niwa, M. / IEEE; Electron Devices Society et al. | 1998
- 179
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Explanation of stress-induced damage in thin oxidesBude, D.J. / Weir, B.E. / Silverman, P.J. et al. | 1998
- 183
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A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structuresSakura, T. / Utsunomiya, H. / Kamakura, Y. / Taniguchi, K. et al. | 1998
- 187
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Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failureWu, E. / Nowak, E. / Aitken, J. / Abadeer, W. / Han, L.K. / Lo, S. et al. | 1998
- 191
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Point contact conduction at the oxide breakdown of MOS devicesSune, J. / Miranda, E. / Nafria, M. / Aymerich, X. et al. | 1998
- 197
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A high performance 180 nm generation logic technologyYang, S. / Ahmed, S. / Arcot, B. / Arghavani, R. / Bai, P. / Chambers, S. / Charvat, P. / Cotner, R. / Gasser, R. / Ghani, T. et al. | 1998
- 201
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A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable Beyond 0.18m Generation and Desirable for Ultra High Speed OperationIshida, M. / Kawakami, T. / Tsuji, A. / Kawamoto, N. / IEEE; Electron Devices Society et al. | 1998
- 201
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A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operationIshida, M. / Kawakami, T. / Tsuji, A. / Kawamoto, N. / Motoyoshi, M. / Ouchi, N. et al. | 1998
- 205
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A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunityOotsuka, F. / Nakamura, M. / Miyake, T. / Iwahashi, S. / Ohira, Y. / Tamaru, T. / Kikushima, K. / Yamaguchi, K. et al. | 1998
- 205
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A Novel 0.20m Full CMOS SRAM Cell Using Stacked Cross Couple with Enhanced Soft Error ImmunityOotsuka, F. / Nakamura, M. / Miyake, T. / Iwahashi, S. / IEEE; Electron Devices Society et al. | 1998
- 209
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A 0.2m Bipolar-CMOS Technology on Bonded SOI with Copper Metallization for Ultra, High-Speed ProcessorsHashimoto, T. / Kikuchi, T. / Watanabe, K. / Ohashi, N. / IEEE; Electron Devices Society et al. | 1998
- 209
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A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processorsHashimoto, T. / Kikuchi, T. / Watanabe, K. / Ohashi, N. / Saito, T. / Yamaguchi, H. / Wada, S. / Natsuaki, N. / Kondo, M. / Kondo, S. et al. | 1998
- 213
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An RF BiCMOS Process Using High f~S~R Spiral Inductor with Premetal Deep Trenches and a Dual Recessed Bipolar Collector SinkYoshida, H. / Suzuki, H. / Kinoshita, Y. / Fujii, H. / IEEE; Electron Devices Society et al. | 1998
- 213
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An RF BiCMOS process using high f/sub SR/ spiral inductor with premetal deep trenches and a dual recessed bipolar collector sinkYoshida, H. / Suzuki, H. / Kinoshita, Y. / Fujii, H. / Yamazaki, T. et al. | 1998
- 217
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1.8 million transistor CMOS ASIC fabricated in a SiGe BiCMOS technologyJohnson, R.A. / Zierak, M.J. / Outama, K.B. / Bahn, T.C. / Joseph, A.J. / Cordero, C.N. / Malinowski, J. / Weeks, T.W. / Milliken, R.A. / Medve, T.J. et al. | 1998
- 223
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30-nm-gate InAlAs/InGaAs HEMTs lattice-matched to InP substratesSuemitsu, T. / Ishii, T. / Yokoyama, H. / Umeda, Y. / Enoki, T. / Ishii, Y. / Tamamura, T. et al. | 1998
- 227
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Improvement of DC, low frequency and reliability properties of InAlAs/InGaAs InP-based HEMTs by means of an InP etch stop layerMeneghesso, G. / Buttari, D. / Perin, E. / Canali, C. / Zanoni, E. et al. | 1998
- 231
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Hydrogen degradation in InP HEMTsBlanchard, R.R. / del Alamo, J.A. / Chao, P.C. / Adams, S.B. et al. | 1998
- 235
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Metamorphic In/sub x/Al/sub 1-x/As/In/sub x/Ga/sub 1-x/As HEMTs on GaAs substrate: the influence of In compositionBollaert, S. / Cordier, Y. / Happy, H. / Zaknoune, M. / Hoel, V. / Lepilliet, S. / Cappy, A. et al. | 1998
- 235
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Metamorphic In~xAl~1~-~xAs/In~xGa~1~-~xAs HEMTs on GaAs Substrate: The Influence of In CompositionBollaert, S. / Cordier, Y. / Happy, H. / Zaknoune, M. / IEEE; Electron Devices Society et al. | 1998
- 239
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Deep submicron PHEMTs characterization with spectrally resolved carrier recombination imagingWang, Z.Y. / Qian, J.Y. / Li-Jen Cheng, / Li, G.P. / Chou, Y.C. / Lai, R. / Streit, D.C. et al. | 1998
- 243
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A new dynamic model for the kink effect in InAlAs/InGaAs HEMTsSomerville, M.H. / Ernst, A. / del Alamo, J.A. et al. | 1998
- 249
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Integrated a-Si:H/pentacene inorganic/organic complementary circuitsBonse, M. / Thomasson, D.B. / Klauk, H. / Gundlach, D.J. / Jackson, T.N. et al. | 1998
- 253
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Tri-layer a-Si:H integrated circuits on polymeric substratesThomasson, D.B. / Bonse, M. / Jiunn-Ru Huang, / Wronski, C.R. / Jackson, T.N. et al. | 1998
- 257
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PolySilicon Thin Film Transistors Fabricated at 100C on a Flexible Plastic SubstrateTheiss, S. / Carey, P. / Smith, P. / Wickboldt, P. / IEEE; Electron Devices Society et al. | 1998
- 257
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Polysilicon thin film transistors fabricated at 100/spl deg/C on a flexible plastic substrateTheiss, S.D. / Carey, P.G. / Smith, P.M. / Wickboldt, P. / Sigmon, T.W. / Tung, Y.J. / King, T.-J. et al. | 1998
- 261
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Hydrogen plasma-enhanced crystallization of amorphous silicon for low-temperature polycrystalline silicon TFT'sPangal, K. / Sturm, J.C. / Wagner, S. et al. | 1998
- 265
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Improved stability of polysilicon thin-film transistors under self-heating and high endurance EEPROM cells for systems-on-panelJin-Woo Lee, / Nae-In Lee, / Hoon-Ju Chung, / Chul-Hi Han, et al. | 1998
- 269
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Highly reliable liquid-phase deposited SiO/sub 2/ with nitrous oxide plasma post-treatment for low temperature processed poly-Si TFTsYeh, C.F. / Chen, D.C. / Lu, C.Y. / Liu, C. / Lee, S.T. / Liu, C.H. / Chen, T.J. et al. | 1998
- 269
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Highly Reliable Liquid-Phase Deposited SiO~2 with Nitrous Oxide Plasma Post-Treatment for Low Temperature Processed Poly-Si TFTsYeh, C. / Chen, D. / Lu, C. / Liu, C. / IEEE; Electron Devices Society et al. | 1998
- 273
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A conductivity modulated high voltage polycrystalline silicon thin film transistor with improved on state and transient performanceXu, Y.Z. / Clough, F.J. / Narayanan, E.M.S. / Chen, Y. / Milne, W.I. et al. | 1998
- 277
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Modeling of grain size variation effects in polycrystalline thin film transistorsWang, A.W. / Saraswat, K.C. et al. | 1998
- 283
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Within-chip variability analysisNassif, S.R. et al. | 1998
- 283
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Within-Chip Variability Analysis (Invited)Nassif, S. / IEEE; Electron Devices Society et al. | 1998
- 287
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Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-chargingHi-Deok Lee, / Myoung-Jun Jang, / Dae-Gwan Kang, / Young-Jong Lee, / Jeong-Mo Hwang, / Dae-Mann Kim, et al. | 1998
- 291
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Impact of crosstalk on delay time and a hierarchy of interconnectsYamashita, K. / Odanaka, S. et al. | 1998
- 291
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Impact of Crosstalk on Delay Time and Hierarchy of InterconnectsYamashita, K. / Odanaka, S. / IEEE; Electron Devices Society et al. | 1998
- 295
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Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnectionsDeutsch, A. / Harrer, H. / Surovic, C.W. / Hellner, G. / Edelstein, D.C. / Goldblatt, R.D. / Biery, G.A. / Greco, N.A. / Foster, D.M. / Crabbe, E. et al. | 1998
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A fast 3D modeling approach to parasitics extraction of bonding wires for RF circuitsXiaoning Qi, / Yue, C.P. / Soh, H.T. / Zhiping Yu, / Dutton, R.W. / Sakai, H. et al. | 1998
- 303
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Equipotential shells for efficient partial inductance extractionBeattie, M. / Alatan, L. / Pileggi, L. et al. | 1998
- 307
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Process- and geometry-scalable bipolar transistor and transmission line models for Si and SiGe MMICs in the 5-22 GHz rangeVoinigescu, S.P. / Marchesan, D. / Showell, J.L. / Maliepaard, M.C. / Cudnoch, M. / Schumacher, M.G.M. / Herod, M. / Walkey, D.J. / Babcock, G.E. / Schvan, P. et al. | 1998
- 311
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Deposition and simulation of refractory barriers into high aspect ratio re-entrant features using directional sputteringSmy, T. / Joshi, R.V. / Dew, S.K. / Brett, M.J. et al. | 1998
- 317
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Achieving High Microprocessor Manufacturing Output-The Copy Exactly! Method (Invited)Gasser, R. / IEEE; Electron Devices Society et al. | 1998
- 317
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Achieving high microprocessor manufacturing output-the Copy Exactly! methodGasser, R.A. et al. | 1998
- 321
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Foundry Technology for the Next Decade (Invited)Sun, J. / Chiang, S. / Liu, M. / IEEE; Electron Devices Society et al. | 1998
- 321
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Foundry technology for the next decadeSun, J.Y.C. / Shang-Yi Chiang, / Liu, M. et al. | 1998
- 325
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Cost-effective cleaning for advanced Si-processingHeyns, M.M. / Bearda, T. / Cornelissen, I. / De Gendt, S. / Knotter, D.M. / Loewenstein, L.M. / Lux, M. / Mertens, P.W. / Mertens, S. / Meuris, M. et al. | 1998
- 325
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Cost-Effective Cleaning for Advanced Si-Processing (Invited)Heyns, M. / Bearda, T. / Cornilissen, I. / De Gendt, S. / IEEE; Electron Devices Society et al. | 1998
- 329
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Physical and Chemical Analytical Instruments for Failure Analyses in G-Bit Devices (Invited)Mitsui, Y. / Yano, F. / Nakamura, Y. / Kimoto, K. / IEEE; Electron Devices Society et al. | 1998
- 329
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Physical and chemical analytical instruments far failure analyses in Gbit devicesMitsui, Y. / Yano, F. / Nakamura, Y. / Kimoto, K. / Hasegawa, T. / Kimura, S. / Asayama, K. et al. | 1998
- 333
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0.1m Level Contact Hole Pattern Formation with KrF Lithography by Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS)Toyoshima, T. / Ishibashi, T. / Minanide, A. / Sugino, K. / IEEE; Electron Devices Society et al. | 1998
- 333
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0.1 /spl mu/m level contact hole pattern formation with KrF lithography by resolution enhancement lithography assisted by chemical shrink (RELACS)Toyoshima, T. / Ishibashi, T. / Minanide, A. / Sugino, K. / Katayama, K. / Shoya, T. / Arimoto, I. / Yasuda, N. / Adachi, H. / Matsui, Y. et al. | 1998
- 337
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Dry Etch Sequencing Induced Gate Oxide Degradation Due to Metallic Contamination in 0.25m CMOS ManufacturingHughes, J. / Perera, A. / Hernandez, I. / Parihar, S. / IEEE; Electron Devices Society et al. | 1998
- 337
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Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 /spl mu/m CMOS manufacturingHughes, J. / Perera, A. / Hernandez, I. / Sanjay Parihar, / Karupanna, K. / Vasek, J. / Hanna, J. / Nagy, A. / Lii, T. / Reese, M. et al. | 1998
- 341
-
Threshold pressure and its influence in chemical mechanical polishing for IC fabricationBin Zhao, / Shi, F.G. et al. | 1998
- 347
-
Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMsTogo, M. / Noda, K. / Tanigawa, T. et al. | 1998
- 351
-
A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyondYoon-Soo Chun, / Byung-Jun Park, / Gi-Tae Jeong, / Yoo-Sang Hwang, / Kyu-Hyun Lee, / Hong-Sik Jeong, / Tae-Young Jung, / Kinam Kim, et al. | 1998
- 355
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Future Directions for DRAM Memory Cell Technology (Invited)Nitayama, A. / Kohyama, Y. / Hieda, K. / IEEE; Electron Devices Society et al. | 1998
- 355
-
Future directions for DRAM memory cell technologyNitayama, A. / Kohyama, Y. / Hieda, K. et al. | 1998
- 359
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FRAM Cell Design with High Immunity to Fatigue and Imprint for 0.5m 3V 1T1C 1M Bit FRAMTanaka, S. / Ogiwara, R. / Itoh, Y. / Miyakawa, T. / IEEE; Electron Devices Society et al. | 1998
- 359
-
FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1M bit FRAMTanaka, S. / Ogiwara, R. / Itoh, Y. / Miyakawa, T. / Takeuchi, Y. / Doumae, S. / Takenaka, H. / Kamata, H. et al. | 1998
- 363
-
Capacitor-on-metal/via-stacked-plug (CMVP) memory cell for 0.25 /spl mu/m CMOS embedded FeRAMAmanuma, K. / Tatsumi, T. / Maejima, Y. / Takahashi, S. / Hada, H. / Okizaki, H. / Kunio, T. et al. | 1998
- 363
-
Capacitor-on-Metal/Via Stacked-Plug (CMVP) Memory Cell for 0.25m CMOS Embedded FeRamAmanuma, K. / Tatsumi, T. / Maejima, Y. / Takahashi, S. / IEEE; Electron Devices Society et al. | 1998
- 367
-
Impact of neutron flux on soft errors in MOS memoriesEto, A. / Hidaka, M. / Okuyama, Y. / Kimura, K. / Hosono, M. et al. | 1998
- 373
-
Ultra thin (<20 /spl Aring/) CVD Si/sub 3/N/sub 4/ gate dielectric for deep-sub-micron CMOS devicesSong, S.C. / Luan, H.F. / Chen, Y.Y. / Gardner, M. / Allen, M. / Kwong, D.L. et al. | 1998
- 377
-
High Quality Ultra-Thin TiO~2/Si~3N~4 Gate Dielectric for Giga Scale MOS TechnologyGuo, X. / Ma, T. / Tamagawa, T. / Halpern, B. / IEEE; Electron Devices Society et al. | 1998
- 377
-
High quality ultra-thin TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric for giga scale MOS technologyXin Guo, / Ma, T.P. / Tamagawa, T. / Halpern, B.L. et al. | 1998
- 381
-
SiOn/Ta~2O~5/TiN Gate Stack Transistor with 1.8nm Equivalent SiO~2 ThicknessPark, D. / Lu, Q. / King, T. / Hu, C. / IEEE; Electron Devices Society et al. | 1998
- 381
-
SiON/Ta/sub 2/O/sub 5//TiN gate-stack transistor with 1.8 nm equivalent SiO/sub 2/ thicknessDonggun Park, / Qiang Lu, / Tsu-Jae King, / Chenming Hu, / Kalnitsky, A. / Sing-Pin Tay, / Chia-Cheng Cheng, et al. | 1998
- 385
-
In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline SiByung Hak Lee, / Dong Kyun Sohn, / Ji-Soo Park, / Chang Hee Han, / Yun-Jun Huh, / Jeong Soo Byun, / Jae Jeong Kim, et al. | 1998
- 385
-
In-Situ Barrier Formation for High Reliable W/Barrier/Poly-Si Gate Using Denudation of WN~x on Polycrystalline SiLee, B. / Sohn, D. / Park, J. / Han, C. / IEEE; Electron Devices Society et al. | 1998
- 389
-
Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyondHiura, Y. / Azuma, A. / Nakajima, K. / Akasaka, Y. / Miyano, K. / Nitta, H. / Honjo, A. / Tsuchida, K. / Toyoshima, Y. / Suguro, K. et al. | 1998
- 393
-
An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layerWakabayashi, H. / Yamamoto, T. / Yoshida, K. / Soda, E. / Tokunaga, K. / Mogami, T. / Kunio, T. et al. | 1998
- 397
-
Improving Gate Oxide Integrity (GOI) of a W/WN~x/Dual-Poly Si Stacked-Gate by Using Wet-Hydrogen Oxidation in 0.14m CMOS DevicesOhnishi, K. / Yamamoto, N. / Uchino, T. / Hanaoka, Y. / IEEE; Electron Devices Society et al. | 1998
- 397
-
Improving gate oxide integrity (GOI) of a W/WNx/dual-poly Si stacked-gate by using wet-hydrogen oxidation in 0.14-/spl mu/m CMOS devicesOhnishi, K. / Yamamoto, N. / Uchino, T. / Hanaoka, Y. / Tsuchiya, R. / Nonaka, Y. / Tanabe, Y. / Umezawa, T. / Fukuda, N. / Mitani, S. et al. | 1998
- 403
-
Scalability of SOI Technology into 0.13m 1.2 V CMOS GenerationLeobandung, E. / Sherony, M. / Sleight, J. / Bolam, R. / IEEE; Electron Devices Society et al. | 1998
- 403
-
Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generationLeobandung, E. / Sherony, M. / Sleight, J. / Bolam, R. / Assaderaghi, F. / Wu, S. / Schepis, D. / Ajmera, A. / Rausch, W. / Davari, B. et al. | 1998
- 407
-
Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25nm Gate Length GenerationWong, H. / Frank, D. / Solomon, R. / IEEE; Electron Devices Society et al. | 1998
- 407
-
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generationWong, H.-S.P. / Frank, D.J. / Solomon, P.M. et al. | 1998
- 411
-
Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applicationsMiyamoto, M. / Nagai, R. / Nagano, T. et al. | 1998
- 415
-
Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technologyKotaki, H. / Kakimoto, S. / Nakano, M. / Adachi, K. / Shibata, A. / Sugimoto, K. / Ohta, K. / Hashizume, N. et al. | 1998
- 419
-
A new dynamic-threshold SOI device having an embedded resistor and a merged body-bias-control transistorHoriuchi, M. et al. | 1998
- 423
-
High performance electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltageTakamiya, M. / Hiramoto, T. et al. | 1998
- 423
-
High Performance Electrically induced Body Dynamic Threshold SOl MOSFET (EIB-DTMOS) with Large Body Effect and Low Threshold VoltageTakamiya, M. / Hiramoto, T. / IEEE; Electron Devices Society et al. | 1998
- 429
-
Transistors and Tunnel Diodes for Analog/Mixed-Signal Circuits and Embedded Memory (Invited)Seabaugh, A. / Brar, B. / Deng, X. / Blake, T. / IEEE; Electron Devices Society et al. | 1998
- 429
-
Transistors and tunnel diodes for analog/mixed-signal circuits and embedded memorySeabaugh, A. / Deng, X. / Brar, B. / Broekaert, T. / Lake, R. / Morris, F. / Frazier, G. et al. | 1998
- 433
-
Arrays of resonant tunnelling diodes defined by in-situ focused ion beam lithography: potential millimetre wave/microwave power sources?See, P. / Steenson, D.P. / Linfield, E.H. / Rose, P.D. / Collins, C.E. / Ritchie, D.A. / Jones, G.A.C. et al. | 1998
- 437
-
Tetrahedral shaped recess channel HEMT with a floating quantum dot gateShima, M. / Sakuma, Y. / Futatsugi, T. / Awano, Y. / Yokoyama, N. et al. | 1998
- 441
-
Room temperature operating infrared (8-12 /spl mu/m) photodetector with InAs quantum dots in modulation doped heterostructuresTaehee Cho, / Jong-Wook Kim, / Jae-Eung Oh, / Songcheol Hong, et al. | 1998
- 441
-
Room Temperature Operating Infrared (8-12m) Photodetector with InAs Quantum Dots In Modulation Doped HeterostructuresCho, T. / Kim, J. / Oh, J. / Hong, S. / IEEE; Electron Devices Society et al. | 1998
- 441
-
Room temperature operating infrared (8-12 mu m) photodetector with InAs quantum dots in modulation doped heterostructuresCho, Taehee / Kim, Jong-Wook / Oh, Jae-Eung / Hong, Songcheol et al. | 1998
- 445
-
Spectral hole burning of InAs self-assembled quantum dots written by two different lasersSugiyama, Y. / Nakata, Y. / Muto, S. / Futatsugi, T. / Yokoyama, N. et al. | 1998
- 449
-
Room temperature Coulomb oscillation and memory effect for single electron memory made by pulse-mode AFM nano-oxidation processMatsumoto, K. / Gotoh, Y. / Maeda, T. / Dagata, J.A. / Harris, J.S. et al. | 1998
- 453
-
A resonant terahertz detector utilizing a high electron mobility transistorJian-Qiang Lu, / Shur, M.S. / Hesler, J.L. / Liangquan Sun, / Weikle, R. et al. | 1998
- 459
-
Monolithic Arrays of Micromachined Pixels for Infrared Applications (Invited)Cole, B. / Higashi, R. / Wood, R. / IEEE; Electron Devices Society et al. | 1998
- 459
-
Monolithic arrays of micromachined pixels for infrared applicationsCole, B.E. / Higashi, R.E. / Wood, R.A. et al. | 1998
- 463
-
A high fill-factor IR bolometer using multi-level electrothermal structuresHyung-Kew Lee, / Jun-Bo Yoon, / Euisik Yoon, / Sang-Baek Ju, / Yoon-Joong Yong, / Wook Lee, / Sang-Gook Kim, et al. | 1998
- 467
-
High-selectivity single-chip spectrometer for operation at visible wavelengthsCorreia, J.H. / Bartek, M. / Wolffenbuttel, R.F. et al. | 1998
- 471
-
Microelectromechanical Mixer+ FiltersWong, A. / Ding, H. / Nguyen, C. / IEEE; Electron Devices Society et al. | 1998
- 471
-
Micromechanical mixer and filtersArk-Chew Wong, / Hao Ding, / Nguyen, C.T.-C. et al. | 1998
- 475
-
Trench oxide isolated single crystal silicon micromachined accelerometerSridhar, U. / Lau Choon How, / Liu Lian Jun, / Miao Yu Bo, / Tan Khen-Sang, / Foo Pang Dow, / Bergstrom, J. / Sooriakumar, K. / Loh Yong Hong, / Lee Han San, et al. | 1998
- 479
-
In-plane sensitive vertical trench-Hall deviceSteiner, R. / Kroener, F. / Olbrich, T. / Baresch, R. / Baltes, H. et al. | 1998
- 483
-
Novel thermal microactuator based on CVD-diamond filmsGluche, P. / Leuner, R. / Kohn, E. / Rembe, C. / Aus der Wiesche, S. / Hofer, E.P. et al. | 1998
- 489
-
Defect and Dopant Diffusion in Ion Implanted Silicon: An Atomic Scale Simulation Approach (Invited)Caturla, M. / Theiss, S. / Lenosky, T. J. / Diaz de la Rubia, T. / IEEE; Electron Devices Society et al. | 1998
- 489
-
Defect and dopant diffusion in ion implanted silicon: an atomic scale simulation approachCaturla, M.-J. / Theiss, S.K. / Lenosky, T.J. / Diaz de la Rubia, T. et al. | 1998
- 493
-
Predictive simulation of transient activation processes in boron-doped silicon structuresLilak, A.D. / Law, M.E. / Jones, K.S. / Giles, M.D. / Andideh, E. / Caturla, M.-J. / Jing Zhu, / Theiss, S. et al. | 1998
- 497
-
Experiments and modeling of boron segregation to {311} defects and initial rapid enhanced boron diffusion induced by self-implantation in SiSaito, T. / Xia, J. / Kim, R. / Aoki, T. / Kobayashi, H. / Kamakura, Y. / Taniguchi, K. et al. | 1998
- 497
-
Experiments and Modeling of Boron Segregation to {311} Defects and Initital Rapid Enhanced Boron Diffusion Induced by Self-Implantation in SiSaito, T. / Xia, J. / Kim, R. / Aoki, T. / IEEE; Electron Devices Society et al. | 1998
- 501
-
Beyond TED: understanding boron shallow junction formationDunham, S.T. / Chakravarthi, S. / Gencer, A.H. et al. | 1998
- 505
-
Modeling solid source boron diffusion for advanced transistor applicationsPackan, P. / Thompson, S. / Andideh, E. / Yu, S. / Ghani, T. / Giles, M. / Sandford, J. / Bohr, M. et al. | 1998
- 509
-
A calibrated model for trapping of implanted dopants at material interface during thermal annealingYong-Seog Oh, / Ward, D.E. et al. | 1998
- 513
-
Monte Carlo simulation of ion implantation into topographically complex structuresObradovic, B.J. / Balamurugan, G. / Wang, G. / Chen, Y. / Tasch, A.F. et al. | 1998
- 517
-
New analytic models and efficient parameter extraction for computationally efficient 1-D and 2-D ion implantation modelingBalamurugan, G. / Obradovic, B. / Wang, G. / Chen, Y. / Tasch, A. et al. | 1998
- 523
-
Progress in RF inductors on silicon-understanding substrate lossesBurghartz, J.N. et al. | 1998
- 523
-
Progress in RF Inductors on Silicon Understanding Substrate Losses (Invited)Burghartz, J. / IEEE; Electron Devices Society et al. | 1998
- 527
-
Application of a new circuit design oriented Q extraction technique to inductors in silicon ICsTong Chen, / Kihong Kim, / O, K. et al. | 1998
- 531
-
Modeling and characterization of on-chip transformersMohan, S.S. / Yue, C.P. / del Mar Hershenson, M. / Wong, S.S. / Lee, T.H. et al. | 1998
- 535
-
A novel buried oxide isolation for monolithic RF inductors on siliconErzgraber, H.B. / Grabolla, T. / Richter, H.H. / Schley, P. / Wolff, A. et al. | 1998
- 540
-
On-chip spiral inductors with diffused shields using channel-stop implantYoshitomi, T. / Sugawara, Y. / Morifuji, E. / Ohguro, T. / Kimijima, H. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1998
- 544
-
High-Performance Electroplated Solenoid-Type Integrated Inductor (SI^2) for RF Applications Using Simple 3D Surface Micromachining TechnologyYoon, J. / Kim, B. / Han, C. / Yoon, E. / IEEE; Electron Devices Society et al. | 1998
- 544
-
High-performance electroplated solenoid-type integrated inductor (SI/sup 2/) for RF applications using simple 3D surface micromachining technologyJun-Bo Yoon, / Bon-Kee Kim, / Chul-Hi Han, / Euisik Yoon, / Kwyro Lee, / Choong-Ki Kim, et al. | 1998
- 548
-
Novel high-Q bondwire inductor for MMICYong-Goo Lee, / Sang-Ki Yun, / Hai-Young Lee, et al. | 1998
- 555
-
Two-dimensional dopant profiling of a 60 nm gate length nMOSFET using scanning capacitance microscopyTimp, W. / O'Malley, M.L. / Kleiman, R.N. / Garno, J.P. et al. | 1998
- 559
-
Direct Measurement of L~e~f~f and Channel Profile in MOSFETs Using 2-D Carrier Profiling TechniquesDeWolf, P. / Stephenson, R. / Biesemans, S. / Jansen, P. / IEEE; Electron Devices Society et al. | 1998
- 559
-
Direct measurement of l/sub eff/ and channel profile in MOSFETs using 2-D carrier profiling techniquesStephenson, R. / Biesemans, S. / Jansen, Ph. / De Meyer, K. / Vandervorst, W. et al. | 1998
- 563
-
A new evaluation method of plasma process-induced Si substrate damage by the voltage shift under constant current injection at metal/Si interfaceEgashira, K. / Eriguchi, K. / Hashimoto, S. et al. | 1998
- 567
-
Direct detecting of dynamic floating-body effects in SOI circuits by backside electron beam testingYoshida, E. / Koyama, T. / Maeda, S. / Yamaguchi, Y. / Komori, J. / Mashiko, Y. et al. | 1998
- 571
-
Remote charge scattering in MOSFETs with ultra-thin gate dielectricsKrishnan, M.S. / Yee Chia Yeo, / Qiang Lu, / Tsu-Jae King, / Bokor, J. / Chenming Hu, et al. | 1998
- 575
-
Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETsTakayanagi-Takagi, M. / Toyoshima, Y. et al. | 1998
- 579
-
Experimental signature and physical mechanisms of substrate enhanced gate current in MOS devicesEsseni, D. / Selmi, L. et al. | 1998
- 585
-
Sub-5 nm multiple-thickness gate oxide technology using oxygen implantationYa-Chin King, / Kuo, C. / Tsu-Jae King, / Chenming Hu, et al. | 1998
- 589
-
Multiple gate oxide thickness for 2 GHz system-on-a-chip technologiesLiu, C.T. / Ma, Y. / Oh, M. / Diodato, P.W. / Stiles, K.R. / Mcmacken, J.R. / Li, F. / Chang, C.P. / Cheung, K.P. / Colonell, J.I. et al. | 1998
- 593
-
Radical oxygen (O/sup */) process for highly-reliable SiO/sub 2/ with higher film-density and smoother SiO/sub 2//Si interfaceNagamine, M. / Itoh, H. / Satake, H. / Toriumi, A. et al. | 1998
- 593
-
Radical Oxygen (O^*) Process for Highly-Reliable Si0~2 with Higher Film-Density and Smoother Si0~2/Si InterfaceNagamine, M. / Itoh, H. / Satake, H. / Toriumi, A. / IEEE; Electron Devices Society et al. | 1998
- 597
-
Impact of nitridation engineering on microscopic SILC characteristics of sub-10-nm tunnel dielectricsOgata, T. / Inoue, M. / Nakamura, T. / Tsuji, N. / Kobayashi, K. / Kawase, K. / Kurokawa, H. / Kaneoka, T. / Ohno, Y. / Miyoshi, H. et al. | 1998
- 601
-
Antenna device reliability for ULSI processingKrishnan, S. / Amerasekera, A. / Rangan, S. / Aur, S. et al. | 1998
- 605
-
Gate Quality Doped High K Films for CMOS Beyond 100nm: 3-10nm Al~2O~3 with Low Leakage and Low Interface StatesManchanda, L. / Lee, W. / Bower, J. / Baumann, E. / IEEE; Electron Devices Society et al. | 1998
- 605
-
Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface statesManchanda, L. / Lee, W.H. / Bower, J.E. / Baumann, F.H. / Case, C.J. / Keller, R.C. / Kim, Y.O. / Laskowski, E.J. / Morris, M.D. / Opila, R.L. et al. | 1998
- 609
-
Ultra Thin High Quality Ta~2O~5 Gate Dielectric Prepared by In-situ Rapid Thermal ProcessingWu, B. / Luan, H. / Kang, L. / Kim, B. / IEEE; Electron Devices Society et al. | 1998
- 609
-
Ultra thin high quality Ta/sub 2/O/sub 5/ gate dielectric prepared by in-situ rapid thermal processingLuan, H.F. / Wu, B.Z. / Kang, L.G. / Kim, B.Y. / Vrtis, R. / Roberts, D. / Kwong, D.L. et al. | 1998
- 615
-
Progress toward 10 nm CMOS devicesTimp, G. / Bourdelle, K.K. / Bower, J.E. / Baumann, F.H. / Boone, T. / Cirelli, R. / Evans-Lutterodt, K. / Garno, J. / Ghetti, A. / Gossmann, H. et al. | 1998
- 619
-
Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETsTakagi, S. / Takayanagi-Takagi, M. / Toriumi, A. et al. | 1998
- 623
-
A 1.2 V, 0.1 mu m gate length CMOS technology: design and process issuesRodder, M. / Hattangady, S. / Yu, N. / Shiau, W. / Nicollian, P. / Laaksonen, T. / Chao, C.P. / Mehrotra, M. / Lee, C. / Murtaza, S. et al. | 1998
- 623
-
A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issuesRodder, M. / Yu, N. / Shiau, W. / Nicollian, P. / Laaksonen, T. / Chao, C.P. / Mehrotra, M. / Lee, C. / Murtaza, S. / Aur, S. et al. | 1998
- 623
-
A 1.2V, 0.1m Gate Length CMOS Technology: Design and Process IssuesRodder, M. / Hattangady, S. / Yu, N. / Shiau, W. / IEEE; Electron Devices Society et al. | 1998
- 627
-
High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delayHargrove, M. / Crowder, S. / Nowak, E. / Logan, R. / Han, L.K. / Ng, H. / Ray, A. / Sinitsky, D. / Smeys, P. / Guarin, F. et al. | 1998
- 627
-
High-Performance Sub-0.08m CMOS with Dual Gate Oxide and 9.7ps Inverter DelayHargrove, M. / Crowder, S. / Nowak, E. / Logan, R. / IEEE; Electron Devices Society et al. | 1998
- 631
-
A study of ultra shallow junction and tilted channel implantation for high performance 0.1 /spl mu/m pMOSFETsGoto, K. / Kase, M. / Momiyama, Y. / Kurata, H. / Tanaka, T. / Deura, M. / Sanbonsugi, Y. / Sugii, T. et al. | 1998
- 631
-
A Study of Ultra Shallow Junction and Tilted Channel Implantation for High Performance 0.1m PMOSFETsGoto, K. / Kase, M. / Momiyama, Y. / Kurata, H. / IEEE; Electron Devices Society et al. | 1998
- 635
-
Channel profile engineering of 0.1 /spl mu/m-Si MOSFETs by through-the-gate implantationPonomarev, Y.V. / Stolk, P.A. / van Brandenburg, A.C.M.C. / Roes, R. / Montree, A.H. / Schmitz, J. / Woerlee, P.H. et al. | 1998
- 635
-
Channel Profile Engineering of 0.11m-Si MOSFETs by Through-the-Gate ImplantationPonomarev, Y. / Stolk, P. / Van Brandenburg, A. / Roes, R. / IEEE; Electron Devices Society et al. | 1998
- 639
-
High Performance pMOSFET with BF~3 Plasma Doped Gate/Source/Drain and S/D ExtensionHa, J. / Park, J. / Kim, W. / Kim, S. / IEEE; Electron Devices Society et al. | 1998
- 639
-
High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extensionHa, J.M. / Park, J.W. / Kim, W.S. / Song, W.S. / Kim, H.S. / Song, H.J. / Fujihara, K. / Kang, H.K. / Lee, M.Y. / Felch, S. et al. | 1998
- 643
-
A 1.9-/spl mu/m/sup 2/ loadless CMOS four-transistor SRAM cell in a 0.18-/spl mu/m logic technologyNoda, K. / Matsui, K. / Imai, K. / Inoue, K. / Tokashiki, K. / Kawamoto, H. / Yoshida, K. / Takeda, K. / Nakamura, N. / Kimura, T. et al. | 1998
- 643
-
A 1.9m^2 Loadless CMOS Four-Transistor SRAM Cell in a 0.18m Logic TechnologyNoda, K. / Matsui, K. / Imai, K. / Inoue, K. / IEEE; Electron Devices Society et al. | 1998
- 653
-
Advanced performance of small-scaled InGaP/GaAs HBT's with f/sub T/ over 150 GHz and f/sub max/ over 250 GHzOka, T. / Hirata, K. / Ouchi, K. / Uchiyama, H. / Taniguchi, T. / Mochizuki, K. / Nakamura, T. et al. | 1998
- 653
-
Advanced Performance of Small-Scaled InGaP/GaAs HBTs with f~T Over 150 GHz and f~m~a~x over 250 GHzOka, T. / Hirata, K. / Ouchi, K. / Uchiyama, H. / IEEE; Electron Devices Society et al. | 1998
- 657
-
Transferred-substrate HBTs with 250 GHz current-gain cutoff frequencyMensa, D. / Lee, Q. / Guthrie, J. / Jaganathan, S. / Rodwell, M.J.W. et al. | 1998
- 661
-
High-gain GaInP/GaAs HBT monolithic transimpedance amplifier for high-speed optoelectronic receiversMohammadi, S. / Park, J.W. / Pavlidis, D. / Dua, C. / Guyaux, J.L. / Garcia, J.C. et al. | 1998
- 665
-
Broadly-tunable narrow-linewidth micromachined laser/photodetector and phototransistorSugihwo, F. / Lin, C.-C. / Eyres, L.A. / Fejer, M.M. / Harris, J.S. et al. | 1998
- 669
-
Failure analysis of travelling wave MSM distributed photodetectorsNespola, A. / Chau, T. / Pirola, M. / Wu, M.C. / Ghione, G. / Naldi, C.U. et al. | 1998
- 673
-
Investigation of the space charge effect in the quantum well infrared photodetectorKuan, C.H. / Hsu, Y.F. / Hsu, M.C. et al. | 1998
- 679
-
Lateral thinking about power devices (LDMOS)Efland, T.R. / Chin-Yu Tsai, / Pendharkar, S. et al. | 1998
- 679
-
Lateral Thinking About Power Devices (LDMOS) (Invited)Efland, T. / Tsai, C. / Pendharkar, S. / IEEE; Electron Devices Society et al. | 1998
- 683
-
A new generation of high voltage MOSFETs breaks the limit line of siliconDeboy, G. / Marz, N. / Stengl, J.-P. / Strack, H. / Tihanyi, J. / Weber, H. et al. | 1998
- 687
-
A lateral insulated gate bipolar transistor employing the self-align sidewall implanted n/sup +/ sourceByeon, D.S. / Lee, B.H. / Kim, D.Y. / Han, M.K. / Yun, C.M. et al. | 1998
- 687
-
A Lateral Insulated Gate Bipolar Transistor Employing the Self-Align Sidewall Implanted N^+ SourceByeon, D. / Lee, B. / Kim, D. / Han, M. / IEEE; Electron Devices Society et al. | 1998
- 691
-
Backside laserprober characterization of thermal effects during high current stress in smart power ESD protection devicesFurbock, C. / Seliger, N. / Pogany, D. / Litzenberger, M. / Gornik, E. / Stecher, M. / Werner, W. et al. | 1998
- 695
-
Breakdown and low-temperature anomalous effects in 6H SiC JFETsMeneghesso, G. / Bartolini, A. / Verzellesi, G. / Cavallini, A. / Castaldini, A. / Canali, C. / Zanoni, E. et al. | 1998
- 699
-
SiGe fast-switching power diodesBrown, A.R. / Hurkx, G.A.M. / Huizing, H.G.A. / Peter, M.S. / de Boer, W.B. / van Berkum, J.G.M. / Zalm, P.C. / Huang, E. / Koper, N. et al. | 1998
- 703
-
Si/SiGe:C heterojunction bipolar transistors in an epi-free well, single-polysilicon technologyKnoll, D. / Heinemann, B. / Osten, H.J. / Ehwald, B. / Schley, P. / Barth, R. / Matthes, M. / Kwang Soo Park, / Young Kim, / Winkler, W. et al. | 1998
- 707
-
Transconductance enhancement in deep submicron strained Si n-MOSFETsRim, K. / Hoyt, J.L. / Gibbons, J.F. et al. | 1998
- 713
-
Two-dimensional dopant profiling of deep submicron MOS devices by electron holographyRau, W.-D. / Baumann, F.H. / Vuong, H.-H. / Hoppner, W. / Rafferty, C.S. / Rucker, H. / Schwander, P. / Ourmazd, A. et al. | 1998
- 717
-
Validation of two-dimensional implant and diffusion profiles using novel scanning capacitance microscope sample preparation and deconvolution techniquesYu, G.M. / Griffin, P.B. / Plummer, J.D. et al. | 1998
- 721
-
Characterization of arsenic dose loss at the Si/SiO/sub 2/ interface using high resolution X-ray photoelectron spectrometryPianetta, P. / Yun Sun, / Renee Mo, / Griffin, P.B. / Plummer, J.D. et al. | 1998
- 721
-
Characterization of Arsenic Dose Loss at the Si/SiO~2 Interface Using High Resolution X-Ray Photoelectron SpectrometryKasnavi, R. / Pianetta, P. / Sun, Y. / Mo, R. / IEEE; Electron Devices Society et al. | 1998
- 725
-
Suppression of reverse short channel effect by a buried carbon layerGossmann, H.-J. / Rafferty, C.S. / Hobler, G. / Vuong, H.-H. / Jacobson, D.C. / Frei, M. et al. | 1998
- 729
-
An integrated approach for accurate simulation and modeling of the silicide-source/drain structure and the silicide-diffusion contact resistanceApte, P.P. / Potla, S. / Prinslow, D.A. / Pollack, G. / Scott, D. / Varahramyan, K. et al. | 1998
- 733
-
Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact modelMeiKei Ieong, / Solomon, P.M. / Laux, S.E. / Wong, H.-S.P. / Chidambarrao, D. et al. | 1998
- 737
-
Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effectTiwari, S. / Welser, J.J. / Solomon, P.M. et al. | 1998
- 741
-
Optimization guidelines for epitaxial collectors of advanced BJT's with improved breakdown voltage and speedPalestri, P. / Fiegna, C. / Selmi, L. / Hurkx, G.A.M. / Slotboom, J.W. / Sangiorgi, E. et al. | 1998
- 747
-
Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETsLiu, C.T. et al. | 1998
- 747
-
Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs (Invited)Liu, C. / IEEE; Electron Devices Society et al. | 1998
- 751
-
A versatile 0.25 micron CMOS technologyPoon, S. / Atwell, C. / Hart, C. / Kolar, D. / Lage, C. / Yeargain, B. et al. | 1998
- 751
-
A Versatile 0.25 micron CMOS Technology (Invited)Poon, S. / Atwell, C. / Hart, C. / Kolar, D. / IEEE; Electron Devices Society et al. | 1998
- 755
-
1.5nm Equivalent Thickness Ta~2O~5 High-k Dielectric with Rugged Si Suited for Mass Production of High Density DRAMSAsano, I. / Kunitomo, M. / Yamamoto, S. / Furukawa, R. / IEEE; Electron Devices Society et al. | 1998
- 755
-
1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMsAsano, I. / Kunitomo, M. / Yamamoto, S. / Furukawa, R. / Sugawara, Y. / Uemura, T. / Kuroda, J. / Kanai, M. / Nakata, M. / Tamaru, T. et al. | 1998
- 759
-
High Levels of IC Manufacturability: One of the Necessary Prerequisites of the 1997 SIA Roadmap (Invited)Maly, W. / IEEE; Electron Devices Society et al. | 1998
- 759
-
High levels of IC manufacturability: one of the necessary prerequisites of the 1997 SIA Roadmap visionMaly, W. et al. | 1998
- 763
-
Statistical Modeling and Circuit Simulation for Design for Manufacturing (Invited)Smedes, T. / Emonts, P. / IEEE; Electron Devices Society et al. | 1998
- 763
-
Statistical modeling and circuit simulation for design for manufacturingSmedes, T. / Emonts, P.G.A. et al. | 1998
- 767
-
Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performanceMehrotra, V. / Nassif, S. / Chung, J. et al. | 1998
- 771
-
Explanation and Quantitative Model for the Matching Behavior of Poly-Silicon ResistorsThewes, R. / Brederlow, R. / Dahl, C. / Kollmer, U. / IEEE; Electron Devices Society et al. | 1998
- 771
-
Explanation and quantitative model for the matching behaviour of poly-silicon resistorsThewes, R. / Brederlow, R. / Dahl, C. / Kollmer, U. / Linnenbank, C.G. / Holzapfl, B. / Becker, J. / Kissing, J. / Kessel, S. / Weber, W. et al. | 1998
- 777
-
CMOS metal replacement gate transistors using tantalum pentoxide gate insulatorChatterjee, A. / Chapman, R.A. / Joyner, K. / Otobe, M. / Hattangady, S. / Bevan, M. / Brown, G.A. / Yang, H. / He, Q. / Rogers, D. et al. | 1998
- 781
-
PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technologyMaiti, B. / Tobin, P.J. / Hobbs, C. / Hegde, R.I. / Huang, F. / O'Meara, D.L. / Jovanovic, D. / Mendicino, M. / Chen, J. / Connelly, D. et al. | 1998
- 785
-
High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1m RegimeYagishita, A. / Saito, T. / Nakajima, K. / Inumiya, S. / IEEE; Electron Devices Society et al. | 1998
- 785
-
High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regimeYagishita, A. / Saito, T. / Nakajima, K. / Inumiya, S. / Akasaka, Y. / Ozawa, Y. / Minamihaba, G. / Yano, H. / Hieda, K. / Suguro, K. et al. | 1998
- 789
-
25 nm CMOS design considerationsTaur, Y. / Wann, C.H. / Frank, D.J. et al. | 1998
- 793
-
Reduced gate leakage current and boron penetration of 0.18 /spl mu/m 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectricHsing-Huang Tseng, / O'Meara, D.L. / Tobin, P.J. / Wang, V.S. / Xin Guo, / Hegde, R. / Yang, I.Y. / Gilbert, P. / Cotton, R. / Hebert, L. et al. | 1998
- 793
-
Reduced Gate Leakage Current and Boron Penetration of 0.18m 1.5V MOSFETs Using Integrated RTCVD Oxynitride Gate DielectricTseng, H. / O'Meara, D. / Tobin, P. / Wang, V. / IEEE; Electron Devices Society et al. | 1998
- 793
-
Reduced gate leakage current and boron penetration of 0.18 mu m 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectricTseng, Hsing-Huang / O'Meara, D.L. / Tobin, P.J. / Wang, V.S. / Xin Guo / Hegde, R. / Yang, I.Y. / Gilbert, P. / Cotton, R. / Hebert, L. et al. | 1998
- 797
-
Effect of barrier layer on the electrical and reliability characteristics of high-k gate dielectric filmsYongjoo Jeon, / Zawadzki, K. / Wen-Jie Qi, / Lucas, A. / Nieh, R. / Lee, J.C. et al. | 1998
- 803
-
(Ba,Sr)TiO/sub 3/ capacitor technology for Gbit-scale DRAMsOno, K. / Horikawa, T. / Shibano, T. / Mikami, N. / Kuroiwa, T. / Kawahara, T. / Matsuno, S. / Uchikawa, F. / Satoh, S. / Abe, H. et al. | 1998
- 803
-
(Ba,Sr)TiO~3 Capacitor Technology for Gbit-Scale DRAMs (Invited)Ono, K. / Horikawa, T. / Shibano, T. / Mikami, N. / IEEE; Electron Devices Society et al. | 1998
- 807
-
All Perovskite Capacitor (APEC) Technology for (Ba,Sr)TiO~3 Capacitor Scaling Toward 0.10m Stacked DRAMsHieda, K. / Eguchi, K. / Fukushima, N. / Aoyama, T. / IEEE; Electron Devices Society et al. | 1998
- 807
-
All perovskite capacitor (APEC) technology for (Ba,Sr)TiO/sub 3/ capacitor scaling toward 0.10 /spl mu/m stacked DRAMsHieda, K. / Eguchi, K. / Fukushima, N. / Aoyama, T. / Natori, K. / Kiyotoshi, M. / Yamazaki, S. / Izuha, M. / Niwa, S. / Fukuzumi, Y. et al. | 1998
- 811
-
A manufacturable integration technology of sputter-BST capacitor with a newly proposed thick Pt electrodeTsunemine, Y. / Okudaira, T. / Kashihara, K. / Hanafusa, K. / Yutani, A. / Fujita, Y. / Matsushita, M. / Itoh, H. / Miyoshi, H. et al. | 1998
- 815
-
Integration Processes of (Ba,Sr)TiO~3 Capacitor for 1 Gb and BeyondLee, B. / Yoo, C. / Lim, H. / Lee, K. / IEEE; Electron Devices Society et al. | 1998
- 815
-
Integration processes of (Ba,Sr)TiO/sub 3/ capacitor for 1 Gb and beyond [DRAMs]Byoung Taek Lee, / Cha Young Yoo, / Han Jin Lim, / Chang Seok Kang, / Hong Bae Park, / Wan Don Kim, / Suk Ho Ju, / Horii, H. / Ki Hoon Lee, / Hyun Woo Kim, et al. | 1998
- 819
-
Sputtering process design of PZT capacitors for stable FeRAM operationInoue, N. / Takeuchi, T. / Hayashi, Y. et al. | 1998
- 823
-
Advanced dielectrics for gate oxide, DRAM and RF capacitorsvan Dover, R.B. / Fleming, R.M. / Alers, G.B. / Werder, D.J. et al. | 1998
- 829
-
The best combination of aluminum and copper interconnects for a high performance 0.18 /spl mu/m CMOS logic deviceIgarashi, M. / Harada, A. / Amishiro, H. / Kawashima, H. / Kusumi, Y. / Saito, T. / Ohsaki, A. / Mori, T. / Fukada, T. / Toyoda, Y. et al. | 1998
- 829
-
The Best Combination of Aluminum and Copper Interconnects for a High Performance 0.18m CMOS Logic DeviceIgarashi, M. / Harada, A. / Amishiro, H. / Kawashima, H. / IEEE; Electron Devices Society et al. | 1998
- 833
-
Interconnect Design Strategy: Structures, Repeaters and Materials Toward 0.1m ULSIs with a Giga-Hertz Clock OperationTakahashi, S. / Edahiro, M. / Hayashi, Y. / IEEE; Electron Devices Society et al. | 1998
- 833
-
Interconnect design strategy: structures, repeaters and materials toward 0.1 /spl mu/m ULSIs with a giga-hertz clock operationTakahashi, S. / Edahiro, M. / Hayashi, Y. et al. | 1998
- 837
-
Advanced interconnect scheme analysis: real impact of technological improvementsLecarval, G. / Morand, Y. / Roger, F. / Rivallin, P. / Poncet, D. et al. | 1998
- 841
-
RC delay reduction of 0.18 /spl mu/m CMOS technology using low dielectric constant fluorinated amorphous carbonMatsubara, Y. / Kishimoto, K. / Endo, K. / Iguchi, M. / Tatsumi, T. / Gomi, H. / Horiuchi, T. / Tzou, E. / Xi, M. / Cheng, L.Y. et al. | 1998
- 841
-
RC Delay Reduction of 0.18m CMOS Technology Using Low Dielectric Constant Fluorinated Amorphous CarbonMatsubara, Y. / Kishimoto, K. / Endo, K. / Icjuchi, M. / IEEE; Electron Devices Society et al. | 1998
- 845
-
Novel co-sputtered fluorinated amorphous carbon films for sub-0.25 /spl mu/m low /spl kappa/ damascene multilevel interconnect applicationsZhu, W. / Pai, C.S. / Bair, H.E. / Krautter, H.W. / Opila, R.L. / Dennis, B.S. / Pinczuk, A. / Chabal, Y.J. / Grundmeier, G. / Graebner, J.E. et al. | 1998
- 845
-
Novel co-sputtered fluorinated amorphous carbon films for sub-0.25 mu m low kappa damascene multilevel interconnect applicationsZhu, W. / Pai, C.S. / Bair, H.E. / Krautter, H.W. / Opila, R.L. / Dennis, B.S. / Pinczuk, A. / Chabal, Y.J. / Grundmeier, G. / Graebner, J.E. et al. | 1998
- 845
-
Novel Co-Sputtered Fluorinated Amorphous Carbon Films for Sub-0.25m Low k Damascene Multilevel Interconnect ApplicationsZhu, W. / Pai, C. / Bair, H. / Krautter, H. / IEEE; Electron Devices Society et al. | 1998
- 849
-
Shared tungsten structures for FEOL/BEOL compatibility in logic-friendly merged DRAMDrynan, J.M. / Fukui, K. / Hamada, M. / Inoue, K. / Kamiyama, S. / Matsumoto, A. / Nobusawa, H. / Sugai, K. / Takenaka, M. / Yamaguchi, H. et al. | 1998
- 855
-
100 nm aperture field emitter arrays for low voltage applicationsPflug, D.G. / Schattenburg, M. / Smith, H.I. / Akinwande, I. et al. | 1998
- 855
-
100nm Aperture Field Emmitter Arrays for Low Voltage ApplicationsPflug, D. / Schattenburg, M. / Smith, H. / Akinwande, A. / IEEE; Electron Devices Society et al. | 1998
- 859
-
Si field emitter array with 90-nm-diameter gate holesTakemura, H. / Yoshiki, M. / Furutake, N. / Tomihari, Y. / Okamoto, A. / Miyano, S. et al. | 1998
- 863
-
An efficient 3-dimensional CAD tool for field-emission devicesYao-Joe Yang, / Korsmeyer, F.T. / Rabinovich, V. / Meng Ding, / Senturia, S.D. / Akinwande, A.I. et al. | 1998
- 867
-
Analysis of low threshold field-emission from conjugated polymers for displaysMusa, I. / Eccleston, W. / Amaratunga, G.A.J. et al. | 1998
- 871
-
Polysilicon VGA active matrix OLED displays-technology and performanceStewart, M. / Howell, R.S. / Pires, L. / Hatalis, M.K. / Howard, W. / Prache, O. et al. | 1998
- 875
-
The impact of the transient response of organic light emitting diodes on the design of active matrix OLED displaysDawson, R.M.A. / Shen, Z. / Furst, D.A. / Connor, S. / Hsu, J. / Kane, M.G. / Stewart, R.G. / Ipri, A. / King, C.N. / Green, P.J. et al. | 1998
- 879
-
Thermal, self-heating and kink effects in a-Si:H thin film transistorsIniguez, B. / Wang, L. / Fjeldly, T.A. / Shur, M.S. / Slade, H. et al. | 1998
- 885
-
Energy dependent electron and hole impact ionization in Si bipolar transistorsPalestri, P. / Selmi, L. / Sangiorgi, E. et al. | 1998
- 889
-
The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memoryKencke, D.L. / Wang, X. / Wang, H. / Ouyang, Q. / Jallepalli, S. / Rashed, M. / Maziar, C. / Tasch, A. / Banerjee, S.K. et al. | 1998
- 893
-
Monte Carlo simulation of hot-carrier degradation in scaled MOS transistors for VLSI technologyGhetti, A. / Bude, J. / Liu, C.T. et al. | 1998
- 897
-
Full-Band Monte Carlo Simulation of a 0.12m-Si-PMOSFET with and without a Strained SiGe-ChannelJungemann, C. / Keith, S. / Meinerzhagen, B. / IEEE; Electron Devices Society et al. | 1998
- 897
-
Full-band Monte Carlo simulation of a 0.12 /spl mu/m-Si-PMOSFET with and without a strained SiGe-channelJungemann, C. / Keith, S. / Meinerzhagen, B. et al. | 1998
- 901
-
A new model of tunnelling current and SILC in ultra-thin oxidesLarcher, L. / Paccagnella, A. / Scarpa, A. / Ghidini, G. et al. | 1998
- 905
-
Monte Carlo simulation of stress-induced leakage current by hopping conduction via multi-traps in oxideOkuyama, Y. / Kamohara, S. / Manabe, Y. / Okuyama, K. / Kubota, Y. / Kobayashi, T. / Kimura, K. et al. | 1998
- 909
-
Analysis of the gate voltage fluctuations in ultra-thin gate oxides after soft breakdownHoussa, M. / Vandewalle, N. / Nigam, T. / Ausloos, M. / Mertens, P.W. / Heyns, M.M. et al. | 1998
- 915
-
Transistor Matching in Analog CMOS Applications (Invited)Pelgrom, M. / Tuinhout, H. / Vertregt, M. / IEEE; Electron Devices Society et al. | 1998
- 915
-
Transistor matching in analog CMOS applicationsPelgrom, M.J.M. / Tuinhout, H.P. / Vertregt, M. et al. | 1998
- 919
-
Threshold voltage fluctuation induced by direct tunnel leakage current through 1.2-2.8 nm thick gate oxides for scaled MOSFETsIwamoto, K. / Ono, T. / Mihara, T. / Miyazaki, S. / Miura, M.M. / Hirose, M. et al. | 1998
- 923
-
A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regimeMomose, H.S. / Kimijima, H. / Ishizuka, S. / Miyahara, Y. / Ohguro, T. / Yoshitomi, T. / Morifuji, E. / Nakamura, S. / Morimoto, T. / Katsumata, Y. et al. | 1998
- 927
-
0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technologyOhguro, T. / Naruse, H. / Sugaya, H. / Kimijima, H. / Morifuji, E. / Yoshitomi, T. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1998
- 927
-
0.12m Raised Gate/Source/Drain Epitaxial Channel NMOS TechnologyOhguro, T. / Naruse, H. / Sugaya, H. / Kimijima, H. / IEEE; Electron Devices Society et al. | 1998
- 931
-
Hot Carrier Reliability Considerations in the Integration of Dual Gate Oxide Transistor Process on a Su 0.25m CMOS Technology for Embedded ApplicationsBhat, N. / Chen, P. / Tsui, P. / Das, A. / IEEE; Electron Devices Society et al. | 1998
- 931
-
Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applicationsBhat, N. / Chen, P. / Tsui, P. / Das, A. / Foisy, M. / Shiho, Y. / Higman, J. / Nguyen, J.-Y. / Gonzales, S. / Collins, S. et al. | 1998
- 935
-
Multi-level metal CMOS manufacturing with deuterium for improved hot carrier reliabilityKizilyalli, I.C. / Weber, G. / Chen, Z. / Abeln, G. / Kotzias, B. / Register, F. / Harris, E. / Sen, S. / Chetlur, S. / Patel, M. et al. | 1998
- 939
-
Reliability of vertical MOSFETs for gigascale memory applicationsGoebel, B. / Bertagnolli, E. / Koch, F. et al. | 1998
- 945
-
A Novel High-Efficiency Quasi-SOI Power MOSFET for Multi-Gigahertz ApplicationMatsumoto, S. / Ishiyama, T. / Hiraoka, Y. / Sakai, T. / IEEE; Electron Devices Society et al. | 1998
- 945
-
A novel high-frequency quasi-SOI power MOSFET for multi-gigahertz applicationsMatsumoto, S. / Ishiyama, T. / Hiraoka, Y. / Sakai, T. / Yachi, T. / Kamitsuna, H. / Muraguchi, M. et al. | 1998
- 949
-
Device Design Methodology to Optimize Low-Frequenccy Noise in Advanced SOI CMOS Technology for RF ICsTseng, Y. / Huang, W. / Mendicino, M. / Ngo, D. / IEEE; Electron Devices Society et al. | 1998
- 949
-
Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF ICsYing-Che Tseng, / Huang, W.M. / Ngo, D. / Ilderem, V. / Woo, J.C.S. et al. | 1998
- 953
-
A 31 GHz f~m~a~x Lateral BJT on SOI Using Self-Aligned External Base Formation TechnologyShino, T. / Inoh, K. / Yamada, T. / Nii, H. / IEEE; Electron Devices Society et al. | 1998
- 953
-
A 31 GHz f/sub max/ lateral BJT on SOI using self-aligned external base formation technologyShino, T. / Inoh, K. / Yamada, T. / Nii, H. / Kawanaka, S. / Fuse, T. / Yoshimi, M. / Katsumata, Y. / Watanabe, S. / Matsunaga, J. et al. | 1998
- 957
-
Record power added efficiency of bipolar power transistors for low voltage wireless applicationsvan Rijs, F. / Visser, H.A. / Magnee, P.H.C. et al. | 1998
- 961
-
An effective gate resistance model for CMOS RF and noise modelingXiaodong Jin, / Jia-Jiunn Ou, / Chih-Hung Chen, / Weidong Liu, / Deen, M.J. / Gray, P.R. / Chenming Hu, et al. | 1998
- 965
-
Process induced damage on RFCMOSMorifuji, E. / Ohguro, T. / Yoshitomi, T. / Kimijima, H. / Morimoto, T. / Momose, H.S. / Katsumata, Y. / Iwai, H. et al. | 1998
- 971
-
Flash Memories: Where We Were and Where We Are Going (Invited)Lai, S. / IEEE; Electron Devices Society et al. | 1998
- 971
-
Flash memories: where we were and where we are goingLai, S. et al. | 1998
- 975
-
Novel 0.44m^2 Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded ApplicationWatanabe, H. / Yamada, S. / Tanimoto, M. / Matsui, M. / IEEE; Electron Devices Society et al. | 1998
- 975
-
Novel 0.44 /spl mu/m/sup 2/ Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded applicationYamada, S. / Tanimoto, M. / Matsui, M. / Kitamura, S. / Amemiya, K. / Tanzawa, T. / Sakagami, E. / Kurata, M. / Isobe, K. / Takebuchi, M. et al. | 1998
- 979
-
A novel 4.6F/sup 2/ NOR cell technology with lightly doped source (LDS) junction for high density flash memoriesJonghan Kim, / Jeong-Hyuk Choi, / Yong-Ju Choi, / Hun-Kyu Lee, / Kyeong-Tae Kim, / Yun-Seung Shin, et al. | 1998
- 979
-
A Novel 4.6F^2 NOR Cell Technology with Lightly Doped Source (LDS) Junction for High Density Flash MemoriesKim, J. / Choi, J. / Choi, Y. / Lee, H. / IEEE; Electron Devices Society et al. | 1998
- 983
-
An advanced flash memory technology on SOIBurnett, D. / Shum, D. / Baker, K. et al. | 1998
- 987
-
Low voltage, low current, high speed program step split gate cell with ballistic direct injection for EEPROM/flashOgura, S. / Hori, A. / Kato, J. / Yamanaka, M. / Odanaka, S. / Fujimoto, H. / Akamatsu, K. / Ogura, T. / Kojima, M. / Kotani, H. et al. | 1998
- 991
-
Flexible Hot-Electron Programming of Flash Memory CellsEsseni, D. / Ricco, B. / IEEE; Electron Devices Society et al. | 1998
- 991
-
Flexible hot-electron programming of flash memoriesEsseni, D. / Ricco, B. et al. | 1998
- 995
-
0.13 /spl mu/m MONOS single transistor memory cell with separated source linesFujiwara, I. / Aozasa, H. / Nakamura, A. / Komatsu, Y. / Hayashi, Y. et al. | 1998
- 995
-
0.13m MONOS Single Transistor Memory Cell with Separated Source LinesFujiwara, I. / Aozasa, H. / Nakamura, A. / Komatsu, Y. / IEEE; Electron Devices Society et al. | 1998
- 1001
-
SOI MOSFET on low cost SPIMOX substrateIyer, S.S.K. / Xiang Lu, / Cheung, N.W. / Chenming Hu, et al. | 1998
- 1005
-
High thermal stability and low junction leakage current of Ti capped Co salicide and its feasibility for high thermal budget CMOS devicesDong Kyun Sohn, / Ji-Soo Park, / Byung Hak Lee, / Jong-Uk Bae, / Kyung Soo Oh, / Seh Kwang Lee, / Jeong Soo Byun, / Jae Jeong Kim, et al. | 1998
- 1009
-
Ultra-shallow junction formation by outdiffusion from implanted oxideSchmitz, J. / van Gestel, M. / Stolk, P.A. / Ponomarev, Y.V. / Roozeboom, F. / Woerlee, P.H. et al. | 1998
- 1013
-
A High Performance 1.5V, 0.10m Gate Length CMOS Technology with Scaled Copper MetallizationGilbert, P. / Yang, I. / Pettinato, C. / Angyal, M. / IEEE; Electron Devices Society et al. | 1998
- 1013
-
A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallizationGilbert, P. / Yang, I. / Pettinato, C. / Angyal, M. / Boeck, B. / Fu, C. / VanGompel, T. / Tiwari, R. / Sparks, T. / Clark, W. et al. | 1998
- 1017
-
Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOLCrowder, S. / Hannon, R. / Ho, H. / Sinitsky, D. / Wu, S. / Winstel, K. / Khan, B. / Stiffler, S.R. / Iyer, S.S. et al. | 1998
- 1017
-
Integration of Trench DRAM into a High-Performance 0.18m Logic Technology with Copper BEOLCrowder, S. / Hannon, R. / Ho, H. / Sinitsky, D. / IEEE; Electron Devices Society et al. | 1998
- 1023
-
A novel high-gain CMOS image sensor using floating N-well/gate tied PMOSFETWeiquan Zhang, / Mansun Chan, / Ko, P.K. et al. | 1998
- 1026
-
31% absolute external quantum efficiency 850-nm LEDs and their modulation behaviorWindisch, R. / Heremans, P. / Potemans, J. / Knobloch, A. / Dutta, B. / Dohler, G.H. / Borghs, G. et al. | 1998
- 1029
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Embedded DRAM technology compatible to the 0.13 mu m high-speed logics by using Ru pillars in cell capacitors and peripheral viasNakamura, S. / Kosugi, M. / Shido, H. / Kosemura, K. / Satoh, A. / Minakata, H. / Tsunoda, H. / Kobayashi, M. / Kurahashi, T. / Hatada, A. et al. | 1998
- 1029
-
Embedded DRAM Technology Comparable to the 0.13m High-Speed Logics by Using Ru pallars in Cell Capacitors and Peripheral viasNakamura, S. / Kosugi, M. / Shido, H. / Kosemura, K. / IEEE; Electron Devices Society et al. | 1998
- 1029
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Embedded DRAM technology compatible to the 0.13 /spl mu/m high-speed logics by using Ru pillars in cell capacitors and peripheral viasNakamura, S. / Kosugi, M. / Shido, H. / Kosemura, K. / Satoh, A. / Minakata, H. / Tsunoda, H. / Kobayashi, M. / Kurahashi, T. / Hatada, A. et al. | 1998
- 1032
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A Folded Channel MOSFET for Deep-Sub-Tenth Micron EraHisamoto, D. / Lee, W. C. / Kedzierski, J. / Anderson, E. / IEEE; Electron Devices Society et al. | 1998